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GET /api/patches/108231/?format=api
{ "id": 108231, "url": "http://patches.dpdk.org/api/patches/108231/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220224061044.1140750-1-vattunuru@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220224061044.1140750-1-vattunuru@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220224061044.1140750-1-vattunuru@marvell.com", "date": "2022-02-24T06:10:44", "name": "[1/1] net/cnxk: add outb soft expiry notification support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "cc091c61b432f1b8c504bc42739d3b051cf4d16d", "submitter": { "id": 1277, "url": "http://patches.dpdk.org/api/people/1277/?format=api", "name": "Vamsi Krishna Attunuru", "email": "vattunuru@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220224061044.1140750-1-vattunuru@marvell.com/mbox/", "series": [ { "id": 21843, "url": "http://patches.dpdk.org/api/series/21843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21843", "date": "2022-02-24T06:10:44", "name": "[1/1] net/cnxk: add outb soft expiry notification support", "version": 1, "mbox": "http://patches.dpdk.org/series/21843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/108231/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/108231/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 066CDA0353;\n\tThu, 24 Feb 2022 07:11:00 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C10EC4114D;\n\tThu, 24 Feb 2022 07:10:59 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 92B8740E5A\n for <dev@dpdk.org>; Thu, 24 Feb 2022 07:10:58 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 21O4ZteC003830\n for <dev@dpdk.org>; Wed, 23 Feb 2022 22:10:57 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3edjga524x-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 23 Feb 2022 22:10:57 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Wed, 23 Feb 2022 22:10:56 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 23 Feb 2022 22:10:56 -0800", "from localhost.localdomain (unknown [10.28.48.51])\n by maili.marvell.com (Postfix) with ESMTP id 54CE15B6927;\n Wed, 23 Feb 2022 22:10:54 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=HlBtnJPBYiXjj/2Mo6GCc0DxnUzu0PZ/jcCq5+M/A5I=;\n b=LMOSs/LuCw263T0kpRx0c6klPDSyZgtHuPuPHnoAVlzCuAKkcEcvvGnKdLViCsW7jkpq\n EifFfV9WkshwUUymO/tNz0w4YuIzI70Aeic3M8fLryVSCvih+kTzHrWvFGugrK/w5+Rt\n zaw9m9qDnpBKlR8Ad4ocusgqjBT4DkswIeFTQM+Yj7/DR6MX97wNWD92wRQQsjxelhLt\n GI8uSwEwLBqUjJET1Kntz6UyX7cfx4JyJgKdoDbq6PBTh/1cO4rwnGs+jjIS6CLN/CTC\n X7V58UbZ9vAeiA0xENJ382Icbt1gsqzosc9ehKAMaM+8HT/pAoj2sGtB7I2/8sZM4wc4 bA==", "From": "Vamsi Attunuru <vattunuru@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <ndabilpuram@marvell.com>, <vattunuru@marvell.com>", "Subject": "[PATCH 1/1] net/cnxk: add outb soft expiry notification support", "Date": "Thu, 24 Feb 2022 11:40:44 +0530", "Message-ID": "<20220224061044.1140750-1-vattunuru@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "SfTk5pR9c8LtCQv0AYh4TOnK6f-Rkbt3", "X-Proofpoint-GUID": "SfTk5pR9c8LtCQv0AYh4TOnK6f-Rkbt3", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514\n definitions=2022-02-23_09,2022-02-23_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Patch implements soft expiry notification mechanism in out bound\npath by creating required number of ring buffers and a common poll\nthread which polls for soft expiry events enqueued by ucode.\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/common/cnxk/roc_idev.c | 15 +++\n drivers/common/cnxk/roc_idev.h | 2 +\n drivers/common/cnxk/roc_ie_ot.h | 25 +++-\n drivers/common/cnxk/roc_nix_inl.c | 71 +++++++++++\n drivers/common/cnxk/roc_nix_inl.h | 20 ++-\n drivers/common/cnxk/roc_nix_inl_dev.c | 146 +++++++++++++++++++++-\n drivers/common/cnxk/roc_nix_inl_dev_irq.c | 2 +-\n drivers/common/cnxk/roc_nix_inl_priv.h | 13 ++\n drivers/common/cnxk/roc_nix_priv.h | 2 +\n drivers/common/cnxk/roc_platform.h | 3 +\n drivers/common/cnxk/version.map | 2 +\n drivers/net/cnxk/cn10k_ethdev_sec.c | 52 +++++++-\n drivers/net/cnxk/cnxk_ethdev.c | 4 +\n drivers/net/cnxk/cnxk_ethdev_sec.c | 1 +\n 14 files changed, 350 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex b1f38fb5fc..a08c7ce8fd 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -185,6 +185,21 @@ roc_idev_cpt_get(void)\n \treturn NULL;\n }\n \n+uint64_t *\n+roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (!idev || !idev->nix_inl_dev)\n+\t\treturn NULL;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\n+\treturn (uint64_t *)&inl_dev->sa_soft_exp_ring[nix->outb_se_ring_base];\n+}\n+\n void\n roc_idev_cpt_set(struct roc_cpt *cpt)\n {\ndiff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h\nindex 16793c2828..7e0beed495 100644\n--- a/drivers/common/cnxk/roc_idev.h\n+++ b/drivers/common/cnxk/roc_idev.h\n@@ -17,4 +17,6 @@ void __roc_api roc_idev_cpt_set(struct roc_cpt *cpt);\n \n struct roc_nix *__roc_api roc_idev_npa_nix_get(void);\n \n+uint64_t *__roc_api roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix);\n+\n #endif /* _ROC_IDEV_H_ */\ndiff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h\nindex c502c7983f..537eafbe79 100644\n--- a/drivers/common/cnxk/roc_ie_ot.h\n+++ b/drivers/common/cnxk/roc_ie_ot.h\n@@ -176,6 +176,28 @@ enum {\n \t(PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) / \\\n \t BITS_PER_LONG_LONG)\n \n+#define ROC_IPSEC_ERR_RING_MAX_ENTRY 65536\n+\n+union roc_ot_ipsec_err_ring_head {\n+\tuint64_t u64;\n+\tstruct {\n+\t\tuint16_t tail_pos;\n+\t\tuint16_t tail_gen;\n+\t\tuint16_t head_pos;\n+\t\tuint16_t head_gen;\n+\t} s;\n+};\n+\n+union roc_ot_ipsec_err_ring_entry {\n+\tuint64_t u64;\n+\tstruct {\n+\t\tuint64_t data0 : 44;\n+\t\tuint64_t data1 : 9;\n+\t\tuint64_t rsvd : 3;\n+\t\tuint64_t comp_code : 8;\n+\t} s;\n+};\n+\n /* Common bit fields between inbound and outbound SA */\n union roc_ot_ipsec_sa_word2 {\n \tstruct {\n@@ -428,7 +450,8 @@ struct roc_ot_ipsec_outb_sa {\n \t\t\tuint64_t count_mib_pkts : 1;\n \t\t\tuint64_t hw_ctx_off : 7;\n \n-\t\t\tuint64_t rsvd1 : 32;\n+\t\t\tuint64_t ctx_id : 16;\n+\t\t\tuint64_t rsvd1 : 16;\n \n \t\t\tuint64_t ctx_push_size : 7;\n \t\t\tuint64_t rsvd2 : 1;\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex e8981c4aa4..0d9e5dd5c4 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -5,6 +5,8 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n+uint32_t soft_exp_consumer_cnt;\n+\n PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ ==\n \t\t 1UL << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2);\n PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ == 512);\n@@ -394,6 +396,34 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)\n \tnix->nb_cpt_lf = nb_lf;\n \tnix->outb_err_sso_pffunc = sso_pffunc;\n \tnix->inl_outb_ena = true;\n+\tnix->outb_se_ring_cnt =\n+\t\troc_nix->ipsec_out_max_sa / ROC_IPSEC_ERR_RING_MAX_ENTRY + 1;\n+\tnix->outb_se_ring_base =\n+\t\troc_nix->port_id * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS;\n+\n+\tif (inl_dev == NULL) {\n+\t\tnix->outb_se_ring_cnt = 0;\n+\t\treturn 0;\n+\t}\n+\n+\t/* Allocate memory to be used as a ring buffer to poll for\n+\t * soft expiry event from ucode\n+\t */\n+\tfor (i = 0; i < nix->outb_se_ring_cnt; i++) {\n+\t\tinl_dev->sa_soft_exp_ring[nix->outb_se_ring_base + i] =\n+\t\t\tplt_zmalloc((ROC_IPSEC_ERR_RING_MAX_ENTRY + 1) *\n+\t\t\t\t\t sizeof(uint64_t),\n+\t\t\t\t 0);\n+\t\tif (!inl_dev->sa_soft_exp_ring[i]) {\n+\t\t\tplt_err(\"Couldn't allocate memory for soft exp ring\");\n+\t\t\twhile (i--)\n+\t\t\t\tplt_free(inl_dev->sa_soft_exp_ring\n+\t\t\t\t\t\t [nix->outb_se_ring_base + i]);\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto lf_fini;\n+\t\t}\n+\t}\n+\n \treturn 0;\n \n lf_fini:\n@@ -412,7 +442,9 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct roc_cpt_lf *lf_base = nix->cpt_lf_base;\n+\tstruct idev_cfg *idev = idev_get_cfg();\n \tstruct dev *dev = &nix->dev;\n+\tstruct nix_inl_dev *inl_dev;\n \tint i, rc, ret = 0;\n \n \tif (!nix->inl_outb_ena)\n@@ -444,6 +476,15 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix)\n \tplt_free(nix->outb_sa_base);\n \tnix->outb_sa_base = NULL;\n \n+\tif (idev && idev->nix_inl_dev) {\n+\t\tinl_dev = idev->nix_inl_dev;\n+\n+\t\tfor (i = 0; i < ROC_NIX_INL_MAX_SOFT_EXP_RNGS; i++) {\n+\t\t\tif (inl_dev->sa_soft_exp_ring[i])\n+\t\t\t\tplt_free(inl_dev->sa_soft_exp_ring[i]);\n+\t\t}\n+\t}\n+\n \tret |= rc;\n \treturn ret;\n }\n@@ -628,6 +669,36 @@ roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev)\n \tnix->inb_inl_dev = use_inl_dev;\n }\n \n+int\n+roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix, bool poll)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\tuint16_t ring_idx, i;\n+\n+\tif (!idev || !idev->nix_inl_dev)\n+\t\treturn 0;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\n+\tfor (i = 0; i < nix->outb_se_ring_cnt; i++) {\n+\t\tring_idx = nix->outb_se_ring_base + i;\n+\n+\t\tif (poll)\n+\t\t\tplt_bitmap_set(inl_dev->soft_exp_ring_bmap, ring_idx);\n+\t\telse\n+\t\t\tplt_bitmap_clear(inl_dev->soft_exp_ring_bmap, ring_idx);\n+\t}\n+\n+\tif (poll)\n+\t\tsoft_exp_consumer_cnt++;\n+\telse\n+\t\tsoft_exp_consumer_cnt--;\n+\n+\treturn 0;\n+}\n+\n bool\n roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex abbeac684a..3c23f611c3 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -43,6 +43,18 @@\n /* Alignment of SA Base */\n #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)\n \n+#define ROC_NIX_INL_SA_SOFT_EXP_ERR_MAX_POLL_COUNT 25\n+\n+#define ROC_NIX_SOFT_EXP_ERR_RING_MAX_ENTRY_LOG2 16\n+\n+#define ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS 4\n+\n+#define ROC_NIX_MAX_TOTAL_OUTB_IPSEC_SA \\\n+\t(ROC_IPSEC_ERR_RING_MAX_ENTRY * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS)\n+\n+#define ROC_NIX_INL_MAX_SOFT_EXP_RNGS \\\n+\t(PLT_MAX_ETHPORTS * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS)\n+\n static inline struct roc_onf_ipsec_inb_sa *\n roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx)\n {\n@@ -100,7 +112,8 @@ roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa)\n }\n \n /* Inline device SSO Work callback */\n-typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args);\n+typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args,\n+\t\t\t\t\t uint32_t soft_exp_event);\n \n struct roc_nix_inl_dev {\n \t/* Input parameters */\n@@ -111,9 +124,10 @@ struct roc_nix_inl_dev {\n \tuint16_t channel;\n \tuint16_t chan_mask;\n \tbool attach_cptlf;\n+\tbool set_soft_exp_poll;\n \t/* End of input parameters */\n \n-#define ROC_NIX_INL_MEM_SZ (1280)\n+#define ROC_NIX_INL_MEM_SZ (2304)\n \tuint8_t reserved[ROC_NIX_INL_MEM_SZ] __plt_cache_aligned;\n } __plt_cache_aligned;\n \n@@ -157,6 +171,8 @@ uint16_t __roc_api roc_nix_inl_outb_sso_pffunc_get(struct roc_nix *roc_nix);\n int __roc_api roc_nix_inl_cb_register(roc_nix_inl_sso_work_cb_t cb, void *args);\n int __roc_api roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb,\n \t\t\t\t\tvoid *args);\n+int __roc_api roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix,\n+\t\t\t\t\t\t bool poll);\n /* NIX Inline/Outbound API */\n enum roc_nix_inl_sa_sync_op {\n \tROC_NIX_INL_SA_OP_FLUSH,\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex dd93765a2b..10f237f9b1 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -13,6 +13,9 @@\n \t ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 | \\\n \t ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3)\n \n+extern uint32_t soft_exp_consumer_cnt;\n+static bool soft_exp_poll_thread_exit = true;\n+\n uint16_t\n nix_inl_dev_pffunc_get(void)\n {\n@@ -28,10 +31,11 @@ nix_inl_dev_pffunc_get(void)\n }\n \n static void\n-nix_inl_selftest_work_cb(uint64_t *gw, void *args)\n+nix_inl_selftest_work_cb(uint64_t *gw, void *args, uint32_t soft_exp_event)\n {\n \tuintptr_t work = gw[1];\n \n+\t(void)soft_exp_event;\n \t*((uintptr_t *)args + (gw[0] & 0x1)) = work;\n \n \tplt_atomic_thread_fence(__ATOMIC_ACQ_REL);\n@@ -518,6 +522,133 @@ nix_inl_lf_detach(struct nix_inl_dev *inl_dev)\n \treturn mbox_process(dev->mbox);\n }\n \n+static void\n+inl_outb_soft_exp_poll(struct nix_inl_dev *inl_dev, uint32_t ring_idx)\n+{\n+\tunion roc_ot_ipsec_err_ring_head head;\n+\tstruct roc_ot_ipsec_outb_sa *sa;\n+\tuint16_t head_l, tail_l;\n+\tuint64_t *ring_base;\n+\tuint32_t port_id;\n+\n+\tport_id = ring_idx / ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS;\n+\tring_base = inl_dev->sa_soft_exp_ring[ring_idx];\n+\tif (!ring_base) {\n+\t\tplt_err(\"Invalid soft exp ring base\");\n+\t\treturn;\n+\t}\n+\n+\thead.u64 = __atomic_load_n(ring_base, __ATOMIC_ACQUIRE);\n+\thead_l = head.s.head_pos;\n+\ttail_l = head.s.tail_pos;\n+\n+\twhile (tail_l != head_l) {\n+\t\tunion roc_ot_ipsec_err_ring_entry entry;\n+\t\tint poll_counter = 0;\n+\n+\t\twhile (poll_counter++ <\n+\t\t ROC_NIX_INL_SA_SOFT_EXP_ERR_MAX_POLL_COUNT) {\n+\t\t\tplt_delay_us(20);\n+\t\t\tentry.u64 = __atomic_load_n(ring_base + tail_l + 1,\n+\t\t\t\t\t\t __ATOMIC_ACQUIRE);\n+\t\t\tif (likely(entry.u64))\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tentry.u64 = plt_be_to_cpu_64(entry.u64);\n+\t\tsa = (struct roc_ot_ipsec_outb_sa *)(((uint64_t)entry.s.data1\n+\t\t\t\t\t\t << 51) |\n+\t\t\t\t\t\t (entry.s.data0 << 7));\n+\n+\t\tif (sa != NULL) {\n+\t\t\tuint64_t tmp = ~(uint32_t)0x0;\n+\t\t\tinl_dev->work_cb(&tmp, sa, (port_id << 8) | 0x1);\n+\t\t\t__atomic_store_n(ring_base + tail_l + 1, 0ULL,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n+\t\t\t__atomic_add_fetch((uint32_t *)ring_base, 1,\n+\t\t\t\t\t __ATOMIC_ACQ_REL);\n+\t\t} else\n+\t\t\tplt_err(\"Invalid SA\");\n+\n+\t\ttail_l++;\n+\t}\n+}\n+\n+static void *\n+nix_inl_outb_poll_thread(void *args)\n+{\n+\tstruct nix_inl_dev *inl_dev = args;\n+\tuint32_t poll_freq;\n+\tuint32_t i;\n+\tbool bit;\n+\n+\tpoll_freq = inl_dev->soft_exp_poll_freq;\n+\n+\twhile (!soft_exp_poll_thread_exit) {\n+\t\tif (soft_exp_consumer_cnt) {\n+\t\t\tfor (i = 0; i < ROC_NIX_INL_MAX_SOFT_EXP_RNGS; i++) {\n+\t\t\t\tbit = plt_bitmap_get(\n+\t\t\t\t\tinl_dev->soft_exp_ring_bmap, i);\n+\t\t\t\tif (bit)\n+\t\t\t\t\tinl_outb_soft_exp_poll(inl_dev, i);\n+\t\t\t}\n+\t\t}\n+\t\tplt_delay_us(poll_freq);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct plt_bitmap *bmap;\n+\tsize_t bmap_sz;\n+\tuint32_t i;\n+\tvoid *mem;\n+\tint rc;\n+\n+\t/* Allocate a bitmap that pool thread uses to get the port_id\n+\t * that's corresponding to the inl_outb_soft_exp_ring\n+\t */\n+\tbmap_sz =\n+\t\tplt_bitmap_get_memory_footprint(ROC_NIX_INL_MAX_SOFT_EXP_RNGS);\n+\tmem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);\n+\tif (mem == NULL) {\n+\t\tplt_err(\"soft expiry ring bmap alloc failed\");\n+\t\trc = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n+\n+\tbmap = plt_bitmap_init(ROC_NIX_INL_MAX_SOFT_EXP_RNGS, mem, bmap_sz);\n+\tif (!bmap) {\n+\t\tplt_err(\"soft expiry ring bmap init failed\");\n+\t\tplt_free(mem);\n+\t\trc = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n+\n+\tinl_dev->soft_exp_ring_bmap_mem = mem;\n+\tinl_dev->soft_exp_ring_bmap = bmap;\n+\n+\tfor (i = 0; i < ROC_NIX_INL_MAX_SOFT_EXP_RNGS; i++)\n+\t\tplt_bitmap_clear(inl_dev->soft_exp_ring_bmap, i);\n+\n+\tsoft_exp_consumer_cnt = 0;\n+\tsoft_exp_poll_thread_exit = false;\n+\tinl_dev->soft_exp_poll_freq = 100;\n+\trc = plt_ctrl_thread_create(&inl_dev->soft_exp_poll_thread,\n+\t\t\t\t \"OUTB_SOFT_EXP_POLL_THREAD\", NULL,\n+\t\t\t\t nix_inl_outb_poll_thread, inl_dev);\n+\tif (rc) {\n+\t\tplt_bitmap_free(inl_dev->soft_exp_ring_bmap);\n+\t\tplt_free(inl_dev->soft_exp_ring_bmap_mem);\n+\t}\n+\n+exit:\n+\treturn rc;\n+}\n+\n int\n roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n {\n@@ -581,6 +712,12 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n \tif (rc)\n \t\tgoto sso_release;\n \n+\tif (roc_inl_dev->set_soft_exp_poll) {\n+\t\trc = nix_inl_outb_poll_thread_setup(inl_dev);\n+\t\tif (rc)\n+\t\t\tgoto cpt_release;\n+\t}\n+\n \t/* Perform selftest if asked for */\n \tif (inl_dev->selftest) {\n \t\trc = nix_inl_selftest();\n@@ -624,6 +761,13 @@ roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev)\n \tinl_dev = idev->nix_inl_dev;\n \tpci_dev = inl_dev->pci_dev;\n \n+\tif (roc_inl_dev->set_soft_exp_poll) {\n+\t\tsoft_exp_poll_thread_exit = true;\n+\t\tpthread_join(inl_dev->soft_exp_poll_thread, NULL);\n+\t\tplt_bitmap_free(inl_dev->soft_exp_ring_bmap);\n+\t\tplt_free(inl_dev->soft_exp_ring_bmap_mem);\n+\t}\n+\n \t/* Flush Inbound CTX cache entries */\n \tnix_inl_cpt_ctx_cache_sync(inl_dev);\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c\nindex 848523b010..0cb9b46b44 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c\n@@ -29,7 +29,7 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)\n \t/* Do we have any work? */\n \tif (work) {\n \t\tif (inl_dev->work_cb)\n-\t\t\tinl_dev->work_cb(gw.u64, inl_dev->cb_args);\n+\t\t\tinl_dev->work_cb(gw.u64, inl_dev->cb_args, false);\n \t\telse\n \t\t\tplt_warn(\"Undelivered inl dev work gw0: %p gw1: %p\",\n \t\t\t\t (void *)gw.u64[0], (void *)gw.u64[1]);\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex 2cdab6dc7a..a695163e84 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -3,6 +3,8 @@\n */\n #ifndef _ROC_NIX_INL_PRIV_H_\n #define _ROC_NIX_INL_PRIV_H_\n+#include <pthread.h>\n+#include <sys/types.h>\n \n struct nix_inl_dev {\n \t/* Base device object */\n@@ -48,6 +50,17 @@ struct nix_inl_dev {\n \t/* CPT data */\n \tstruct roc_cpt_lf cpt_lf;\n \n+\t/* OUTB soft expiry poll thread */\n+\tpthread_t soft_exp_poll_thread;\n+\tuint32_t soft_exp_poll_freq;\n+\tvoid *sa_soft_exp_ring[ROC_NIX_INL_MAX_SOFT_EXP_RNGS];\n+\n+\t/* Soft expiry ring bitmap */\n+\tstruct plt_bitmap *soft_exp_ring_bmap;\n+\n+\t/* bitmap memory */\n+\tvoid *soft_exp_ring_bmap_mem;\n+\n \t/* Device arguments */\n \tuint8_t selftest;\n \tuint16_t channel;\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex deb2a6ba11..959de778f2 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -178,6 +178,8 @@ struct nix {\n \tuint16_t outb_err_sso_pffunc;\n \tstruct roc_cpt_lf *cpt_lf_base;\n \tuint16_t nb_cpt_lf;\n+\tuint16_t outb_se_ring_cnt;\n+\tuint16_t outb_se_ring_base;\n \t/* Mode provided by driver */\n \tbool inb_inl_dev;\n \ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex adfb88c68d..1adbdd5084 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -14,6 +14,7 @@\n #include <rte_ether.h>\n #include <rte_interrupts.h>\n #include <rte_io.h>\n+#include <rte_lcore.h>\n #include <rte_log.h>\n #include <rte_malloc.h>\n #include <rte_memzone.h>\n@@ -56,6 +57,7 @@\n #define BITMASK_ULL\t\t GENMASK_ULL\n #define PLT_ALIGN_CEIL\t\t RTE_ALIGN_CEIL\n #define PLT_INIT\t\t RTE_INIT\n+#define PLT_MAX_ETHPORTS\t RTE_MAX_ETHPORTS\n #define PLT_TAILQ_FOREACH_SAFE\t RTE_TAILQ_FOREACH_SAFE\n \n #ifndef PLT_ETHER_ADDR_LEN\n@@ -114,6 +116,7 @@\n #define plt_intr_disable\t rte_intr_disable\n #define plt_thread_is_intr\t rte_thread_is_intr\n #define plt_intr_callback_fn\t rte_intr_callback_fn\n+#define plt_ctrl_thread_create\t rte_ctrl_thread_create\n \n #define plt_intr_efd_counter_size_get\trte_intr_efd_counter_size_get\n #define plt_intr_efd_counter_size_set\trte_intr_efd_counter_size_set\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex ad1b5e8476..aff99ee7c8 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -83,6 +83,7 @@ INTERNAL {\n \troc_hash_sha512_gen;\n \troc_idev_cpt_get;\n \troc_idev_cpt_set;\n+\troc_nix_inl_outb_ring_base_get;\n \troc_idev_lmt_base_addr_get;\n \troc_idev_npa_maxpools_get;\n \troc_idev_npa_maxpools_set;\n@@ -154,6 +155,7 @@ INTERNAL {\n \troc_nix_inl_outb_sa_base_get;\n \troc_nix_inl_outb_sso_pffunc_get;\n \troc_nix_inl_outb_is_enabled;\n+\troc_nix_inl_outb_soft_exp_poll_switch;\n \troc_nix_inl_sa_sync;\n \troc_nix_inl_ctx_write;\n \troc_nix_inl_inb_sa_init;\ndiff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c\nindex 12cec0a17e..d6a0e7ab64 100644\n--- a/drivers/net/cnxk/cn10k_ethdev_sec.c\n+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c\n@@ -9,6 +9,7 @@\n \n #include <cn10k_ethdev.h>\n #include <cnxk_security.h>\n+#include <roc_priv.h>\n \n static struct rte_cryptodev_capabilities cn10k_eth_sec_crypto_caps[] = {\n \t{\t/* AES GCM */\n@@ -139,7 +140,7 @@ static const struct rte_security_capability cn10k_eth_sec_capabilities[] = {\n };\n \n static void\n-cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)\n+cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args, uint32_t soft_exp_event)\n {\n \tstruct rte_eth_event_ipsec_desc desc;\n \tstruct cn10k_sec_sess_priv sess_priv;\n@@ -172,8 +173,18 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)\n \t\t}\n \t\t/* Fall through */\n \tdefault:\n-\t\tplt_err(\"Unknown event gw[0] = 0x%016lx, gw[1] = 0x%016lx\",\n-\t\t\tgw[0], gw[1]);\n+\t\tif (soft_exp_event & 0x1) {\n+\t\t\tsa = (struct roc_ot_ipsec_outb_sa *)args;\n+\t\t\tpriv = roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(sa);\n+\t\t\tdesc.metadata = (uint64_t)priv->userdata;\n+\t\t\tdesc.subtype = RTE_ETH_EVENT_IPSEC_SA_TIME_EXPIRY;\n+\t\t\teth_dev = &rte_eth_devices[soft_exp_event >> 8];\n+\t\t\trte_eth_dev_callback_process(eth_dev,\n+\t\t\t\tRTE_ETH_EVENT_IPSEC, &desc);\n+\t\t} else {\n+\t\t\tplt_err(\"Unknown event gw[0] = 0x%016lx, gw[1] = 0x%016lx\",\n+\t\t\t\tgw[0], gw[1]);\n+\t\t}\n \t\treturn;\n \t}\n \n@@ -225,6 +236,30 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)\n \trte_pktmbuf_free(mbuf);\n }\n \n+static int\n+cn10k_eth_sec_outb_sa_misc_fill(struct roc_nix *roc_nix,\n+\t\t\t\tstruct roc_ot_ipsec_outb_sa *sa, void *sa_cptr,\n+\t\t\t\tstruct rte_security_ipsec_xform *ipsec_xfrm,\n+\t\t\t\tuint32_t sa_idx)\n+{\n+\tuint64_t *ring_base, ring_addr;\n+\n+\tif (ipsec_xfrm->life.bytes_soft_limit |\n+\t ipsec_xfrm->life.packets_soft_limit) {\n+\t\tring_base = roc_nix_inl_outb_ring_base_get(roc_nix);\n+\t\tif (ring_base == NULL)\n+\t\t\treturn -ENOTSUP;\n+\n+\t\tring_addr = ring_base[sa_idx >>\n+\t\t\t\t ROC_NIX_SOFT_EXP_ERR_RING_MAX_ENTRY_LOG2];\n+\t\tsa->ctx.err_ctl.s.mode = ROC_IE_OT_ERR_CTL_MODE_RING;\n+\t\tsa->ctx.err_ctl.s.address = ring_addr >> 3;\n+\t\tsa->w0.s.ctx_id = ((uintptr_t)sa_cptr >> 51) & 0x1ff;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n cn10k_eth_sec_session_create(void *device,\n \t\t\t struct rte_security_session_conf *conf,\n@@ -386,6 +421,17 @@ cn10k_eth_sec_session_create(void *device,\n \t\t\tgoto mempool_put;\n \t\t}\n \n+\t\t/* Fill outbound sa misc params */\n+\t\trc = cn10k_eth_sec_outb_sa_misc_fill(&dev->nix, outb_sa_dptr,\n+\t\t\t\t\t\t outb_sa, ipsec, sa_idx);\n+\t\tif (rc) {\n+\t\t\tsnprintf(tbuf, sizeof(tbuf),\n+\t\t\t\t \"Failed to init outb sa misc params, rc=%d\",\n+\t\t\t\t rc);\n+\t\t\trc |= cnxk_eth_outb_sa_idx_put(dev, sa_idx);\n+\t\t\tgoto mempool_put;\n+\t\t}\n+\n \t\t/* Save userdata */\n \t\toutb_priv->userdata = conf->userdata;\n \t\toutb_priv->sa_idx = sa_idx;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 27751a6956..f4045169f0 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -1405,6 +1405,8 @@ cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)\n \t/* Disable Rx via NPC */\n \troc_nix_npc_rx_ena_dis(&dev->nix, false);\n \n+\troc_nix_inl_outb_soft_exp_poll_switch(&dev->nix, false);\n+\n \t/* Stop rx queues and free up pkts pending */\n \tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n \t\trc = dev_ops->rx_queue_stop(eth_dev, i);\n@@ -1503,6 +1505,8 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)\n \n \tcnxk_nix_toggle_flag_link_cfg(dev, false);\n \n+\troc_nix_inl_outb_soft_exp_poll_switch(&dev->nix, true);\n+\n \treturn 0;\n \n rx_disable:\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c\nindex 3fef0562ea..1f87ef8265 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_sec.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c\n@@ -278,6 +278,7 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv,\n \t}\n \n \tinl_dev->attach_cptlf = true;\n+\tinl_dev->set_soft_exp_poll = true;\n \trc = roc_nix_inl_dev_init(inl_dev);\n \tif (rc) {\n \t\tplt_err(\"Failed to init nix inl device, rc=%d(%s)\", rc,\n", "prefixes": [ "1/1" ] }