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GET /api/patches/108204/?format=api
{ "id": 108204, "url": "http://patches.dpdk.org/api/patches/108204/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-4-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220224031029.14049-4-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220224031029.14049-4-suanmingm@nvidia.com", "date": "2022-02-24T03:10:18", "name": "[v3,03/14] net/mlx5: introduce hardware steering enable routine", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d33cda97a4a8da507a712e45a3579c882281cbb5", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-4-suanmingm@nvidia.com/mbox/", "series": [ { "id": 21839, "url": "http://patches.dpdk.org/api/series/21839/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21839", "date": "2022-02-24T03:10:16", "name": "net/mlx5: add hardware steering", "version": 3, "mbox": "http://patches.dpdk.org/series/21839/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/108204/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/108204/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4D5A4A0353;\n\tThu, 24 Feb 2022 04:11:05 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 14DDC4115D;\n\tThu, 24 Feb 2022 04:10:59 +0100 (CET)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2084.outbound.protection.outlook.com [40.107.93.84])\n by mails.dpdk.org (Postfix) with ESMTP id 4BBDE4115B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v3 03/14] net/mlx5: introduce hardware steering enable routine", "Date": "Thu, 24 Feb 2022 05:10:18 +0200", "Message-ID": "<20220224031029.14049-4-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220224031029.14049-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>\n <20220224031029.14049-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "567c8689-1467-4acf-7100-08d9f7434458", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1336:EE_", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB1336661ADF66EA8DCE468D71C13D9@CY4PR12MB1336.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 8A15JlSGxZpauogOPGKMRB/alE3EXsZYVy5ESNvxSv4E+wA3/fiajHpKMZSBKQATNR3seKNuryhMvhkSU/jxOBfjLxvWgJju4q1ONfRrk6NJoXmsyGNwoJt6w0ku3Mr+oca0cJTWQQ6nlPyucirvYLXyUPvnLMUdhCLd6bss+XLFZkwT2cIBbtL1DHxNW7IfUvYEMBc4J7aaFEJYWc9USTHbvj32YsBiLD3jVJqMKk0CmkTnpf2V8OTWrk9fYc+zGgphePqLxVAn35cFFd/Zuu0jfcDK2rlqOBBiFiXBX3dpzEWyXMAFE5OWI1C+8h0vUaD0TbhIIQ6Hp5+V91LDRDqofpBXlkzlew7b+C3qlfc6+K7N+RloKkFOzmE39d5mbWvjkcfJk7IDIY2Xg9u7D3w8CZcgh99Jj0pd+5+6Xti0NoFP33M40AqeHTgo1FvkudqInFCEmn1MnvpvrIKkJ08KRAhaeTpmYLa+uwO2MxF6k1QQBsNln6E9hkksGYALdrRGrEfQlBxAKONZI9WrnsV+rdYOMrXGlhnnlRFLT5kj3FIG6qYcO07gWCN/pW1GUtTJ8TWGGDWfP6gBbpORtjtaVgKacvv2r6HCHJZuS1qFEdZ7Mtg4iETgcXG7G3Yx3sbZJUJVCopiBbGYRB0I3HxEkl8vdBxJGq6izfkzllj0YsgbChhSedvi9VrB30svZUaRSIrBv7ASdreYZAbKOVjES3JuLzSY2S4IXImp7T4=", "X-Forefront-Antispam-Report": "CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(4326008)(36756003)(47076005)(426003)(83380400001)(40460700003)(336012)(5660300002)(55016003)(2906002)(8936002)(7696005)(110136005)(36860700001)(316002)(16526019)(6286002)(186003)(26005)(8676002)(508600001)(81166007)(356005)(82310400004)(70206006)(70586007)(6666004)(86362001)(1076003)(54906003)(6636002)(2616005)(36900700001)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Feb 2022 03:10:52.9902 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 567c8689-1467-4acf-7100-08d9f7434458", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT028.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1336", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The new hardware steering engine relies on using dedicated steering WQEs\ninstead of direct writing to the low-level steering table entries directly.\nIn the first introduce implementation the hardware steering engine supports\nthe new queue based Flow API, the existing synchronous non-queue based Flow\nAPI is not supported.\n\nA new dv_flow_en value 2 is added to manage mlx5 PMD steering engine:\n\ndv_flow_en\trte_flow API\trte_flow_async API\n------------------------------------------------\n 0\t\tsupport\t\tnot support\n 1\t\tsupport\t\tnot support\n 2\t\tnot support\tsupport\n\nThis commit introduces the extra dv_flow_en = 2 to specify the new\nflow initialize and manage operation routine.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 13 ++++++++++---\n drivers/net/mlx5/linux/mlx5_os.c | 4 ++++\n drivers/net/mlx5/mlx5.c | 7 ++++++-\n drivers/net/mlx5/mlx5.h | 3 ++-\n drivers/net/mlx5/mlx5_flow.c | 22 ++++++++++++++++++++++\n 5 files changed, 44 insertions(+), 5 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 8956cd1dd8..0e0169c8bb 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -942,10 +942,17 @@ for an additional list of options shared with other mlx5 drivers.\n \n - ``dv_flow_en`` parameter [int]\n \n- A nonzero value enables the DV flow steering assuming it is supported\n- by the driver (RDMA Core library version is rdma-core-24.0 or higher).\n+ Value 0 means legacy Verbs flow offloading.\n \n- Enabled by default if supported.\n+ Value 1 enables the DV flow steering assuming it is supported by the\n+ driver (RDMA Core library version is rdma-core-24.0 or higher).\n+\n+ Value 2 enables the WQE based hardware steering. In this mode only\n+ the queue-based rte_flow_q flow management is supported.\n+\n+ Configured by default to 1 DV flow steering if the driver(RDMA CORE library)\n+ supported. Otherwise, the value will be 0 which indicates legacy Verbs flow\n+ offloading.\n \n - ``dv_esw_en`` parameter [int]\n \ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex ecf823da56..0faf26f5b8 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -482,6 +482,8 @@ mlx5_alloc_shared_dr(struct mlx5_priv *priv)\n \terr = mlx5_alloc_table_hash_list(priv);\n \tif (err)\n \t\tgoto error;\n+\tif (priv->sh->config.dv_flow_en == 2)\n+\t\treturn 0;\n \t/* The resources below are only valid with DV support. */\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t/* Init port id action list. */\n@@ -1519,6 +1521,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tpriv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev);\n \tif (!priv->drop_queue.hrxq)\n \t\tgoto error;\n+\tif (priv->sh->config.dv_flow_en == 2)\n+\t\treturn eth_dev;\n \t/* Port representor shares the same max priority with pf port. */\n \tif (!priv->sh->flow_priority_check_flag) {\n \t\t/* Supported Verbs flow priority number detection. */\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 9f65a8f901..f49d30c05c 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1199,7 +1199,12 @@ mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque)\n \t} else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {\n \t\tconfig->dv_esw_en = !!tmp;\n \t} else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {\n-\t\tconfig->dv_flow_en = !!tmp;\n+\t\tif (tmp > 2) {\n+\t\t\tDRV_LOG(ERR, \"Invalid %s parameter.\", key);\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\tconfig->dv_flow_en = tmp;\n \t} else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {\n \t\tif (tmp != MLX5_XMETA_MODE_LEGACY &&\n \t\t tmp != MLX5_XMETA_MODE_META16 &&\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 0f465d0e9e..b2259fc1fb 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -287,7 +287,8 @@ struct mlx5_sh_config {\n \tint tx_skew; /* Tx scheduling skew between WQE and data on wire. */\n \tuint32_t reclaim_mode:2; /* Memory reclaim mode. */\n \tuint32_t dv_esw_en:1; /* Enable E-Switch DV flow. */\n-\tuint32_t dv_flow_en:1; /* Enable DV flow. */\n+\t/* Enable DV flow. 1 means SW steering, 2 means HW steering. */\n+\tunsigned int dv_flow_en:2;\n \tuint32_t dv_xmeta_en:2; /* Enable extensive flow metadata. */\n \tuint32_t dv_miss_info:1; /* Restore packet after partial hw miss. */\n \tuint32_t l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex b289f13fc0..cdb40c0756 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -6840,6 +6840,15 @@ mlx5_flow_create(struct rte_eth_dev *dev,\n \t\t const struct rte_flow_action actions[],\n \t\t struct rte_flow_error *error)\n {\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\n+\tif (priv->sh->config.dv_flow_en == 2) {\n+\t\trte_flow_error_set(error, ENOTSUP,\n+\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t NULL,\n+\t\t\t \"Flow non-Q creation not supported\");\n+\t\treturn NULL;\n+\t}\n \t/*\n \t * If the device is not started yet, it is not allowed to created a\n \t * flow from application. PMD default flows and traffic control flows\n@@ -7336,6 +7345,13 @@ mlx5_flow_destroy(struct rte_eth_dev *dev,\n \t\t struct rte_flow *flow,\n \t\t struct rte_flow_error *error __rte_unused)\n {\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\n+\tif (priv->sh->config.dv_flow_en == 2)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t NULL,\n+\t\t\t \"Flow non-Q destruction not supported\");\n \tflow_list_destroy(dev, MLX5_FLOW_TYPE_GEN,\n \t\t\t\t(uintptr_t)(void *)flow);\n \treturn 0;\n@@ -7433,7 +7449,13 @@ mlx5_flow_query(struct rte_eth_dev *dev,\n \t\tstruct rte_flow_error *error)\n {\n \tint ret;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n \n+\tif (priv->sh->config.dv_flow_en == 2)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t NULL,\n+\t\t\t \"Flow non-Q query not supported\");\n \tret = flow_drv_query(dev, (uintptr_t)(void *)flow, actions, data,\n \t\t\t error);\n \tif (ret < 0)\n", "prefixes": [ "v3", "03/14" ] }