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GET /api/patches/108202/?format=api
{ "id": 108202, "url": "http://patches.dpdk.org/api/patches/108202/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-2-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220224031029.14049-2-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220224031029.14049-2-suanmingm@nvidia.com", "date": "2022-02-24T03:10:16", "name": "[v3,01/14] net/mlx5: introduce hardware steering operation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ce5abefe316c18d8b5f372c488afa0619807e942", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-2-suanmingm@nvidia.com/mbox/", "series": [ { "id": 21839, "url": "http://patches.dpdk.org/api/series/21839/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21839", "date": "2022-02-24T03:10:16", "name": "net/mlx5: add hardware steering", "version": 3, "mbox": "http://patches.dpdk.org/series/21839/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/108202/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/108202/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 281F9A0353;\n\tThu, 24 Feb 2022 04:10:53 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F3FBE40DF6;\n\tThu, 24 Feb 2022 04:10:52 +0100 (CET)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2058.outbound.protection.outlook.com [40.107.92.58])\n by mails.dpdk.org (Postfix) with ESMTP id 2C44240696\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v3 01/14] net/mlx5: introduce hardware steering operation", "Date": "Thu, 24 Feb 2022 05:10:16 +0200", "Message-ID": "<20220224031029.14049-2-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220224031029.14049-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>\n <20220224031029.14049-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "af03077b-d766-4ab9-0347-08d9f7434195", "X-MS-TrafficTypeDiagnostic": "BY5PR12MB4145:EE_", "X-Microsoft-Antispam-PRVS": "\n <BY5PR12MB414537F906224BBE0D5514E7C13D9@BY5PR12MB4145.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Y7RxgUF5WKUPicZ6zRy4PmNATQMB6mDpen6GXIAnOc7JoBPmKYKBx8oVu5a8apzytXubPTF450YcBYkNhUJJXXFUGuBXu4E5ggquQyH1NDu8n9pJT38Kakv8C8N5/bKQ4F8BtDUju9j8NwHBcTTsAZxrzE8LQN3Si/S9aElpZM4ouKp3ELOV2iT7wmWiD+6y8MughnbKdrIN6UsZR5+wMZSvh13VfYLewJlWK+mExnVzxTQuCqxLZpsSIKaVDTHN3GNSvgVkZjdJZXQGjPsxf/WDCk/mdAN69kw4iAlEg+IuqLxGn6FnIhGI7A/btWj3FXwsaE/oVHNXMf0h1QyoiFzw/pfihPMI+5e7b6s9ltLLpGEeXAuXWQ3QDiSPU5FD0Q/kF1Q+8uA3plToMI/Y8zqplD1QgnaN3t4zZeHZ0bbGlZb75nmr3WsvmJHCOeUwXjwj85o5nrAanoe6kdTzBz2UntK41QjcWrnCOMgIS0H7k0dPCbtQpjKpm6OHhNqzq9crYrjE2Ud7l7LSHP1buUqb/G+Cl3CNoa29LYVlEBVy7nyl6M+fGult5dpXgCYwJOO2NX2UGhpoXzphKSSTmhBM1e3s8glzCGZcHZKVEw/JJvCn38F+p+fyF8HERPn1/6un+m5rj3u3rQf4yEy2sLDLhgt8L9yA4cJLDMHRt+hYxfMwyGWZuqvCbAQn5j05JfQRFxl78PJE6EA6ofErjA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(82310400004)(70586007)(8936002)(70206006)(8676002)(5660300002)(55016003)(4326008)(2906002)(40460700003)(36756003)(47076005)(36860700001)(6286002)(2616005)(26005)(508600001)(336012)(356005)(1076003)(7696005)(186003)(316002)(110136005)(6636002)(54906003)(83380400001)(81166007)(6666004)(16526019)(86362001)(426003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Feb 2022 03:10:48.3383 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n af03077b-d766-4ab9-0347-08d9f7434195", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT004.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4145", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The Connect-X steering is a lookup hardware mechanism that accesses\nflow tables, matches packets to the rules, and performs specified actions.\nHistorically, mlx5 PMD implements several software engines to manage\nsteering hardware facility:\n\n - FW Steering - Verbs/Direct Verbs, uses FW calls to manage flows\n - SW Steering - DevX/mlx5dv, uses WQEs to access table memory directly\n\nHowever, there are still some disadvantages:\n\n - performance is limited, we should invoke firmware either to\n manage the entire flow, or to handle some internal steering objects\n\n - organizing and preparing flow infrastructure (actions, matchers,\n groups, etc.) on the flow inserting is sure to cause slow flow\n insertion\n\n - security, exposing the low-level steering entries directly to the\n userspace may cause security risks\n\nA new hardware WQE based steering operation with codename \"HW Steering\"\nis going to be introduced to get rid of the security risks. And it will\ntake advantage of the recently new introduced async queue-based rte_flow\nAPIs to prepare everything in advance to achieve high insertion rate.\n\nIn this new HW steering engine, the original SW steering rte_flow API\nwill not be supported in the first implementation, only the new async\nqueue-based flow operations is going to be supported. A new steering\nmode parameter for dv_flow_en will be introduced and user will be\nable to engage the new steering engine.\n\nThis commit adds the basic driver operation.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_flow_os.h | 1 +\n drivers/net/mlx5/meson.build | 1 +\n drivers/net/mlx5/mlx5_flow.c | 1 +\n drivers/net/mlx5/mlx5_flow.h | 1 +\n drivers/net/mlx5/mlx5_flow_hw.c | 13 +++++++++++++\n drivers/net/mlx5/windows/mlx5_flow_os.h | 1 +\n 6 files changed, 18 insertions(+)\n create mode 100644 drivers/net/mlx5/mlx5_flow_hw.c", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_flow_os.h b/drivers/net/mlx5/linux/mlx5_flow_os.h\nindex 1926d26410..e28a9e0436 100644\n--- a/drivers/net/mlx5/linux/mlx5_flow_os.h\n+++ b/drivers/net/mlx5/linux/mlx5_flow_os.h\n@@ -9,6 +9,7 @@\n \n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops;\n+extern const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;\n #endif\n \n /**\ndiff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build\nindex 2f6d8cbb3d..39a2b8c523 100644\n--- a/drivers/net/mlx5/meson.build\n+++ b/drivers/net/mlx5/meson.build\n@@ -16,6 +16,7 @@ sources = files(\n 'mlx5_flow.c',\n 'mlx5_flow_meter.c',\n 'mlx5_flow_dv.c',\n+ 'mlx5_flow_hw.c',\n 'mlx5_flow_aso.c',\n 'mlx5_flow_flex.c',\n 'mlx5_mac.c',\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex a87ac8e6d7..b289f13fc0 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -76,6 +76,7 @@ const struct mlx5_flow_driver_ops *flow_drv_ops[] = {\n \t[MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops,\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \t[MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops,\n+\t[MLX5_FLOW_TYPE_HW] = &mlx5_flow_hw_drv_ops,\n #endif\n \t[MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops,\n \t[MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex a20773eeb2..b70ef0c1b8 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -452,6 +452,7 @@ enum mlx5_flow_drv_type {\n \tMLX5_FLOW_TYPE_MIN,\n \tMLX5_FLOW_TYPE_DV,\n \tMLX5_FLOW_TYPE_VERBS,\n+\tMLX5_FLOW_TYPE_HW,\n \tMLX5_FLOW_TYPE_MAX,\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nnew file mode 100644\nindex 0000000000..729d5914a8\n--- /dev/null\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include <rte_flow.h>\n+\n+#include \"mlx5_flow.h\"\n+\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n+\n+const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;\n+\n+#endif\ndiff --git a/drivers/net/mlx5/windows/mlx5_flow_os.h b/drivers/net/mlx5/windows/mlx5_flow_os.h\nindex dfcb012334..52013b06a0 100644\n--- a/drivers/net/mlx5/windows/mlx5_flow_os.h\n+++ b/drivers/net/mlx5/windows/mlx5_flow_os.h\n@@ -10,6 +10,7 @@\n \n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops;\n+extern const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;\n #endif\n \n /**\n", "prefixes": [ "v3", "01/14" ] }