Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/107992/?format=api
{ "id": 107992, "url": "http://patches.dpdk.org/api/patches/107992/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220222160634.24489-17-mk@semihalf.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220222160634.24489-17-mk@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220222160634.24489-17-mk@semihalf.com", "date": "2022-02-22T16:06:29", "name": "[16/21] net/ena: make Tx completion timeout configurable", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d833998ce4c30846e3f01869ace81921e3582116", "submitter": { "id": 786, "url": "http://patches.dpdk.org/api/people/786/?format=api", "name": "Michal Krawczyk", "email": "mk@semihalf.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220222160634.24489-17-mk@semihalf.com/mbox/", "series": [ { "id": 21796, "url": "http://patches.dpdk.org/api/series/21796/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21796", "date": "2022-02-22T16:06:13", "name": "net/ena: v2.6.0 driver update", "version": 1, "mbox": "http://patches.dpdk.org/series/21796/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/107992/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/107992/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 71378A0352;\n\tTue, 22 Feb 2022 17:08:46 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0DCEE41C2E;\n\tTue, 22 Feb 2022 17:07:16 +0100 (CET)", "from mail-ej1-f52.google.com (mail-ej1-f52.google.com\n [209.85.218.52]) by mails.dpdk.org (Postfix) with ESMTP id 3306F411DF\n for <dev@dpdk.org>; Tue, 22 Feb 2022 17:07:13 +0100 (CET)", "by mail-ej1-f52.google.com with SMTP id r13so21335714ejd.5\n for <dev@dpdk.org>; Tue, 22 Feb 2022 08:07:13 -0800 (PST)", "from DESKTOP-U5LNN3J.localdomain (89-79-181-52.dynamic.chello.pl.\n [89.79.181.52])\n by smtp.gmail.com with ESMTPSA id x6sm10013477edv.109.2022.02.22.08.07.11\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 22 Feb 2022 08:07:11 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20210112.gappssmtp.com; s=20210112;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=oCWqJTcYdWnvA0jll4GvmUtKZbrObkrt69QJcxg4sj8=;\n b=71RUBrUd6J90dgpL9mEfkJsqD5eAUF+7l1WjGN0HmXMBgSd064O46bQKAMVwtjTCf+\n AxFQ3qo1Y7p44ZosBBFkyU+VBa2iFfQgQxZOxB6CCKCUURZUPlvuz7Ypz9EfWtE47nyi\n mRqELMr4QyGh7z7oSxSFbxi21PeC7LpCGy05C6qVv6TU/dTdU9DjiSm6wMMGTS+goU69\n nQlo7Vm0shLyur1LC6sH5hV/He5nVyOb1oGVNArhpd6dJmjB+ZfJGH2RXJBlHQ/OhonO\n x4Ja+t5feynNZxMkcRzA/qnRaIb0MEiESPAhEPZlulb5LhkVW7eRloQfZfNaY0rFZPF5\n tEtg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20210112;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=oCWqJTcYdWnvA0jll4GvmUtKZbrObkrt69QJcxg4sj8=;\n b=dxnHUWFLikdF0RK8bHOS0K5/cIAkAiRWa7BSIM7iZLvx2ZX9ThQ8dKIFNGv7fCcr72\n 3CAckE8Tl5N7vwxlGpgNYbD/DJftHF08dlMtHkzqf+4HNN2S1vv1tlLckWqr9ZiWLQ9q\n VGAXheIpigFZdw24E5/u8OIEniqRxiBqhXF51+IrWkkDBo687D6UJIWrSmCGXbvaWYUN\n bmXgMV+GJHTxBT8RWfUMxgTUtPu7B16boD3a3fUUI60RC6zCld6FcQoD0lm6u/2BzWky\n C9p4KCX7Ow1e4dVLLAcJFiiAznlyXI52lYPUCnJN4Wk4M3wBD19wDdvPkKgp737QZ8hA\n jHnQ==", "X-Gm-Message-State": "AOAM530CkpGdhy+wBvL2mJEcvZFQSz1aLL806Ye8rX4piuK5tebnccFH\n Y3l6NXUmBY6RgRa6Rsf+ILurzsMzO3vOcg==", "X-Google-Smtp-Source": "\n ABdhPJxJztcRitKwv7T0W0xAcc6D6CWo70Vcp8gyh8htGib4lliG7pycSA8CXJWuYS5oV9VsvNN3cw==", "X-Received": "by 2002:a17:906:6d12:b0:6cd:6970:2d4c with SMTP id\n m18-20020a1709066d1200b006cd69702d4cmr19888009ejr.323.1645546032419;\n Tue, 22 Feb 2022 08:07:12 -0800 (PST)", "From": "Michal Krawczyk <mk@semihalf.com>", "To": "dev@dpdk.org", "Cc": "shaibran@amazon.com, upstream@semihalf.com,\n Michal Krawczyk <mk@semihalf.com>, Dawid Gorecki <dgr@semihalf.com>", "Subject": "[PATCH 16/21] net/ena: make Tx completion timeout configurable", "Date": "Tue, 22 Feb 2022 17:06:29 +0100", "Message-Id": "<20220222160634.24489-17-mk@semihalf.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220222160634.24489-1-mk@semihalf.com>", "References": "<20220222160634.24489-1-mk@semihalf.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The default missing Tx completion timeout was set to 5 seconds.\nIn order to provide users with the interface to control this timeout\nto adjust it with the application's watchdog, the device argument for\ncontrolling this value was added.\n\nThe parameter is called 'miss_txc_to' and can be modified using the\ndevargs interface:\n\n ./app -a <bdf>,miss_txc_to=UINT_NUMBER\n\nThis parameter accepts values from 0 to 60 and indicates number of\nseconds after which the Tx packet will be considered as missing.\n\nHW hints for the Tx completions timeout were removed to do not overwrite\nparameter from the user. Also specyfing default Tx completion timeout\nvalue was moved from the configuration to init phase in order to\nsimplify default value assignment.\n\nSigned-off-by: Michal Krawczyk <mk@semihalf.com>\nReviewed-by: Dawid Gorecki <dgr@semihalf.com>\nReviewed-by: Shai Brandes <shaibran@amazon.com>\n---\n doc/guides/nics/ena.rst | 9 ++++\n doc/guides/rel_notes/release_22_03.rst | 1 +\n drivers/net/ena/ena_ethdev.c | 66 ++++++++++++++++++++------\n drivers/net/ena/ena_ethdev.h | 1 +\n 4 files changed, 62 insertions(+), 15 deletions(-)", "diff": "diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst\nindex 85c790e80f..3d780acac9 100644\n--- a/doc/guides/nics/ena.rst\n+++ b/doc/guides/nics/ena.rst\n@@ -87,6 +87,15 @@ Configuration information\n effect only if the device also supports large LLQ headers. Otherwise, the\n default value will be used.\n \n+ * **miss_txc_to** (default 5)\n+\n+ Number of seconds after which the Tx packet will be considered missing.\n+ If the missing packets number will exceed dynamically calculated threshold,\n+ the driver will trigger the device reset which should be handled by the\n+ application. Checking for missing Tx completions happens in the driver's\n+ timer service. Setting this parameter to 0 disables this feature. Maximum\n+ allowed value is 60 seconds.\n+\n **ENA Configuration Parameters**\n \n * **Number of Queues**\ndiff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst\nindex 1b87b9c174..d0d2824371 100644\n--- a/doc/guides/rel_notes/release_22_03.rst\n+++ b/doc/guides/rel_notes/release_22_03.rst\n@@ -116,6 +116,7 @@ New Features\n * Added ENA admin queue support for the MP applications.\n * Added free Tx mbuf on demand feature support.\n * Added ``rte_eth_xstats_get_names_by_id`` API support.\n+ * Added ``miss_txc_to`` device argument for setting the Tx completion timeout.\n \n * **Updated Cisco enic driver.**\n \ndiff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex d413111b08..4bb2b195b1 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -62,6 +62,10 @@ struct ena_stats {\n \n /* Device arguments */\n #define ENA_DEVARG_LARGE_LLQ_HDR \"large_llq_hdr\"\n+/* Timeout in seconds after which a single uncompleted Tx packet should be\n+ * considered as a missing.\n+ */\n+#define ENA_DEVARG_MISS_TXC_TO \"miss_txc_to\"\n \n /*\n * Each rte_memzone should have unique name.\n@@ -2132,6 +2136,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)\n \tsnprintf(adapter->name, ENA_NAME_MAX_LEN, \"ena_%d\",\n \t\t adapter->id_number);\n \n+\tadapter->missing_tx_completion_to = ENA_TX_TIMEOUT;\n+\n \trc = ena_parse_devargs(adapter, pci_dev->device.devargs);\n \tif (rc != 0) {\n \t\tPMD_INIT_LOG(CRIT, \"Failed to parse devargs\\n\");\n@@ -2307,7 +2313,6 @@ static int ena_dev_configure(struct rte_eth_dev *dev)\n \tadapter->missing_tx_completion_budget =\n \t\tRTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);\n \n-\tadapter->missing_tx_completion_to = ENA_TX_TIMEOUT;\n \t/* To avoid detection of the spurious Tx completion timeout due to\n \t * application not calling the Tx cleanup function, set timeout for the\n \t * Tx queue which should be half of the missing completion timeout for a\n@@ -2830,20 +2835,6 @@ static void ena_update_hints(struct ena_adapter *adapter,\n \t\tadapter->ena_dev.mmio_read.reg_read_to =\n \t\t\thints->mmio_read_timeout * 1000;\n \n-\tif (hints->missing_tx_completion_timeout) {\n-\t\tif (hints->missing_tx_completion_timeout ==\n-\t\t ENA_HW_HINTS_NO_TIMEOUT) {\n-\t\t\tadapter->missing_tx_completion_to =\n-\t\t\t\tENA_HW_HINTS_NO_TIMEOUT;\n-\t\t} else {\n-\t\t\t/* Convert from msecs to ticks */\n-\t\t\tadapter->missing_tx_completion_to = rte_get_timer_hz() *\n-\t\t\t\thints->missing_tx_completion_timeout / 1000;\n-\t\t\tadapter->tx_cleanup_stall_delay =\n-\t\t\t\tadapter->missing_tx_completion_to / 2;\n-\t\t}\n-\t}\n-\n \tif (hints->driver_watchdog_timeout) {\n \t\tif (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)\n \t\t\tadapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;\n@@ -3396,6 +3387,45 @@ static int ena_xstats_get_by_id(struct rte_eth_dev *dev,\n \treturn valid;\n }\n \n+static int ena_process_uint_devarg(const char *key,\n+\t\t\t\t const char *value,\n+\t\t\t\t void *opaque)\n+{\n+\tstruct ena_adapter *adapter = opaque;\n+\tchar *str_end;\n+\tuint64_t uint_value;\n+\n+\tuint_value = strtoull(value, &str_end, 10);\n+\tif (value == str_end) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\"Invalid value for key '%s'. Only uint values are accepted.\\n\",\n+\t\t\tkey);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (strcmp(key, ENA_DEVARG_MISS_TXC_TO) == 0) {\n+\t\tif (uint_value > ENA_MAX_TX_TIMEOUT_SECONDS) {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\"Tx timeout too high: %\" PRIu64 \" sec. Maximum allowed: %d sec.\\n\",\n+\t\t\t\tuint_value, ENA_MAX_TX_TIMEOUT_SECONDS);\n+\t\t\treturn -EINVAL;\n+\t\t} else if (uint_value == 0) {\n+\t\t\tPMD_INIT_LOG(INFO,\n+\t\t\t\t\"Check for missing Tx completions has been disabled.\\n\");\n+\t\t\tadapter->missing_tx_completion_to =\n+\t\t\t\tENA_HW_HINTS_NO_TIMEOUT;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(INFO,\n+\t\t\t\t\"Tx packet completion timeout set to %\" PRIu64 \" seconds.\\n\",\n+\t\t\t\tuint_value);\n+\t\t\tadapter->missing_tx_completion_to =\n+\t\t\t\tuint_value * rte_get_timer_hz();\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int ena_process_bool_devarg(const char *key,\n \t\t\t\t const char *value,\n \t\t\t\t void *opaque)\n@@ -3427,6 +3457,7 @@ static int ena_parse_devargs(struct ena_adapter *adapter,\n {\n \tstatic const char * const allowed_args[] = {\n \t\tENA_DEVARG_LARGE_LLQ_HDR,\n+\t\tENA_DEVARG_MISS_TXC_TO,\n \t\tNULL,\n \t};\n \tstruct rte_kvargs *kvlist;\n@@ -3444,7 +3475,12 @@ static int ena_parse_devargs(struct ena_adapter *adapter,\n \n \trc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,\n \t\tena_process_bool_devarg, adapter);\n+\tif (rc != 0)\n+\t\tgoto exit;\n+\trc = rte_kvargs_process(kvlist, ENA_DEVARG_MISS_TXC_TO,\n+\t\tena_process_uint_devarg, adapter);\n \n+exit:\n \trte_kvargs_free(kvlist);\n \n \treturn rc;\ndiff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h\nindex ca3e5ed691..c0094b03ee 100644\n--- a/drivers/net/ena/ena_ethdev.h\n+++ b/drivers/net/ena/ena_ethdev.h\n@@ -40,6 +40,7 @@\n #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())\n \n #define ENA_TX_TIMEOUT\t\t\t(5 * rte_get_timer_hz())\n+#define ENA_MAX_TX_TIMEOUT_SECONDS\t60\n #define ENA_MONITORED_TX_QUEUES\t\t3\n #define ENA_DEFAULT_MISSING_COMP\t256U\n \n", "prefixes": [ "16/21" ] }