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GET /api/patches/107822/?format=api
{ "id": 107822, "url": "http://patches.dpdk.org/api/patches/107822/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220218171527.56719-6-kai.ji@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220218171527.56719-6-kai.ji@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220218171527.56719-6-kai.ji@intel.com", "date": "2022-02-18T17:15:23", "name": "[v9,5/9] crypto/qat: unify symmetric functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ca2311bc806967caf32b9349ab36f8d644701565", "submitter": { "id": 2202, "url": "http://patches.dpdk.org/api/people/2202/?format=api", "name": "Ji, Kai", "email": "kai.ji@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220218171527.56719-6-kai.ji@intel.com/mbox/", "series": [ { "id": 21741, "url": "http://patches.dpdk.org/api/series/21741/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21741", "date": "2022-02-18T17:15:18", "name": "drivers/qat: QAT symmetric crypto datapatch rework", "version": 9, "mbox": "http://patches.dpdk.org/series/21741/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/107822/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/107822/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 95CF3A0032;\n\tFri, 18 Feb 2022 18:16:18 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E7E6B41160;\n\tFri, 18 Feb 2022 18:15:53 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id C317241140\n for <dev@dpdk.org>; Fri, 18 Feb 2022 18:15:48 +0100 (CET)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Feb 2022 09:15:39 -0800", "from silpixa00400465.ir.intel.com ([10.55.128.22])\n by orsmga005.jf.intel.com with ESMTP; 18 Feb 2022 09:15:37 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1645204549; x=1676740549;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=7Def21DjzBE9oFwtfOYNmytyRfdzjaSt7SP+f6WLe98=;\n b=CY5cYnXa/WZ3MYG6liGMaDTNKA/lfEpNY9I1L7JsHL/M7dR6RBaD7FGn\n oiZAMz5zFRgW07fcfQ0wg8TDqbSzbJAsrgCcutbx5qCgL0ZyO5w9lFL5m\n 12VjmRMspBBMTqOtU72jipeZ1cQl1x4m8bCYVgZbzB301hVRga/srZYDQ\n 8sibWMDBotJ8/0CvE5jy5ryysjfwA2z/pdfVfBPBIbW4MYXng8Yu6Hhed\n IFZ/BQcUSr3UPtcaP2CLmTAEWzhLQC46kt+voHMb9DamN9GlPtUU5JVRj\n N1ZWA/jbzqKdTKvNlnuu6k7Qh5Yp6x7P7W1YJWZHsiasu4/NZO6RTXOo6 Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10262\"; a=\"238571902\"", "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"238571902\"", "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"705446248\"" ], "X-ExtLoop1": "1", "From": "Kai Ji <kai.ji@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com,\n\troy.fan.zhang@intel.com,\n\tKai Ji <kai.ji@intel.com>", "Subject": "[dpdk-dev v9 5/9] crypto/qat: unify symmetric functions", "Date": "Sat, 19 Feb 2022 01:15:23 +0800", "Message-Id": "<20220218171527.56719-6-kai.ji@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20220218171527.56719-1-kai.ji@intel.com>", "References": "<20220217162909.22713-1-kai.ji@intel.com>\n <20220218171527.56719-1-kai.ji@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch removes qat_sym_pmd.c and integrates all the functions into\nqat_sym.c. The unified/integrated qat sym crypto pmd functions should\nmake them easier to maintain.\n\nSigned-off-by: Kai Ji <kai.ji@intel.com>\n---\n drivers/common/qat/meson.build | 4 +-\n drivers/common/qat/qat_device.c | 4 +-\n drivers/common/qat/qat_qp.c | 3 +-\n drivers/crypto/qat/qat_crypto.h | 5 +-\n drivers/crypto/qat/qat_sym.c | 21 +++\n drivers/crypto/qat/qat_sym.h | 147 ++++++++++++++--\n drivers/crypto/qat/qat_sym_hw_dp.c | 11 +-\n drivers/crypto/qat/qat_sym_pmd.c | 251 ---------------------------\n drivers/crypto/qat/qat_sym_pmd.h | 95 ----------\n drivers/crypto/qat/qat_sym_session.c | 2 +-\n 10 files changed, 168 insertions(+), 375 deletions(-)\n delete mode 100644 drivers/crypto/qat/qat_sym_pmd.c\n delete mode 100644 drivers/crypto/qat/qat_sym_pmd.h", "diff": "diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex af92271a75..1bf6896a7e 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -1,5 +1,5 @@\n # SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(c) 2017-2018 Intel Corporation\n+# Copyright(c) 2017-2022 Intel Corporation\n \n if is_windows\n build = false\n@@ -73,7 +73,7 @@ if qat_compress\n endif\n \n if qat_crypto\n- foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',\n+ foreach f: ['qat_sym.c', 'qat_sym_session.c',\n 'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c',\n 'dev/qat_sym_pmd_gen1.c',\n 'dev/qat_asym_pmd_gen1.c',\ndiff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c\nindex 1f870d689a..6824d97050 100644\n--- a/drivers/common/qat/qat_device.c\n+++ b/drivers/common/qat/qat_device.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2018-2020 Intel Corporation\n+ * Copyright(c) 2018-2022 Intel Corporation\n */\n \n #include <rte_string_fns.h>\n@@ -8,7 +8,7 @@\n \n #include \"qat_device.h\"\n #include \"adf_transport_access_macros.h\"\n-#include \"qat_sym_pmd.h\"\n+#include \"qat_sym.h\"\n #include \"qat_comp_pmd.h\"\n #include \"adf_pf2vf_msg.h\"\n #include \"qat_pf2vf.h\"\ndiff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex 7f2fdc53ce..b36ffa6f6d 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -838,7 +838,8 @@ qat_dequeue_op_burst(void *qp, void **ops,\n \n \t\tif (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)\n \t\t\tqat_sym_process_response(ops, resp_msg,\n-\t\t\t\ttmp_qp->op_cookies[head >> rx_queue->trailz]);\n+\t\t\t\ttmp_qp->op_cookies[head >> rx_queue->trailz],\n+\t\t\t\tNULL);\n \t\telse if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)\n \t\t\tnb_fw_responses = qat_comp_process_response(\n \t\t\t\tops, resp_msg,\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nindex 5ca76fcaa6..c01266f81c 100644\n--- a/drivers/crypto/qat/qat_crypto.h\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -12,7 +12,10 @@\n extern uint8_t qat_sym_driver_id;\n extern uint8_t qat_asym_driver_id;\n \n-/** helper macro to set cryptodev capability range **/\n+/**\n+ * helper macro to set cryptodev capability range\n+ * <n: name> <l: min > <r: max> <i: increment> <v: value>\n+ **/\n #define CAP_RNG(n, l, r, i) .n = {.min = l, .max = r, .increment = i}\n \n #define CAP_RNG_ZERO(n) .n = {.min = 0, .max = 0, .increment = 0}\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex 83bf55c933..aad4b243b7 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -17,6 +17,27 @@ uint8_t qat_sym_driver_id;\n \n struct qat_crypto_gen_dev_ops qat_sym_gen_dev_ops[QAT_N_GENS];\n \n+void\n+qat_sym_init_op_cookie(void *op_cookie)\n+{\n+\tstruct qat_sym_op_cookie *cookie = op_cookie;\n+\n+\tcookie->qat_sgl_src_phys_addr =\n+\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_sym_op_cookie,\n+\t\t\tqat_sgl_src);\n+\n+\tcookie->qat_sgl_dst_phys_addr =\n+\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_sym_op_cookie,\n+\t\t\tqat_sgl_dst);\n+\n+\tcookie->opt.spc_gmac.cd_phys_addr =\n+\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_sym_op_cookie,\n+\t\t\topt.spc_gmac.cd_cipher);\n+}\n+\n static inline void\n set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,\n \t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param,\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex e3ec7f0de4..f4ff2ce4cd 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2018 Intel Corporation\n+ * Copyright(c) 2015-2022 Intel Corporation\n */\n \n #ifndef _QAT_SYM_H_\n@@ -15,7 +15,7 @@\n \n #include \"qat_common.h\"\n #include \"qat_sym_session.h\"\n-#include \"qat_sym_pmd.h\"\n+#include \"qat_crypto.h\"\n #include \"qat_logs.h\"\n \n #define BYTE_LENGTH 8\n@@ -24,6 +24,67 @@\n */\n #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ\n \n+/** Intel(R) QAT Symmetric Crypto PMD name */\n+#define CRYPTODEV_NAME_QAT_SYM_PMD\tcrypto_qat\n+\n+/* Internal capabilities */\n+#define QAT_SYM_CAP_MIXED_CRYPTO\t(1 << 0)\n+#define QAT_SYM_CAP_VALID\t\t(1 << 31)\n+\n+/**\n+ * Macro to add a sym capability\n+ * helper function to add an sym capability\n+ * <n: name> <b: block size> <k: key size> <d: digest size>\n+ * <a: aad_size> <i: iv_size>\n+ **/\n+#define QAT_SYM_PLAIN_AUTH_CAP(n, b, d)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n+\t\t\t{.auth = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_##n,\t\t\\\n+\t\t\t\tb, d\t\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t}\n+\n+#define QAT_SYM_AUTH_CAP(n, b, k, d, a, i)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n+\t\t\t{.auth = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_##n,\t\t\\\n+\t\t\t\tb, k, d, a, i\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t}\n+\n+#define QAT_SYM_AEAD_CAP(n, b, k, d, a, i)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\t\\\n+\t\t\t{.aead = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AEAD_##n,\t\t\\\n+\t\t\t\tb, k, d, a, i\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t}\n+\n+#define QAT_SYM_CIPHER_CAP(n, b, k, i)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\t\\\n+\t\t\t{.cipher = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_##n,\t\t\\\n+\t\t\t\tb, k, i\t\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t}\n+\n /*\n * Maximum number of SGL entries\n */\n@@ -54,6 +115,22 @@ struct qat_sym_op_cookie {\n \t} opt;\n };\n \n+struct qat_sym_dp_ctx {\n+\tstruct qat_sym_session *session;\n+\tuint32_t tail;\n+\tuint32_t head;\n+\tuint16_t cached_enqueue;\n+\tuint16_t cached_dequeue;\n+};\n+\n+uint16_t\n+qat_sym_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n+\t\tuint16_t nb_ops);\n+\n+uint16_t\n+qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops,\n+\t\tuint16_t nb_ops);\n+\n int\n qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen);\n@@ -213,17 +290,11 @@ qat_sym_preprocess_requests(void **ops, uint16_t nb_ops)\n \t\t}\n \t}\n }\n-#else\n-\n-static inline void\n-qat_sym_preprocess_requests(void **ops __rte_unused,\n-\t\t\t\tuint16_t nb_ops __rte_unused)\n-{\n-}\n #endif\n \n-static inline void\n-qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie)\n+static __rte_always_inline int\n+qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie,\n+\t\tuint64_t *dequeue_err_count __rte_unused)\n {\n \tstruct icp_qat_fw_comn_resp *resp_msg =\n \t\t\t(struct icp_qat_fw_comn_resp *)resp;\n@@ -282,6 +353,12 @@ qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie)\n \t}\n \n \t*op = (void *)rx_op;\n+\n+\t/*\n+\t * return 1 as dequeue op only move on to the next op\n+\t * if one was ready to return to API\n+\t */\n+\treturn 1;\n }\n \n int\n@@ -293,6 +370,52 @@ qat_sym_configure_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id,\n int\n qat_sym_get_dp_ctx_size(struct rte_cryptodev *dev);\n \n+void\n+qat_sym_init_op_cookie(void *cookie);\n+\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+static __rte_always_inline void\n+qat_sym_debug_log_dump(struct icp_qat_fw_la_bulk_req *qat_req,\n+\t\tstruct qat_sym_session *ctx,\n+\t\tstruct rte_crypto_vec *vec, uint32_t vec_len,\n+\t\tstruct rte_crypto_va_iova_ptr *cipher_iv,\n+\t\tstruct rte_crypto_va_iova_ptr *auth_iv,\n+\t\tstruct rte_crypto_va_iova_ptr *aad,\n+\t\tstruct rte_crypto_va_iova_ptr *digest)\n+{\n+\tuint32_t i;\n+\n+\tQAT_DP_HEXDUMP_LOG(DEBUG, \"qat_req:\", qat_req,\n+\t\t\tsizeof(struct icp_qat_fw_la_bulk_req));\n+\tfor (i = 0; i < vec_len; i++)\n+\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"src_data:\", vec[i].base, vec[i].len);\n+\tif (cipher_iv && ctx->cipher_iv.length > 0)\n+\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"cipher iv:\", cipher_iv->va,\n+\t\t\t\tctx->cipher_iv.length);\n+\tif (auth_iv && ctx->auth_iv.length > 0)\n+\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"auth iv:\", auth_iv->va,\n+\t\t\t\tctx->auth_iv.length);\n+\tif (aad && ctx->aad_len > 0)\n+\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"aad:\", aad->va,\n+\t\t\t\tctx->aad_len);\n+\tif (digest && ctx->digest_length > 0)\n+\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"digest:\", digest->va,\n+\t\t\t\tctx->digest_length);\n+}\n+#else\n+static __rte_always_inline void\n+qat_sym_debug_log_dump(struct icp_qat_fw_la_bulk_req *qat_req __rte_unused,\n+\t\tstruct qat_sym_session *ctx __rte_unused,\n+\t\tstruct rte_crypto_vec *vec __rte_unused,\n+\t\tuint32_t vec_len __rte_unused,\n+\t\tstruct rte_crypto_va_iova_ptr *cipher_iv __rte_unused,\n+\t\tstruct rte_crypto_va_iova_ptr *auth_iv __rte_unused,\n+\t\tstruct rte_crypto_va_iova_ptr *aad __rte_unused,\n+\t\tstruct rte_crypto_va_iova_ptr *digest __rte_unused)\n+{\n+}\n+#endif\n+\n #else\n \n static inline void\n@@ -307,5 +430,5 @@ qat_sym_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,\n {\n }\n \n-#endif\n+#endif /* BUILD_QAT_SYM */\n #endif /* _QAT_SYM_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym_hw_dp.c b/drivers/crypto/qat/qat_sym_hw_dp.c\nindex 792ad2b213..5322faff44 100644\n--- a/drivers/crypto/qat/qat_sym_hw_dp.c\n+++ b/drivers/crypto/qat/qat_sym_hw_dp.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2020 Intel Corporation\n+ * Copyright(c) 2022 Intel Corporation\n */\n \n #include <cryptodev_pmd.h>\n@@ -9,18 +9,9 @@\n #include \"icp_qat_fw_la.h\"\n \n #include \"qat_sym.h\"\n-#include \"qat_sym_pmd.h\"\n #include \"qat_sym_session.h\"\n #include \"qat_qp.h\"\n \n-struct qat_sym_dp_ctx {\n-\tstruct qat_sym_session *session;\n-\tuint32_t tail;\n-\tuint32_t head;\n-\tuint16_t cached_enqueue;\n-\tuint16_t cached_dequeue;\n-};\n-\n static __rte_always_inline int32_t\n qat_sym_dp_parse_data_vec(struct qat_qp *qp, struct icp_qat_fw_la_bulk_req *req,\n \t\tstruct rte_crypto_vec *data, uint16_t n_data_vecs)\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\ndeleted file mode 100644\nindex 28a26260fb..0000000000\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ /dev/null\n@@ -1,251 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2018 Intel Corporation\n- */\n-\n-#include <rte_bus_pci.h>\n-#include <rte_common.h>\n-#include <rte_dev.h>\n-#include <rte_malloc.h>\n-#include <rte_pci.h>\n-#include <cryptodev_pmd.h>\n-#ifdef RTE_LIB_SECURITY\n-#include <rte_security_driver.h>\n-#endif\n-\n-#include \"qat_logs.h\"\n-#include \"qat_crypto.h\"\n-#include \"qat_sym.h\"\n-#include \"qat_sym_session.h\"\n-#include \"qat_sym_pmd.h\"\n-\n-#define MIXED_CRYPTO_MIN_FW_VER 0x04090000\n-\n-uint8_t qat_sym_driver_id;\n-\n-struct qat_crypto_gen_dev_ops qat_sym_gen_dev_ops[QAT_N_GENS];\n-\n-void\n-qat_sym_init_op_cookie(void *op_cookie)\n-{\n-\tstruct qat_sym_op_cookie *cookie = op_cookie;\n-\n-\tcookie->qat_sgl_src_phys_addr =\n-\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\toffsetof(struct qat_sym_op_cookie,\n-\t\t\tqat_sgl_src);\n-\n-\tcookie->qat_sgl_dst_phys_addr =\n-\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\toffsetof(struct qat_sym_op_cookie,\n-\t\t\tqat_sgl_dst);\n-\n-\tcookie->opt.spc_gmac.cd_phys_addr =\n-\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\toffsetof(struct qat_sym_op_cookie,\n-\t\t\topt.spc_gmac.cd_cipher);\n-}\n-\n-static uint16_t\n-qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n-\t\tuint16_t nb_ops)\n-{\n-\treturn qat_enqueue_op_burst(qp, NULL, (void **)ops, nb_ops);\n-}\n-\n-static uint16_t\n-qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n-\t\tuint16_t nb_ops)\n-{\n-\treturn qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops);\n-}\n-\n-/* An rte_driver is needed in the registration of both the device and the driver\n- * with cryptodev.\n- * The actual qat pci's rte_driver can't be used as its name represents\n- * the whole pci device with all services. Think of this as a holder for a name\n- * for the crypto part of the pci device.\n- */\n-static const char qat_sym_drv_name[] = RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD);\n-static const struct rte_driver cryptodev_qat_sym_driver = {\n-\t.name = qat_sym_drv_name,\n-\t.alias = qat_sym_drv_name\n-};\n-\n-int\n-qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,\n-\t\tstruct qat_dev_cmd_param *qat_dev_cmd_param __rte_unused)\n-{\n-\tint i = 0, ret = 0;\n-\tstruct qat_device_info *qat_dev_instance =\n-\t\t\t&qat_pci_devs[qat_pci_dev->qat_dev_id];\n-\tstruct rte_cryptodev_pmd_init_params init_params = {\n-\t\t.name = \"\",\n-\t\t.socket_id = qat_dev_instance->pci_dev->device.numa_node,\n-\t\t.private_data_size = sizeof(struct qat_cryptodev_private)\n-\t};\n-\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n-\tchar capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];\n-\tstruct rte_cryptodev *cryptodev;\n-\tstruct qat_cryptodev_private *internals;\n-\tstruct qat_capabilities_info capa_info;\n-\tconst struct rte_cryptodev_capabilities *capabilities;\n-\tconst struct qat_crypto_gen_dev_ops *gen_dev_ops =\n-\t\t&qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen];\n-\tuint64_t capa_size;\n-\n-\tsnprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, \"%s_%s\",\n-\t\t\tqat_pci_dev->name, \"sym\");\n-\tQAT_LOG(DEBUG, \"Creating QAT SYM device %s\", name);\n-\n-\tif (gen_dev_ops->cryptodev_ops == NULL) {\n-\t\tQAT_LOG(ERR, \"Device %s does not support symmetric crypto\",\n-\t\t\t\tname);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\t/*\n-\t * All processes must use same driver id so they can share sessions.\n-\t * Store driver_id so we can validate that all processes have the same\n-\t * value, typically they have, but could differ if binaries built\n-\t * separately.\n-\t */\n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\tqat_pci_dev->qat_sym_driver_id =\n-\t\t\t\tqat_sym_driver_id;\n-\t} else if (rte_eal_process_type() == RTE_PROC_SECONDARY) {\n-\t\tif (qat_pci_dev->qat_sym_driver_id !=\n-\t\t\t\tqat_sym_driver_id) {\n-\t\t\tQAT_LOG(ERR,\n-\t\t\t\t\"Device %s have different driver id than corresponding device in primary process\",\n-\t\t\t\tname);\n-\t\t\treturn -(EFAULT);\n-\t\t}\n-\t}\n-\n-\t/* Populate subset device to use in cryptodev device creation */\n-\tqat_dev_instance->sym_rte_dev.driver = &cryptodev_qat_sym_driver;\n-\tqat_dev_instance->sym_rte_dev.numa_node =\n-\t\t\tqat_dev_instance->pci_dev->device.numa_node;\n-\tqat_dev_instance->sym_rte_dev.devargs = NULL;\n-\n-\tcryptodev = rte_cryptodev_pmd_create(name,\n-\t\t\t&(qat_dev_instance->sym_rte_dev), &init_params);\n-\n-\tif (cryptodev == NULL)\n-\t\treturn -ENODEV;\n-\n-\tqat_dev_instance->sym_rte_dev.name = cryptodev->data->name;\n-\tcryptodev->driver_id = qat_sym_driver_id;\n-\tcryptodev->dev_ops = gen_dev_ops->cryptodev_ops;\n-\n-\tcryptodev->enqueue_burst = qat_sym_pmd_enqueue_op_burst;\n-\tcryptodev->dequeue_burst = qat_sym_pmd_dequeue_op_burst;\n-\n-\tcryptodev->feature_flags = gen_dev_ops->get_feature_flags(qat_pci_dev);\n-\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-#ifdef RTE_LIB_SECURITY\n-\tif (gen_dev_ops->create_security_ctx) {\n-\t\tcryptodev->security_ctx =\n-\t\t\tgen_dev_ops->create_security_ctx((void *)cryptodev);\n-\t\tif (cryptodev->security_ctx == NULL) {\n-\t\t\tQAT_LOG(ERR, \"rte_security_ctx memory alloc failed\");\n-\t\t\tret = -ENOMEM;\n-\t\t\tgoto error;\n-\t\t}\n-\n-\t\tcryptodev->feature_flags |= RTE_CRYPTODEV_FF_SECURITY;\n-\t\tQAT_LOG(INFO, \"Device %s rte_security support enabled\", name);\n-\t} else\n-\t\tQAT_LOG(INFO, \"Device %s rte_security support disabled\", name);\n-\n-#endif\n-\tsnprintf(capa_memz_name, RTE_CRYPTODEV_NAME_MAX_LEN,\n-\t\t\t\"QAT_SYM_CAPA_GEN_%d\",\n-\t\t\tqat_pci_dev->qat_dev_gen);\n-\n-\tinternals = cryptodev->data->dev_private;\n-\tinternals->qat_dev = qat_pci_dev;\n-\tinternals->service_type = QAT_SERVICE_SYMMETRIC;\n-\tinternals->dev_id = cryptodev->data->dev_id;\n-\n-\tcapa_info = gen_dev_ops->get_capabilities(qat_pci_dev);\n-\tcapabilities = capa_info.data;\n-\tcapa_size = capa_info.size;\n-\n-\tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n-\tif (internals->capa_mz == NULL) {\n-\t\tinternals->capa_mz = rte_memzone_reserve(capa_memz_name,\n-\t\t\t\tcapa_size, rte_socket_id(), 0);\n-\t\tif (internals->capa_mz == NULL) {\n-\t\t\tQAT_LOG(DEBUG,\n-\t\t\t\t\"Error allocating capability memzon for %s\",\n-\t\t\t\tname);\n-\t\t\tret = -EFAULT;\n-\t\t\tgoto error;\n-\t\t}\n-\t}\n-\n-\tmemcpy(internals->capa_mz->addr, capabilities, capa_size);\n-\tinternals->qat_dev_capabilities = internals->capa_mz->addr;\n-\n-\twhile (1) {\n-\t\tif (qat_dev_cmd_param[i].name == NULL)\n-\t\t\tbreak;\n-\t\tif (!strcmp(qat_dev_cmd_param[i].name, SYM_ENQ_THRESHOLD_NAME))\n-\t\t\tinternals->min_enq_burst_threshold =\n-\t\t\t\t\tqat_dev_cmd_param[i].val;\n-\t\ti++;\n-\t}\n-\n-\tqat_pci_dev->sym_dev = internals;\n-\tQAT_LOG(DEBUG, \"Created QAT SYM device %s as cryptodev instance %d\",\n-\t\t\tcryptodev->data->name, internals->dev_id);\n-\n-\trte_cryptodev_pmd_probing_finish(cryptodev);\n-\n-\treturn 0;\n-\n-error:\n-#ifdef RTE_LIB_SECURITY\n-\trte_free(cryptodev->security_ctx);\n-\tcryptodev->security_ctx = NULL;\n-#endif\n-\trte_cryptodev_pmd_destroy(cryptodev);\n-\tmemset(&qat_dev_instance->sym_rte_dev, 0,\n-\t\tsizeof(qat_dev_instance->sym_rte_dev));\n-\n-\treturn ret;\n-}\n-\n-int\n-qat_sym_dev_destroy(struct qat_pci_device *qat_pci_dev)\n-{\n-\tstruct rte_cryptodev *cryptodev;\n-\n-\tif (qat_pci_dev == NULL)\n-\t\treturn -ENODEV;\n-\tif (qat_pci_dev->sym_dev == NULL)\n-\t\treturn 0;\n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n-\t\trte_memzone_free(qat_pci_dev->sym_dev->capa_mz);\n-\n-\t/* free crypto device */\n-\tcryptodev = rte_cryptodev_pmd_get_dev(qat_pci_dev->sym_dev->dev_id);\n-#ifdef RTE_LIB_SECURITY\n-\trte_free(cryptodev->security_ctx);\n-\tcryptodev->security_ctx = NULL;\n-#endif\n-\trte_cryptodev_pmd_destroy(cryptodev);\n-\tqat_pci_devs[qat_pci_dev->qat_dev_id].sym_rte_dev.name = NULL;\n-\tqat_pci_dev->sym_dev = NULL;\n-\n-\treturn 0;\n-}\n-\n-static struct cryptodev_driver qat_crypto_drv;\n-RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,\n-\t\tcryptodev_qat_sym_driver,\n-\t\tqat_sym_driver_id);\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h\ndeleted file mode 100644\nindex 59fbdefa12..0000000000\n--- a/drivers/crypto/qat/qat_sym_pmd.h\n+++ /dev/null\n@@ -1,95 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2018 Intel Corporation\n- */\n-\n-#ifndef _QAT_SYM_PMD_H_\n-#define _QAT_SYM_PMD_H_\n-\n-#ifdef BUILD_QAT_SYM\n-\n-#include <rte_ether.h>\n-#include <rte_cryptodev.h>\n-#ifdef RTE_LIB_SECURITY\n-#include <rte_security.h>\n-#endif\n-\n-#include \"qat_crypto.h\"\n-#include \"qat_device.h\"\n-\n-/** Intel(R) QAT Symmetric Crypto PMD name */\n-#define CRYPTODEV_NAME_QAT_SYM_PMD\tcrypto_qat\n-\n-/* Internal capabilities */\n-#define QAT_SYM_CAP_MIXED_CRYPTO\t(1 << 0)\n-#define QAT_SYM_CAP_VALID\t\t(1 << 31)\n-\n-/**\n- * Macro to add a sym capability\n- * helper function to add an sym capability\n- * <n: name> <b: block size> <k: key size> <d: digest size>\n- * <a: aad_size> <i: iv_size>\n- **/\n-#define QAT_SYM_PLAIN_AUTH_CAP(n, b, d)\t\t\t\t\t\\\n-\t{\t\t\t\t\t\t\t\t\\\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n-\t\t{.sym = {\t\t\t\t\t\t\\\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n-\t\t\t{.auth = {\t\t\t\t\t\\\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_##n,\t\t\\\n-\t\t\t\tb, d\t\t\t\t\t\\\n-\t\t\t}, }\t\t\t\t\t\t\\\n-\t\t}, }\t\t\t\t\t\t\t\\\n-\t}\n-\n-#define QAT_SYM_AUTH_CAP(n, b, k, d, a, i)\t\t\t\t\\\n-\t{\t\t\t\t\t\t\t\t\\\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n-\t\t{.sym = {\t\t\t\t\t\t\\\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n-\t\t\t{.auth = {\t\t\t\t\t\\\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_##n,\t\t\\\n-\t\t\t\tb, k, d, a, i\t\t\t\t\\\n-\t\t\t}, }\t\t\t\t\t\t\\\n-\t\t}, }\t\t\t\t\t\t\t\\\n-\t}\n-\n-#define QAT_SYM_AEAD_CAP(n, b, k, d, a, i)\t\t\t\t\\\n-\t{\t\t\t\t\t\t\t\t\\\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n-\t\t{.sym = {\t\t\t\t\t\t\\\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\t\\\n-\t\t\t{.aead = {\t\t\t\t\t\\\n-\t\t\t\t.algo = RTE_CRYPTO_AEAD_##n,\t\t\\\n-\t\t\t\tb, k, d, a, i\t\t\t\t\\\n-\t\t\t}, }\t\t\t\t\t\t\\\n-\t\t}, }\t\t\t\t\t\t\t\\\n-\t}\n-\n-#define QAT_SYM_CIPHER_CAP(n, b, k, i)\t\t\t\t\t\\\n-\t{\t\t\t\t\t\t\t\t\\\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n-\t\t{.sym = {\t\t\t\t\t\t\\\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\t\\\n-\t\t\t{.cipher = {\t\t\t\t\t\\\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_##n,\t\t\\\n-\t\t\t\tb, k, i\t\t\t\t\t\\\n-\t\t\t}, }\t\t\t\t\t\t\\\n-\t\t}, }\t\t\t\t\t\t\t\\\n-\t}\n-\n-extern uint8_t qat_sym_driver_id;\n-\n-extern struct qat_crypto_gen_dev_ops qat_sym_gen_dev_ops[];\n-\n-int\n-qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,\n-\t\tstruct qat_dev_cmd_param *qat_dev_cmd_param);\n-\n-int\n-qat_sym_dev_destroy(struct qat_pci_device *qat_pci_dev);\n-\n-void\n-qat_sym_init_op_cookie(void *op_cookie);\n-\n-#endif\n-#endif /* _QAT_SYM_PMD_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 3a880096c4..9d6a19c0be 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -20,7 +20,7 @@\n \n #include \"qat_logs.h\"\n #include \"qat_sym_session.h\"\n-#include \"qat_sym_pmd.h\"\n+#include \"qat_sym.h\"\n \n /* SHA1 - 20 bytes - Initialiser state can be found in FIPS stds 180-2 */\n static const uint8_t sha1InitialState[] = {\n", "prefixes": [ "v9", "5/9" ] }