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{
    "id": 107819,
    "url": "http://patches.dpdk.org/api/patches/107819/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220218171527.56719-4-kai.ji@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220218171527.56719-4-kai.ji@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220218171527.56719-4-kai.ji@intel.com",
    "date": "2022-02-18T17:15:21",
    "name": "[v9,3/9] crypto/qat: rework session functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "fd579ef65598dfa61d3eef0ce0aecf6d48dd7b39",
    "submitter": {
        "id": 2202,
        "url": "http://patches.dpdk.org/api/people/2202/?format=api",
        "name": "Ji, Kai",
        "email": "kai.ji@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220218171527.56719-4-kai.ji@intel.com/mbox/",
    "series": [
        {
            "id": 21741,
            "url": "http://patches.dpdk.org/api/series/21741/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21741",
            "date": "2022-02-18T17:15:18",
            "name": "drivers/qat: QAT symmetric crypto datapatch rework",
            "version": 9,
            "mbox": "http://patches.dpdk.org/series/21741/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/107819/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/107819/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1645204548; x=1676740548;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=549xPUgoHXwNImIUiRDy1SaQpo1aSbIITWF9T1XtbZw=;\n b=h4DHfOIZazRZHMOYIZ4HnWd8F8lf3HmOdpXp9ewI+QwVOPxISikVqnad\n R9FgSyR7lHxQ/Ij6ZfCqdEMnSwCrveY0aPk3l+OWpsXOGlhgG/p6/kFSB\n aVfo95VHP6Z+jPc8t+Gs1ob3+3ryEbyhBNpqovayVW9Ikf8ohFCGP1kgU\n Pn+h5SricUeJ63paOaj08ZagDoyZt/SNj0vYCQOrWw0wihdeEuXYWg+Gu\n azA98WDJoXYbodj1uzaswG8zlOiIuXVNzsHyp3b9ZxsnPSOhNQkdUf8xg\n rgZYmela8XEDn3lZZ9RNRRMNtWO6HBCoZEi4THtegfaXgV4qT5xa4eRU/ w==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10262\"; a=\"238571896\"",
            "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"238571896\"",
            "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"705446217\""
        ],
        "X-ExtLoop1": "1",
        "From": "Kai Ji <kai.ji@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "gakhil@marvell.com,\n\troy.fan.zhang@intel.com,\n\tKai Ji <kai.ji@intel.com>",
        "Subject": "[dpdk-dev v9 3/9] crypto/qat: rework session functions",
        "Date": "Sat, 19 Feb 2022 01:15:21 +0800",
        "Message-Id": "<20220218171527.56719-4-kai.ji@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20220218171527.56719-1-kai.ji@intel.com>",
        "References": "<20220217162909.22713-1-kai.ji@intel.com>\n <20220218171527.56719-1-kai.ji@intel.com>",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "This patch introduces a set of set_session methods to QAT\ngenerations. In addition, the reuse of QAT session between\ngenerations is prohibit as the support of min_qat_dev_gen_id'\nis removed.\n\nSigned-off-by: Kai Ji <kai.ji@intel.com>\n---\n drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   |   9 +-\n drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |  91 ++++++-\n drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 256 ++++++++++++++++++-\n drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 125 ++++++++-\n drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |   3 +\n drivers/crypto/qat/dev/qat_sym_pmd_gen1.c    |  64 +++++\n drivers/crypto/qat/qat_crypto.h              |   8 +-\n drivers/crypto/qat/qat_sym.c                 |  12 +-\n drivers/crypto/qat/qat_sym_session.c         | 113 ++------\n drivers/crypto/qat/qat_sym_session.h         |   2 +-\n 10 files changed, 574 insertions(+), 109 deletions(-)",
    "diff": "diff --git a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c\nindex 9ed1f21d9d..01a897a21f 100644\n--- a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c\n+++ b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2017-2021 Intel Corporation\n+ * Copyright(c) 2017-2022 Intel Corporation\n  */\n \n #include <rte_cryptodev.h>\n@@ -65,6 +65,13 @@ qat_asym_crypto_feature_flags_get_gen1(\n \treturn feature_flags;\n }\n \n+int\n+qat_asym_crypto_set_session_gen1(void *cdev __rte_unused,\n+\t\tvoid *session __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n RTE_INIT(qat_asym_crypto_gen1_init)\n {\n \tqat_asym_gen_dev_ops[QAT_GEN1].cryptodev_ops =\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\nindex b4ec440e05..64e6ae66ec 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2017-2021 Intel Corporation\n+ * Copyright(c) 2017-2022 Intel Corporation\n  */\n \n #include <rte_cryptodev.h>\n@@ -166,6 +166,91 @@ qat_sym_crypto_qp_setup_gen2(struct rte_cryptodev *dev, uint16_t qp_id,\n \treturn 0;\n }\n \n+void\n+qat_sym_session_set_ext_hash_flags_gen2(struct qat_sym_session *session,\n+\t\tuint8_t hash_flag)\n+{\n+\tstruct icp_qat_fw_comn_req_hdr *header = &session->fw_req.comn_hdr;\n+\tstruct icp_qat_fw_cipher_auth_cd_ctrl_hdr *cd_ctrl =\n+\t\t\t(struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *)\n+\t\t\tsession->fw_req.cd_ctrl.content_desc_ctrl_lw;\n+\n+\t/* Set the Use Extended Protocol Flags bit in LW 1 */\n+\tQAT_FIELD_SET(header->comn_req_flags,\n+\t\t\tQAT_COMN_EXT_FLAGS_USED,\n+\t\t\tQAT_COMN_EXT_FLAGS_BITPOS,\n+\t\t\tQAT_COMN_EXT_FLAGS_MASK);\n+\n+\t/* Set Hash Flags in LW 28 */\n+\tcd_ctrl->hash_flags |= hash_flag;\n+\n+\t/* Set proto flags in LW 1 */\n+\tswitch (session->qat_cipher_alg) {\n+\tcase ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_SNOW_3G_PROTO);\n+\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n+\t\t\t\theader->serv_specif_flags, 0);\n+\t\tbreak;\n+\tcase ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n+\t\t\t\theader->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_ZUC_3G_PROTO);\n+\t\tbreak;\n+\tdefault:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n+\t\t\t\theader->serv_specif_flags, 0);\n+\t\tbreak;\n+\t}\n+}\n+\n+static int\n+qat_sym_crypto_set_session_gen2(void *cdev, void *session)\n+{\n+\tstruct rte_cryptodev *dev = cdev;\n+\tstruct qat_sym_session *ctx = session;\n+\tconst struct qat_cryptodev_private *qat_private =\n+\t\t\tdev->data->dev_private;\n+\tint ret;\n+\n+\tret = qat_sym_crypto_set_session_gen1(cdev, session);\n+\tif (ret == -ENOTSUP) {\n+\t\t/* GEN1 returning -ENOTSUP as it cannot handle some mixed algo,\n+\t\t * but some are not supported by GEN2, so checking here\n+\t\t */\n+\t\tif ((qat_private->internal_capabilities &\n+\t\t\t\tQAT_SYM_CAP_MIXED_CRYPTO) == 0)\n+\t\t\treturn -ENOTSUP;\n+\n+\t\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&\n+\t\t\t\tctx->qat_cipher_alg !=\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx,\n+\t\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);\n+\t\t} else if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&\n+\t\t\t\tctx->qat_cipher_alg !=\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx,\n+\t\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);\n+\t\t} else if ((ctx->aes_cmac ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n+\t\t\t\t(ctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n+\t\t\t\tctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx, 0);\n+\t\t}\n+\n+\t\tret = 0;\n+\t}\n+\n+\treturn ret;\n+}\n+\n struct rte_cryptodev_ops qat_sym_crypto_ops_gen2 = {\n \n \t/* Device related operations */\n@@ -204,6 +289,8 @@ RTE_INIT(qat_sym_crypto_gen2_init)\n \tqat_sym_gen_dev_ops[QAT_GEN2].cryptodev_ops = &qat_sym_crypto_ops_gen2;\n \tqat_sym_gen_dev_ops[QAT_GEN2].get_capabilities =\n \t\t\tqat_sym_crypto_cap_get_gen2;\n+\tqat_sym_gen_dev_ops[QAT_GEN2].set_session =\n+\t\t\tqat_sym_crypto_set_session_gen2;\n \tqat_sym_gen_dev_ops[QAT_GEN2].get_feature_flags =\n \t\t\tqat_sym_crypto_feature_flags_get_gen1;\n \n@@ -221,4 +308,6 @@ RTE_INIT(qat_asym_crypto_gen2_init)\n \t\t\tqat_asym_crypto_cap_get_gen1;\n \tqat_asym_gen_dev_ops[QAT_GEN2].get_feature_flags =\n \t\t\tqat_asym_crypto_feature_flags_get_gen1;\n+\tqat_asym_gen_dev_ops[QAT_GEN2].set_session =\n+\t\t\tqat_asym_crypto_set_session_gen1;\n }\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\nindex d3336cf4a1..db864d973a 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2017-2021 Intel Corporation\n+ * Copyright(c) 2017-2022 Intel Corporation\n  */\n \n #include <rte_cryptodev.h>\n@@ -143,6 +143,257 @@ qat_sym_crypto_cap_get_gen3(struct qat_pci_device *qat_dev __rte_unused)\n \treturn capa_info;\n }\n \n+static __rte_always_inline void\n+enqueue_one_aead_job_gen3(struct qat_sym_session *ctx,\n+\tstruct icp_qat_fw_la_bulk_req *req,\n+\tstruct rte_crypto_va_iova_ptr *iv,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *aad,\n+\tunion rte_crypto_sym_ofs ofs, uint32_t data_len)\n+{\n+\tif (ctx->is_single_pass) {\n+\t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param =\n+\t\t\t(void *)&req->serv_specif_rqpars;\n+\n+\t\t/* QAT GEN3 uses single pass to treat AEAD as\n+\t\t * cipher operation\n+\t\t */\n+\t\tcipher_param = (void *)&req->serv_specif_rqpars;\n+\n+\t\tqat_set_cipher_iv(cipher_param, iv, ctx->cipher_iv.length, req);\n+\t\tcipher_param->cipher_offset = ofs.ofs.cipher.head;\n+\t\tcipher_param->cipher_length = data_len - ofs.ofs.cipher.head -\n+\t\t\t\tofs.ofs.cipher.tail;\n+\n+\t\tcipher_param->spc_aad_addr = aad->iova;\n+\t\tcipher_param->spc_auth_res_addr = digest->iova;\n+\n+\t\treturn;\n+\t}\n+\n+\tenqueue_one_aead_job_gen1(ctx, req, iv, digest, aad, ofs, data_len);\n+}\n+\n+static __rte_always_inline void\n+enqueue_one_auth_job_gen3(struct qat_sym_session *ctx,\n+\tstruct qat_sym_op_cookie *cookie,\n+\tstruct icp_qat_fw_la_bulk_req *req,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *auth_iv,\n+\tunion rte_crypto_sym_ofs ofs, uint32_t data_len)\n+{\n+\tstruct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl;\n+\tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n+\tuint32_t ver_key_offset;\n+\tuint32_t auth_data_len = data_len - ofs.ofs.auth.head -\n+\t\t\tofs.ofs.auth.tail;\n+\n+\tif (!ctx->is_single_pass_gmac ||\n+\t\t\t(auth_data_len > QAT_AES_GMAC_SPC_MAX_SIZE)) {\n+\t\tenqueue_one_auth_job_gen1(ctx, req, digest, auth_iv, ofs,\n+\t\t\t\tdata_len);\n+\t\treturn;\n+\t}\n+\n+\tcipher_cd_ctrl = (void *) &req->cd_ctrl;\n+\tcipher_param = (void *)&req->serv_specif_rqpars;\n+\tver_key_offset = sizeof(struct icp_qat_hw_auth_setup) +\n+\t\t\tICP_QAT_HW_GALOIS_128_STATE1_SZ +\n+\t\t\tICP_QAT_HW_GALOIS_H_SZ + ICP_QAT_HW_GALOIS_LEN_A_SZ +\n+\t\t\tICP_QAT_HW_GALOIS_E_CTR0_SZ +\n+\t\t\tsizeof(struct icp_qat_hw_cipher_config);\n+\n+\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||\n+\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {\n+\t\t/* AES-GMAC */\n+\t\tqat_set_cipher_iv(cipher_param, auth_iv, ctx->auth_iv.length,\n+\t\t\t\treq);\n+\t}\n+\n+\t/* Fill separate Content Descriptor for this op */\n+\trte_memcpy(cookie->opt.spc_gmac.cd_cipher.key,\n+\t\t\tctx->auth_op == ICP_QAT_HW_AUTH_GENERATE ?\n+\t\t\t\tctx->cd.cipher.key :\n+\t\t\t\tRTE_PTR_ADD(&ctx->cd, ver_key_offset),\n+\t\t\tctx->auth_key_length);\n+\tcookie->opt.spc_gmac.cd_cipher.cipher_config.val =\n+\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD(\n+\t\t\t\tICP_QAT_HW_CIPHER_AEAD_MODE,\n+\t\t\t\tctx->qat_cipher_alg,\n+\t\t\t\tICP_QAT_HW_CIPHER_NO_CONVERT,\n+\t\t\t\t(ctx->auth_op == ICP_QAT_HW_AUTH_GENERATE ?\n+\t\t\t\t\tICP_QAT_HW_CIPHER_ENCRYPT :\n+\t\t\t\t\tICP_QAT_HW_CIPHER_DECRYPT));\n+\tQAT_FIELD_SET(cookie->opt.spc_gmac.cd_cipher.cipher_config.val,\n+\t\t\tctx->digest_length,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);\n+\tcookie->opt.spc_gmac.cd_cipher.cipher_config.reserved =\n+\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(auth_data_len);\n+\n+\t/* Update the request */\n+\treq->cd_pars.u.s.content_desc_addr =\n+\t\t\tcookie->opt.spc_gmac.cd_phys_addr;\n+\treq->cd_pars.u.s.content_desc_params_sz = RTE_ALIGN_CEIL(\n+\t\t\tsizeof(struct icp_qat_hw_cipher_config) +\n+\t\t\tctx->auth_key_length, 8) >> 3;\n+\treq->comn_mid.src_length = data_len;\n+\treq->comn_mid.dst_length = 0;\n+\n+\tcipher_param->spc_aad_addr = 0;\n+\tcipher_param->spc_auth_res_addr = digest->iova;\n+\tcipher_param->spc_aad_sz = auth_data_len;\n+\tcipher_param->reserved = 0;\n+\tcipher_param->spc_auth_res_sz = ctx->digest_length;\n+\n+\treq->comn_hdr.service_cmd_id = ICP_QAT_FW_LA_CMD_CIPHER;\n+\tcipher_cd_ctrl->cipher_cfg_offset = 0;\n+\tICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);\n+\tICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);\n+\tICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(\n+\t\t\treq->comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_SINGLE_PASS_PROTO);\n+\tICP_QAT_FW_LA_PROTO_SET(\n+\t\t\treq->comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+}\n+\n+static int\n+qat_sym_build_op_aead_gen3(void *in_op, struct qat_sym_session *ctx,\n+\t\tuint8_t *out_msg, void *op_cookie)\n+{\n+\tregister struct icp_qat_fw_la_bulk_req *req;\n+\tstruct rte_crypto_op *op = in_op;\n+\tstruct qat_sym_op_cookie *cookie = op_cookie;\n+\tstruct rte_crypto_sgl in_sgl, out_sgl;\n+\tstruct rte_crypto_vec in_vec[QAT_SYM_SGL_MAX_NUMBER],\n+\t\t\tout_vec[QAT_SYM_SGL_MAX_NUMBER];\n+\tstruct rte_crypto_va_iova_ptr cipher_iv;\n+\tstruct rte_crypto_va_iova_ptr aad;\n+\tstruct rte_crypto_va_iova_ptr digest;\n+\tunion rte_crypto_sym_ofs ofs;\n+\tint32_t total_len;\n+\n+\tin_sgl.vec = in_vec;\n+\tout_sgl.vec = out_vec;\n+\n+\treq = (struct icp_qat_fw_la_bulk_req *)out_msg;\n+\trte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));\n+\n+\tofs.raw = qat_sym_convert_op_to_vec_aead(op, ctx, &in_sgl, &out_sgl,\n+\t\t\t&cipher_iv, &aad, &digest);\n+\tif (unlikely(ofs.raw == UINT64_MAX)) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttotal_len = qat_sym_build_req_set_data(req, in_op, cookie,\n+\t\t\tin_sgl.vec, in_sgl.num, out_sgl.vec, out_sgl.num);\n+\tif (unlikely(total_len < 0)) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tenqueue_one_aead_job_gen3(ctx, req, &cipher_iv, &digest, &aad, ofs,\n+\t\ttotal_len);\n+\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tqat_sym_debug_log_dump(req, ctx, in_sgl.vec, in_sgl.num, &cipher_iv,\n+\t\t\tNULL, &aad, &digest);\n+#endif\n+\n+\treturn 0;\n+}\n+\n+static int\n+qat_sym_build_op_auth_gen3(void *in_op, struct qat_sym_session *ctx,\n+\t\tuint8_t *out_msg, void *op_cookie)\n+{\n+\tregister struct icp_qat_fw_la_bulk_req *req;\n+\tstruct rte_crypto_op *op = in_op;\n+\tstruct qat_sym_op_cookie *cookie = op_cookie;\n+\tstruct rte_crypto_sgl in_sgl, out_sgl;\n+\tstruct rte_crypto_vec in_vec[QAT_SYM_SGL_MAX_NUMBER],\n+\t\t\tout_vec[QAT_SYM_SGL_MAX_NUMBER];\n+\tstruct rte_crypto_va_iova_ptr auth_iv;\n+\tstruct rte_crypto_va_iova_ptr digest;\n+\tunion rte_crypto_sym_ofs ofs;\n+\tint32_t total_len;\n+\n+\tin_sgl.vec = in_vec;\n+\tout_sgl.vec = out_vec;\n+\n+\treq = (struct icp_qat_fw_la_bulk_req *)out_msg;\n+\trte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));\n+\n+\tofs.raw = qat_sym_convert_op_to_vec_auth(op, ctx, &in_sgl, &out_sgl,\n+\t\t\tNULL, &auth_iv, &digest);\n+\tif (unlikely(ofs.raw == UINT64_MAX)) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttotal_len = qat_sym_build_req_set_data(req, in_op, cookie,\n+\t\t\tin_sgl.vec, in_sgl.num, out_sgl.vec, out_sgl.num);\n+\tif (unlikely(total_len < 0)) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tenqueue_one_auth_job_gen3(ctx, cookie, req, &digest, &auth_iv,\n+\t\t\tofs, total_len);\n+\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tqat_sym_debug_log_dump(req, ctx, in_sgl.vec, in_sgl.num, NULL,\n+\t\t\t&auth_iv, NULL, &digest);\n+#endif\n+\n+\treturn 0;\n+}\n+\n+static int\n+qat_sym_crypto_set_session_gen3(void *cdev __rte_unused, void *session)\n+{\n+\tstruct qat_sym_session *ctx = session;\n+\tenum rte_proc_type_t proc_type = rte_eal_process_type();\n+\tint ret;\n+\n+\tret = qat_sym_crypto_set_session_gen1(cdev, session);\n+\t/* special single pass build request for GEN3 */\n+\tif (ctx->is_single_pass)\n+\t\tctx->build_request[proc_type] = qat_sym_build_op_aead_gen3;\n+\telse if (ctx->is_single_pass_gmac)\n+\t\tctx->build_request[proc_type] = qat_sym_build_op_auth_gen3;\n+\n+\tif (ret == -ENOTSUP) {\n+\t\t/* GEN1 returning -ENOTSUP as it cannot handle some mixed algo,\n+\t\t * this is addressed by GEN3\n+\t\t */\n+\t\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&\n+\t\t\t\tctx->qat_cipher_alg !=\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx,\n+\t\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);\n+\t\t} else if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&\n+\t\t\t\tctx->qat_cipher_alg !=\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx,\n+\t\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);\n+\t\t} else if ((ctx->aes_cmac ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n+\t\t\t\t(ctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n+\t\t\t\tctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx, 0);\n+\t\t}\n+\n+\t\tret = 0;\n+\t}\n+\n+\treturn ret;\n+}\n+\n RTE_INIT(qat_sym_crypto_gen3_init)\n {\n \tqat_sym_gen_dev_ops[QAT_GEN3].cryptodev_ops = &qat_sym_crypto_ops_gen1;\n@@ -150,6 +401,8 @@ RTE_INIT(qat_sym_crypto_gen3_init)\n \t\t\tqat_sym_crypto_cap_get_gen3;\n \tqat_sym_gen_dev_ops[QAT_GEN3].get_feature_flags =\n \t\t\tqat_sym_crypto_feature_flags_get_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN3].set_session =\n+\t\t\tqat_sym_crypto_set_session_gen3;\n #ifdef RTE_LIB_SECURITY\n \tqat_sym_gen_dev_ops[QAT_GEN3].create_security_ctx =\n \t\t\tqat_sym_create_security_gen1;\n@@ -161,4 +414,5 @@ RTE_INIT(qat_asym_crypto_gen3_init)\n \tqat_asym_gen_dev_ops[QAT_GEN3].cryptodev_ops = NULL;\n \tqat_asym_gen_dev_ops[QAT_GEN3].get_capabilities = NULL;\n \tqat_asym_gen_dev_ops[QAT_GEN3].get_feature_flags = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN3].set_session = NULL;\n }\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\nindex 37a58c026f..7642a87d55 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2017-2021 Intel Corporation\n+ * Copyright(c) 2017-2022 Intel Corporation\n  */\n \n #include <rte_cryptodev.h>\n@@ -103,11 +103,133 @@ qat_sym_crypto_cap_get_gen4(struct qat_pci_device *qat_dev __rte_unused)\n \treturn capa_info;\n }\n \n+static __rte_always_inline void\n+enqueue_one_aead_job_gen4(struct qat_sym_session *ctx,\n+\tstruct icp_qat_fw_la_bulk_req *req,\n+\tstruct rte_crypto_va_iova_ptr *iv,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *aad,\n+\tunion rte_crypto_sym_ofs ofs, uint32_t data_len)\n+{\n+\tif (ctx->is_single_pass && ctx->is_ucs) {\n+\t\tstruct icp_qat_fw_la_cipher_20_req_params *cipher_param_20 =\n+\t\t\t(void *)&req->serv_specif_rqpars;\n+\t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param =\n+\t\t\t(void *)&req->serv_specif_rqpars;\n+\n+\t\t/* QAT GEN4 uses single pass to treat AEAD as cipher\n+\t\t * operation\n+\t\t */\n+\t\tqat_set_cipher_iv(cipher_param, iv, ctx->cipher_iv.length,\n+\t\t\t\treq);\n+\t\tcipher_param->cipher_offset = ofs.ofs.cipher.head;\n+\t\tcipher_param->cipher_length = data_len -\n+\t\t\t\tofs.ofs.cipher.head - ofs.ofs.cipher.tail;\n+\n+\t\tcipher_param_20->spc_aad_addr = aad->iova;\n+\t\tcipher_param_20->spc_auth_res_addr = digest->iova;\n+\n+\t\treturn;\n+\t}\n+\n+\tenqueue_one_aead_job_gen1(ctx, req, iv, digest, aad, ofs, data_len);\n+}\n+\n+static int\n+qat_sym_build_op_aead_gen4(void *in_op, struct qat_sym_session *ctx,\n+\t\tuint8_t *out_msg, void *op_cookie)\n+{\n+\tregister struct icp_qat_fw_la_bulk_req *qat_req;\n+\tstruct rte_crypto_op *op = in_op;\n+\tstruct qat_sym_op_cookie *cookie = op_cookie;\n+\tstruct rte_crypto_sgl in_sgl, out_sgl;\n+\tstruct rte_crypto_vec in_vec[QAT_SYM_SGL_MAX_NUMBER],\n+\t\t\tout_vec[QAT_SYM_SGL_MAX_NUMBER];\n+\tstruct rte_crypto_va_iova_ptr cipher_iv;\n+\tstruct rte_crypto_va_iova_ptr aad;\n+\tstruct rte_crypto_va_iova_ptr digest;\n+\tunion rte_crypto_sym_ofs ofs;\n+\tint32_t total_len;\n+\n+\tin_sgl.vec = in_vec;\n+\tout_sgl.vec = out_vec;\n+\n+\tqat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;\n+\trte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));\n+\n+\tofs.raw = qat_sym_convert_op_to_vec_aead(op, ctx, &in_sgl, &out_sgl,\n+\t\t\t&cipher_iv, &aad, &digest);\n+\tif (unlikely(ofs.raw == UINT64_MAX)) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttotal_len = qat_sym_build_req_set_data(qat_req, in_op, cookie,\n+\t\t\tin_sgl.vec, in_sgl.num, out_sgl.vec, out_sgl.num);\n+\tif (unlikely(total_len < 0)) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tenqueue_one_aead_job_gen4(ctx, qat_req, &cipher_iv, &digest, &aad, ofs,\n+\t\ttotal_len);\n+\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tqat_sym_debug_log_dump(qat_req, ctx, in_sgl.vec, in_sgl.num, &cipher_iv,\n+\t\t\tNULL, &aad, &digest);\n+#endif\n+\n+\treturn 0;\n+}\n+\n+static int\n+qat_sym_crypto_set_session_gen4(void *cdev, void *session)\n+{\n+\tstruct qat_sym_session *ctx = session;\n+\tenum rte_proc_type_t proc_type = rte_eal_process_type();\n+\tint ret;\n+\n+\tret = qat_sym_crypto_set_session_gen1(cdev, session);\n+\t/* special single pass build request for GEN4 */\n+\tif (ctx->is_single_pass && ctx->is_ucs)\n+\t\tctx->build_request[proc_type] = qat_sym_build_op_aead_gen4;\n+\n+\tif (ret == -ENOTSUP) {\n+\t\t/* GEN1 returning -ENOTSUP as it cannot handle some mixed algo,\n+\t\t * this is addressed by GEN4\n+\t\t */\n+\t\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&\n+\t\t\t\tctx->qat_cipher_alg !=\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx,\n+\t\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);\n+\t\t} else if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&\n+\t\t\t\tctx->qat_cipher_alg !=\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx,\n+\t\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);\n+\t\t} else if ((ctx->aes_cmac ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n+\t\t\t\t(ctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n+\t\t\t\tctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx, 0);\n+\t\t}\n+\n+\t\tret = 0;\n+\t}\n+\n+\treturn ret;\n+}\n+\n RTE_INIT(qat_sym_crypto_gen4_init)\n {\n \tqat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1;\n \tqat_sym_gen_dev_ops[QAT_GEN4].get_capabilities =\n \t\t\tqat_sym_crypto_cap_get_gen4;\n+\tqat_sym_gen_dev_ops[QAT_GEN4].set_session =\n+\t\t\tqat_sym_crypto_set_session_gen4;\n \tqat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags =\n \t\t\tqat_sym_crypto_feature_flags_get_gen1;\n #ifdef RTE_LIB_SECURITY\n@@ -121,4 +243,5 @@ RTE_INIT(qat_asym_crypto_gen4_init)\n \tqat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = NULL;\n \tqat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = NULL;\n \tqat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN4].set_session = NULL;\n }\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\nindex 1130e0e76f..96cdb97a26 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n@@ -856,6 +856,9 @@ qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev);\n uint64_t\n qat_asym_crypto_feature_flags_get_gen1(struct qat_pci_device *qat_dev);\n \n+int\n+qat_asym_crypto_set_session_gen1(void *cryptodev, void *session);\n+\n #ifdef RTE_LIB_SECURITY\n extern struct rte_security_ops security_qat_ops_gen1;\n \ndiff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\nindex c429825a67..501132a448 100644\n--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n@@ -452,12 +452,76 @@ qat_sym_create_security_gen1(void *cryptodev)\n }\n \n #endif\n+int\n+qat_sym_crypto_set_session_gen1(void *cryptodev __rte_unused, void *session)\n+{\n+\tstruct qat_sym_session *ctx = session;\n+\tqat_sym_build_request_t build_request = NULL;\n+\tenum rte_proc_type_t proc_type = rte_eal_process_type();\n+\tint handle_mixed = 0;\n+\n+\tif ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||\n+\t\t\tctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) &&\n+\t\t\t!ctx->is_gmac) {\n+\t\t/* AES-GCM or AES-CCM */\n+\t\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||\n+\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||\n+\t\t\t(ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128\n+\t\t\t&& ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE\n+\t\t\t&& ctx->qat_hash_alg ==\n+\t\t\t\t\tICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {\n+\t\t\t/* do_aead = 1; */\n+\t\t\tbuild_request = qat_sym_build_op_aead_gen1;\n+\t\t} else {\n+\t\t\t/* do_auth = 1; do_cipher = 1; */\n+\t\t\tbuild_request = qat_sym_build_op_chain_gen1;\n+\t\t\thandle_mixed = 1;\n+\t\t}\n+\t} else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH || ctx->is_gmac) {\n+\t\t/* do_auth = 1; do_cipher = 0;*/\n+\t\tbuild_request = qat_sym_build_op_auth_gen1;\n+\t} else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {\n+\t\t/* do_auth = 0; do_cipher = 1; */\n+\t\tbuild_request = qat_sym_build_op_cipher_gen1;\n+\t}\n+\n+\tif (build_request)\n+\t\tctx->build_request[proc_type] = build_request;\n+\telse\n+\t\treturn -EINVAL;\n+\n+\t/* no more work if not mixed op */\n+\tif (!handle_mixed)\n+\t\treturn 0;\n+\n+\t/* Check none supported algs if mixed */\n+\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&\n+\t\t\tctx->qat_cipher_alg !=\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n+\t\treturn -ENOTSUP;\n+\t} else if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&\n+\t\t\tctx->qat_cipher_alg !=\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {\n+\t\treturn -ENOTSUP;\n+\t} else if ((ctx->aes_cmac ||\n+\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n+\t\t\t(ctx->qat_cipher_alg ==\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n+\t\t\tctx->qat_cipher_alg ==\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\treturn 0;\n+}\n \n RTE_INIT(qat_sym_crypto_gen1_init)\n {\n \tqat_sym_gen_dev_ops[QAT_GEN1].cryptodev_ops = &qat_sym_crypto_ops_gen1;\n \tqat_sym_gen_dev_ops[QAT_GEN1].get_capabilities =\n \t\t\tqat_sym_crypto_cap_get_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN1].set_session =\n+\t\t\tqat_sym_crypto_set_session_gen1;\n \tqat_sym_gen_dev_ops[QAT_GEN1].get_feature_flags =\n \t\t\tqat_sym_crypto_feature_flags_get_gen1;\n #ifdef RTE_LIB_SECURITY\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nindex 6eaa15b975..5ca76fcaa6 100644\n--- a/drivers/crypto/qat/qat_crypto.h\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2021 Intel Corporation\n+ * Copyright(c) 2022 Intel Corporation\n  */\n \n  #ifndef _QAT_CRYPTO_H_\n@@ -48,15 +48,21 @@ typedef uint64_t (*get_feature_flags_t)(struct qat_pci_device *qat_dev);\n \n typedef void * (*create_security_ctx_t)(void *cryptodev);\n \n+typedef int (*set_session_t)(void *cryptodev, void *session);\n+\n struct qat_crypto_gen_dev_ops {\n \tget_feature_flags_t get_feature_flags;\n \tget_capabilities_info_t get_capabilities;\n \tstruct rte_cryptodev_ops *cryptodev_ops;\n+\tset_session_t set_session;\n #ifdef RTE_LIB_SECURITY\n \tcreate_security_ctx_t create_security_ctx;\n #endif\n };\n \n+extern struct qat_crypto_gen_dev_ops qat_sym_gen_dev_ops[];\n+extern struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[];\n+\n int\n qat_cryptodev_config(struct rte_cryptodev *dev,\n \t\tstruct rte_cryptodev_config *config);\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex f814bf8f75..83bf55c933 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -13,6 +13,10 @@\n #include \"qat_sym.h\"\n #include \"dev/qat_crypto_pmd_gens.h\"\n \n+uint8_t qat_sym_driver_id;\n+\n+struct qat_crypto_gen_dev_ops qat_sym_gen_dev_ops[QAT_N_GENS];\n+\n static inline void\n set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,\n \t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param,\n@@ -126,7 +130,7 @@ handle_spc_gmac(struct qat_sym_session *ctx, struct rte_crypto_op *op,\n \n int\n qat_sym_build_request(void *in_op, uint8_t *out_msg,\n-\t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen)\n+\t\tvoid *op_cookie, __rte_unused enum qat_device_gen qat_dev_gen)\n {\n \tint ret = 0;\n \tstruct qat_sym_session *ctx = NULL;\n@@ -191,12 +195,6 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {\n-\t\tQAT_DP_LOG(ERR, \"Session alg not supported on this device gen\");\n-\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;\n-\t\treturn -EINVAL;\n-\t}\n-\n \tqat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;\n \trte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));\n \tqat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 8ca475ca8b..3a880096c4 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n- * Copyright(c) 2015-2019 Intel Corporation\n+ * Copyright(c) 2015-2022 Intel Corporation\n  */\n \n #include <openssl/sha.h>\t/* Needed to calculate pre-compute values */\n@@ -486,80 +486,6 @@ qat_sym_session_configure(struct rte_cryptodev *dev,\n \treturn 0;\n }\n \n-static void\n-qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session,\n-\t\tuint8_t hash_flag)\n-{\n-\tstruct icp_qat_fw_comn_req_hdr *header = &session->fw_req.comn_hdr;\n-\tstruct icp_qat_fw_cipher_auth_cd_ctrl_hdr *cd_ctrl =\n-\t\t\t(struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *)\n-\t\t\tsession->fw_req.cd_ctrl.content_desc_ctrl_lw;\n-\n-\t/* Set the Use Extended Protocol Flags bit in LW 1 */\n-\tQAT_FIELD_SET(header->comn_req_flags,\n-\t\t\tQAT_COMN_EXT_FLAGS_USED,\n-\t\t\tQAT_COMN_EXT_FLAGS_BITPOS,\n-\t\t\tQAT_COMN_EXT_FLAGS_MASK);\n-\n-\t/* Set Hash Flags in LW 28 */\n-\tcd_ctrl->hash_flags |= hash_flag;\n-\n-\t/* Set proto flags in LW 1 */\n-\tswitch (session->qat_cipher_alg) {\n-\tcase ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2:\n-\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_SNOW_3G_PROTO);\n-\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n-\t\t\t\theader->serv_specif_flags, 0);\n-\t\tbreak;\n-\tcase ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3:\n-\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n-\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n-\t\t\t\theader->serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_ZUC_3G_PROTO);\n-\t\tbreak;\n-\tdefault:\n-\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n-\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n-\t\t\t\theader->serv_specif_flags, 0);\n-\t\tbreak;\n-\t}\n-}\n-\n-static void\n-qat_sym_session_handle_mixed(const struct rte_cryptodev *dev,\n-\t\tstruct qat_sym_session *session)\n-{\n-\tconst struct qat_cryptodev_private *qat_private =\n-\t\t\tdev->data->dev_private;\n-\tenum qat_device_gen min_dev_gen = (qat_private->internal_capabilities &\n-\t\t\tQAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3;\n-\n-\tif (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&\n-\t\t\tsession->qat_cipher_alg !=\n-\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n-\t\tsession->min_qat_dev_gen = min_dev_gen;\n-\t\tqat_sym_session_set_ext_hash_flags(session,\n-\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);\n-\t} else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&\n-\t\t\tsession->qat_cipher_alg !=\n-\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {\n-\t\tsession->min_qat_dev_gen = min_dev_gen;\n-\t\tqat_sym_session_set_ext_hash_flags(session,\n-\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);\n-\t} else if ((session->aes_cmac ||\n-\t\t\tsession->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n-\t\t\t(session->qat_cipher_alg ==\n-\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n-\t\t\tsession->qat_cipher_alg ==\n-\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n-\t\tsession->min_qat_dev_gen = min_dev_gen;\n-\t\tqat_sym_session_set_ext_hash_flags(session, 0);\n-\t}\n-}\n-\n int\n qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\tstruct rte_crypto_sym_xform *xform, void *session_private)\n@@ -569,7 +495,6 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \tenum qat_device_gen qat_dev_gen = internals->qat_dev->qat_dev_gen;\n \tint ret;\n \tint qat_cmd_id;\n-\tint handle_mixed = 0;\n \n \t/* Verify the session physical address is known */\n \trte_iova_t session_paddr = rte_mempool_virt2iova(session);\n@@ -584,7 +509,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \tsession->cd_paddr = session_paddr +\n \t\t\toffsetof(struct qat_sym_session, cd);\n \n-\tsession->min_qat_dev_gen = QAT_GEN1;\n+\tsession->dev_id = internals->dev_id;\n \tsession->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_NONE;\n \tsession->is_ucs = 0;\n \n@@ -625,7 +550,6 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\t\t\txform, session);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n-\t\t\thandle_mixed = 1;\n \t\t}\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_HASH_CIPHER:\n@@ -643,7 +567,6 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\t\t\txform, session);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n-\t\t\thandle_mixed = 1;\n \t\t}\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:\n@@ -664,12 +587,9 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\treturn -ENOTSUP;\n \t}\n \tqat_sym_session_finalize(session);\n-\tif (handle_mixed) {\n-\t\t/* Special handling of mixed hash+cipher algorithms */\n-\t\tqat_sym_session_handle_mixed(dev, session);\n-\t}\n \n-\treturn 0;\n+\treturn qat_sym_gen_dev_ops[qat_dev_gen].set_session((void *)dev,\n+\t\t\t(void *)session);\n }\n \n static int\n@@ -678,14 +598,13 @@ qat_sym_session_handle_single_pass(struct qat_sym_session *session,\n {\n \tsession->is_single_pass = 1;\n \tsession->is_auth = 1;\n-\tsession->min_qat_dev_gen = QAT_GEN3;\n \tsession->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER;\n \t/* Chacha-Poly is special case that use QAT CTR mode */\n-\tif (aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) {\n+\tif (aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM)\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_AEAD_MODE;\n-\t} else {\n+\telse\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n-\t}\n+\n \tsession->cipher_iv.offset = aead_xform->iv.offset;\n \tsession->cipher_iv.length = aead_xform->iv.length;\n \tsession->aad_len = aead_xform->aad_length;\n@@ -1205,9 +1124,9 @@ static int partial_hash_md5(uint8_t *data_in, uint8_t *data_out)\n \treturn 0;\n }\n \n-static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,\n-\t\t\tuint8_t *data_in,\n-\t\t\tuint8_t *data_out)\n+static int\n+partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,\n+\t\tuint8_t *data_in, uint8_t *data_out)\n {\n \tint digest_size;\n \tuint8_t digest[qat_hash_get_digest_size(\n@@ -1654,7 +1573,6 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t\tcipher_cd_ctrl->cipher_state_sz =\n \t\t\tICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;\n \t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n-\t\tcdesc->min_qat_dev_gen = QAT_GEN2;\n \t} else {\n \t\ttotal_key_size = cipherkeylen;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;\n@@ -2002,7 +1920,6 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tmemcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);\n \t\tcd_extra_size += ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;\n \t\tauth_param->hash_state_sz = ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;\n-\t\tcdesc->min_qat_dev_gen = QAT_GEN2;\n \n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_MD5:\n@@ -2263,8 +2180,6 @@ qat_sec_session_set_docsis_parameters(struct rte_cryptodev *dev,\n \tsession->cd_paddr = session_paddr +\n \t\t\toffsetof(struct qat_sym_session, cd);\n \n-\tsession->min_qat_dev_gen = QAT_GEN1;\n-\n \t/* Get requested QAT command id - should be cipher */\n \tqat_cmd_id = qat_get_cmd_id(xform);\n \tif (qat_cmd_id != ICP_QAT_FW_LA_CMD_CIPHER) {\n@@ -2289,6 +2204,9 @@ qat_security_session_create(void *dev,\n {\n \tvoid *sess_private_data;\n \tstruct rte_cryptodev *cdev = (struct rte_cryptodev *)dev;\n+\tstruct qat_cryptodev_private *internals = cdev->data->dev_private;\n+\tenum qat_device_gen qat_dev_gen = internals->qat_dev->qat_dev_gen;\n+\tstruct qat_sym_session *sym_session = NULL;\n \tint ret;\n \n \tif (conf->action_type != RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL ||\n@@ -2312,8 +2230,11 @@ qat_security_session_create(void *dev,\n \t}\n \n \tset_sec_session_private_data(sess, sess_private_data);\n+\tsym_session = (struct qat_sym_session *)sess_private_data;\n+\tsym_session->dev_id = internals->dev_id;\n \n-\treturn ret;\n+\treturn qat_sym_gen_dev_ops[qat_dev_gen].set_session((void *)cdev,\n+\t\t\tsess_private_data);\n }\n \n int\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex fe875a7fd0..01908abd9e 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -105,7 +105,7 @@ struct qat_sym_session {\n \tuint16_t auth_key_length;\n \tuint16_t digest_length;\n \trte_spinlock_t lock;\t/* protects this struct */\n-\tenum qat_device_gen min_qat_dev_gen;\n+\tuint16_t dev_id;\n \tuint8_t aes_cmac;\n \tuint8_t is_single_pass;\n \tuint8_t is_single_pass_gmac;\n",
    "prefixes": [
        "v9",
        "3/9"
    ]
}