Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/107730/?format=api
{ "id": 107730, "url": "http://patches.dpdk.org/api/patches/107730/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220217110924.419024-12-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220217110924.419024-12-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220217110924.419024-12-tduszynski@marvell.com", "date": "2022-02-17T11:09:24", "name": "[v6,11/11] raw/cnxk_gpio: add option to allow using subset of GPIOs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3d302f178888fe9a47a46bc0e1700e4a532e8a6d", "submitter": { "id": 2215, "url": "http://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220217110924.419024-12-tduszynski@marvell.com/mbox/", "series": [ { "id": 21706, "url": "http://patches.dpdk.org/api/series/21706/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21706", "date": "2022-02-17T11:09:13", "name": "Add cnxk_gpio", "version": 6, "mbox": "http://patches.dpdk.org/series/21706/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/107730/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/107730/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 624E5A00BE;\n\tThu, 17 Feb 2022 12:10:43 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8A56841203;\n\tThu, 17 Feb 2022 12:09:59 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id A2AA141229\n for <dev@dpdk.org>; Thu, 17 Feb 2022 12:09:57 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 21H9HZAV005436;\n Thu, 17 Feb 2022 03:09:56 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e9kktrcmc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 17 Feb 2022 03:09:56 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 17 Feb 2022 03:09:53 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 17 Feb 2022 03:09:53 -0800", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 23CA13F70A8;\n Thu, 17 Feb 2022 03:09:51 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=G28gu3xyi5NxupjM7lD0M2dHPU9Vf7Z2IslpQorN//I=;\n b=QhSUTqzWreH1dBdxNMNbftXpiCruGD+KGrwlgO7ht1n8vEGj9NhKCjolieD0pVlqf5Nj\n u6fJUn11vSqJeYOZkWMFVaH6HbWzj64oJBq0FE9qArxYS+oMc7CywARzKu0mz9p+D/0Y\n V/T/KQnXDu7uKlLv0uDJl1tpTS+wxb8NJhJhh7D/MKinHM7GwwH5NzAU3J/SibDSS+kn\n BycA5ugHKP84YdsYTlammpvUNrFa2rvTeHjLAy75AO+HoHwH2lbkOxiE1nWkzWACZ6Mz\n NK94IFHSnbTIUYrk2F7LImdOFsAOpNoWfSJvGeGIvcf7pUDmHSVh5TLLxlChR7pv/neA VQ==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>, Jakub Palider <jpalider@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>", "CC": "<jerinj@marvell.com>, <thomas@monjalon.net>", "Subject": "[PATCH v6 11/11] raw/cnxk_gpio: add option to allow using subset of\n GPIOs", "Date": "Thu, 17 Feb 2022 12:09:24 +0100", "Message-ID": "<20220217110924.419024-12-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220217110924.419024-1-tduszynski@marvell.com>", "References": "<20220118132424.2573372-1-tduszynski@marvell.com>\n <20220217110924.419024-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "1awGw9AMHk0SZTCmHhnKJ7HJ11EMhZ27", "X-Proofpoint-GUID": "1awGw9AMHk0SZTCmHhnKJ7HJ11EMhZ27", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-02-17_04,2022-02-17_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add PMD parameter that allows one to select only subset of available\nGPIOs.\n\nThis might be useful in cases where some GPIOs are already reserved yet\nstill available for userspace access but particular app should not touch\nthem.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nReviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>\n---\n doc/guides/rawdevs/cnxk_gpio.rst | 5 +\n drivers/raw/cnxk_gpio/cnxk_gpio.c | 173 +++++++++++++++++----\n drivers/raw/cnxk_gpio/cnxk_gpio.h | 2 +\n drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c | 49 +++---\n drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h | 8 +\n 5 files changed, 188 insertions(+), 49 deletions(-)", "diff": "diff --git a/doc/guides/rawdevs/cnxk_gpio.rst b/doc/guides/rawdevs/cnxk_gpio.rst\nindex c03a5b937c..adff535a77 100644\n--- a/doc/guides/rawdevs/cnxk_gpio.rst\n+++ b/doc/guides/rawdevs/cnxk_gpio.rst\n@@ -57,6 +57,11 @@ former returns number GPIOs available in the system irrespective of GPIOs\n being controllable or not. Thus it is user responsibility to pick the proper\n ones. The latter call simply returns queue capacity.\n \n+In order to allow using only subset of available GPIOs `allowlist` PMD param may\n+be used. For example passing `--vdev=cnxk_gpio,gpiochip=448,allowlist=[0,1,2,3]`\n+to EAL will deny using all GPIOs except those specified explicitly in the\n+`allowlist`.\n+\n Respective queue needs to be configured with ``rte_rawdev_queue_setup()``. This\n call barely exports GPIO to userspace.\n \ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.c b/drivers/raw/cnxk_gpio/cnxk_gpio.c\nindex 230016b078..4ff132861d 100644\n--- a/drivers/raw/cnxk_gpio/cnxk_gpio.c\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.c\n@@ -22,9 +22,13 @@\n static const char *const cnxk_gpio_args[] = {\n #define CNXK_GPIO_ARG_GPIOCHIP \"gpiochip\"\n \tCNXK_GPIO_ARG_GPIOCHIP,\n+#define CNXK_GPIO_ARG_ALLOWLIST \"allowlist\"\n+\tCNXK_GPIO_ARG_ALLOWLIST,\n \tNULL\n };\n \n+static char *allowlist;\n+\n static void\n cnxk_gpio_format_name(char *name, size_t len)\n {\n@@ -73,13 +77,23 @@ cnxk_gpio_parse_arg_gpiochip(const char *key __rte_unused, const char *value,\n }\n \n static int\n-cnxk_gpio_parse_args(struct cnxk_gpiochip *gpiochip,\n-\t\t struct rte_devargs *devargs)\n+cnxk_gpio_parse_arg_allowlist(const char *key __rte_unused, const char *value,\n+\t\t\t void *extra_args __rte_unused)\n+{\n+\tallowlist = strdup(value);\n+\tif (!allowlist)\n+\t\treturn -ENOMEM;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_gpio_parse_args(struct cnxk_gpiochip *gpiochip, const char *args)\n {\n \tstruct rte_kvargs *kvlist;\n \tint ret;\n \n-\tkvlist = rte_kvargs_parse(devargs->args, cnxk_gpio_args);\n+\tkvlist = rte_kvargs_parse(args, cnxk_gpio_args);\n \tif (!kvlist)\n \t\treturn 0;\n \n@@ -92,6 +106,14 @@ cnxk_gpio_parse_args(struct cnxk_gpiochip *gpiochip,\n \t\t\tgoto out;\n \t}\n \n+\tret = rte_kvargs_count(kvlist, CNXK_GPIO_ARG_ALLOWLIST);\n+\tif (ret == 1) {\n+\t\tret = rte_kvargs_process(kvlist, CNXK_GPIO_ARG_ALLOWLIST,\n+\t\t\t\t\t cnxk_gpio_parse_arg_allowlist, NULL);\n+\t\tif (ret)\n+\t\t\tgoto out;\n+\t}\n+\n \tret = 0;\n out:\n \trte_kvargs_free(kvlist);\n@@ -99,6 +121,60 @@ cnxk_gpio_parse_args(struct cnxk_gpiochip *gpiochip,\n \treturn ret;\n }\n \n+static int\n+cnxk_gpio_parse_allowlist(struct cnxk_gpiochip *gpiochip)\n+{\n+\tint i, ret, val, queue = 0;\n+\tchar *token;\n+\tint *list;\n+\n+\tlist = rte_calloc(NULL, gpiochip->num_gpios, sizeof(*list), 0);\n+\tif (!list)\n+\t\treturn -ENOMEM;\n+\n+\t/* replace brackets with something meaningless for strtol() */\n+\tallowlist[0] = ' ';\n+\tallowlist[strlen(allowlist) - 1] = ' ';\n+\n+\t/* quiesce -Wcast-qual */\n+\ttoken = strtok((char *)(uintptr_t)allowlist, \",\");\n+\tdo {\n+\t\terrno = 0;\n+\t\tval = strtol(token, NULL, 10);\n+\t\tif (errno) {\n+\t\t\tRTE_LOG(ERR, PMD, \"failed to parse %s\\n\", token);\n+\t\t\tret = -errno;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (val < 0 || val >= gpiochip->num_gpios) {\n+\t\t\tRTE_LOG(ERR, PMD, \"gpio%d out of 0-%d range\\n\", val,\n+\t\t\t\tgpiochip->num_gpios - 1);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tfor (i = 0; i < queue; i++) {\n+\t\t\tif (list[i] != val)\n+\t\t\t\tcontinue;\n+\n+\t\t\tRTE_LOG(WARNING, PMD, \"gpio%d already allowed\\n\", val);\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (i == queue)\n+\t\t\tlist[queue++] = val;\n+\t} while ((token = strtok(NULL, \",\")));\n+\n+\tgpiochip->allowlist = list;\n+\tgpiochip->num_queues = queue;\n+\n+\treturn 0;\n+out:\n+\trte_free(list);\n+\n+\treturn ret;\n+}\n+\n static int\n cnxk_gpio_read_attr(char *attr, char *val)\n {\n@@ -175,13 +251,24 @@ cnxk_gpio_write_attr_int(const char *attr, int val)\n \treturn cnxk_gpio_write_attr(attr, buf);\n }\n \n+static bool\n+cnxk_gpio_queue_valid(struct cnxk_gpiochip *gpiochip, uint16_t queue)\n+{\n+\treturn queue < gpiochip->num_queues;\n+}\n+\n+static int\n+cnxk_queue_to_gpio(struct cnxk_gpiochip *gpiochip, uint16_t queue)\n+{\n+\treturn gpiochip->allowlist ? gpiochip->allowlist[queue] : queue;\n+}\n+\n static struct cnxk_gpio *\n cnxk_gpio_lookup(struct cnxk_gpiochip *gpiochip, uint16_t queue)\n {\n-\tif (queue >= gpiochip->num_gpios)\n-\t\treturn NULL;\n+\tint gpio = cnxk_queue_to_gpio(gpiochip, queue);\n \n-\treturn gpiochip->gpios[queue];\n+\treturn gpiochip->gpios[gpio];\n }\n \n static int\n@@ -191,11 +278,14 @@ cnxk_gpio_queue_setup(struct rte_rawdev *dev, uint16_t queue_id,\n \tstruct cnxk_gpiochip *gpiochip = dev->dev_private;\n \tchar buf[CNXK_GPIO_BUFSZ];\n \tstruct cnxk_gpio *gpio;\n-\tint ret;\n+\tint num, ret;\n \n \tRTE_SET_USED(queue_conf);\n \tRTE_SET_USED(queue_conf_size);\n \n+\tif (!cnxk_gpio_queue_valid(gpiochip, queue_id))\n+\t\treturn -EINVAL;\n+\n \tgpio = cnxk_gpio_lookup(gpiochip, queue_id);\n \tif (gpio)\n \t\treturn -EEXIST;\n@@ -203,7 +293,9 @@ cnxk_gpio_queue_setup(struct rte_rawdev *dev, uint16_t queue_id,\n \tgpio = rte_zmalloc(NULL, sizeof(*gpio), 0);\n \tif (!gpio)\n \t\treturn -ENOMEM;\n-\tgpio->num = queue_id + gpiochip->base;\n+\n+\tnum = cnxk_queue_to_gpio(gpiochip, queue_id);\n+\tgpio->num = num + gpiochip->base;\n \tgpio->gpiochip = gpiochip;\n \n \tsnprintf(buf, sizeof(buf), \"%s/export\", CNXK_GPIO_CLASS_PATH);\n@@ -213,7 +305,7 @@ cnxk_gpio_queue_setup(struct rte_rawdev *dev, uint16_t queue_id,\n \t\treturn ret;\n \t}\n \n-\tgpiochip->gpios[queue_id] = gpio;\n+\tgpiochip->gpios[num] = gpio;\n \n \treturn 0;\n }\n@@ -224,18 +316,22 @@ cnxk_gpio_queue_release(struct rte_rawdev *dev, uint16_t queue_id)\n \tstruct cnxk_gpiochip *gpiochip = dev->dev_private;\n \tchar buf[CNXK_GPIO_BUFSZ];\n \tstruct cnxk_gpio *gpio;\n-\tint ret;\n+\tint num, ret;\n+\n+\tif (!cnxk_gpio_queue_valid(gpiochip, queue_id))\n+\t\treturn -EINVAL;\n \n \tgpio = cnxk_gpio_lookup(gpiochip, queue_id);\n \tif (!gpio)\n \t\treturn -ENODEV;\n \n \tsnprintf(buf, sizeof(buf), \"%s/unexport\", CNXK_GPIO_CLASS_PATH);\n-\tret = cnxk_gpio_write_attr_int(buf, gpiochip->base + queue_id);\n+\tret = cnxk_gpio_write_attr_int(buf, gpio->num);\n \tif (ret)\n \t\treturn ret;\n \n-\tgpiochip->gpios[queue_id] = NULL;\n+\tnum = cnxk_queue_to_gpio(gpiochip, queue_id);\n+\tgpiochip->gpios[num] = NULL;\n \trte_free(gpio);\n \n \treturn 0;\n@@ -245,16 +341,17 @@ static int\n cnxk_gpio_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,\n \t\t\t rte_rawdev_obj_t queue_conf, size_t queue_conf_size)\n {\n-\tunsigned int *conf;\n+\tstruct cnxk_gpiochip *gpiochip = dev->dev_private;\n+\tstruct cnxk_gpio_queue_conf *conf = queue_conf;\n \n-\tRTE_SET_USED(dev);\n-\tRTE_SET_USED(queue_id);\n+\tif (!cnxk_gpio_queue_valid(gpiochip, queue_id))\n+\t\treturn -EINVAL;\n \n \tif (queue_conf_size != sizeof(*conf))\n \t\treturn -EINVAL;\n \n-\tconf = (unsigned int *)queue_conf;\n-\t*conf = 1;\n+\tconf->size = 1;\n+\tconf->gpio = cnxk_queue_to_gpio(gpiochip, queue_id);\n \n \treturn 0;\n }\n@@ -264,7 +361,7 @@ cnxk_gpio_queue_count(struct rte_rawdev *dev)\n {\n \tstruct cnxk_gpiochip *gpiochip = dev->dev_private;\n \n-\treturn gpiochip->num_gpios;\n+\treturn gpiochip->num_queues;\n }\n \n static const struct {\n@@ -463,21 +560,27 @@ cnxk_gpio_process_buf(struct cnxk_gpio *gpio, struct rte_rawdev_buf *rbuf)\n \treturn ret;\n }\n \n+static bool\n+cnxk_gpio_valid(struct cnxk_gpiochip *gpiochip, int gpio)\n+{\n+\treturn gpio < gpiochip->num_gpios && gpiochip->gpios[gpio];\n+}\n+\n static int\n cnxk_gpio_enqueue_bufs(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,\n \t\t unsigned int count, rte_rawdev_obj_t context)\n {\n \tstruct cnxk_gpiochip *gpiochip = dev->dev_private;\n-\tunsigned int queue = (size_t)context;\n+\tunsigned int gpio_num = (size_t)context;\n \tstruct cnxk_gpio *gpio;\n \tint ret;\n \n \tif (count == 0)\n \t\treturn 0;\n \n-\tgpio = cnxk_gpio_lookup(gpiochip, queue);\n-\tif (!gpio)\n-\t\treturn -ENODEV;\n+\tif (!cnxk_gpio_valid(gpiochip, gpio_num))\n+\t\treturn -EINVAL;\n+\tgpio = gpiochip->gpios[gpio_num];\n \n \tret = cnxk_gpio_process_buf(gpio, buffers[0]);\n \tif (ret)\n@@ -491,15 +594,15 @@ cnxk_gpio_dequeue_bufs(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,\n \t\t unsigned int count, rte_rawdev_obj_t context)\n {\n \tstruct cnxk_gpiochip *gpiochip = dev->dev_private;\n-\tunsigned int queue = (size_t)context;\n+\tunsigned int gpio_num = (size_t)context;\n \tstruct cnxk_gpio *gpio;\n \n \tif (count == 0)\n \t\treturn 0;\n \n-\tgpio = cnxk_gpio_lookup(gpiochip, queue);\n-\tif (!gpio)\n-\t\treturn -ENODEV;\n+\tif (!cnxk_gpio_valid(gpiochip, gpio_num))\n+\t\treturn -EINVAL;\n+\tgpio = gpiochip->gpios[gpio_num];\n \n \tif (gpio->rsp) {\n \t\tbuffers[0]->buf_addr = gpio->rsp;\n@@ -558,7 +661,7 @@ cnxk_gpio_probe(struct rte_vdev_device *dev)\n \tcnxk_gpio_set_defaults(gpiochip);\n \n \t/* defaults may be overwritten by this call */\n-\tret = cnxk_gpio_parse_args(gpiochip, dev->device.devargs);\n+\tret = cnxk_gpio_parse_args(gpiochip, rte_vdev_device_args(dev));\n \tif (ret)\n \t\tgoto out;\n \n@@ -583,6 +686,15 @@ cnxk_gpio_probe(struct rte_vdev_device *dev)\n \t\tRTE_LOG(ERR, PMD, \"failed to read %s\", buf);\n \t\tgoto out;\n \t}\n+\tgpiochip->num_queues = gpiochip->num_gpios;\n+\n+\tif (allowlist) {\n+\t\tret = cnxk_gpio_parse_allowlist(gpiochip);\n+\t\tfree(allowlist);\n+\t\tallowlist = NULL;\n+\t\tif (ret)\n+\t\t\tgoto out;\n+\t}\n \n \tgpiochip->gpios = rte_calloc(NULL, gpiochip->num_gpios,\n \t\t\t\t sizeof(struct cnxk_gpio *), 0);\n@@ -594,6 +706,8 @@ cnxk_gpio_probe(struct rte_vdev_device *dev)\n \n \treturn 0;\n out:\n+\tfree(allowlist);\n+\trte_free(gpiochip->allowlist);\n \trte_rawdev_pmd_release(rawdev);\n \n \treturn ret;\n@@ -630,6 +744,7 @@ cnxk_gpio_remove(struct rte_vdev_device *dev)\n \t\tcnxk_gpio_queue_release(rawdev, gpio->num);\n \t}\n \n+\trte_free(gpiochip->allowlist);\n \trte_free(gpiochip->gpios);\n \tcnxk_gpio_irq_fini();\n \trte_rawdev_pmd_release(rawdev);\n@@ -643,4 +758,6 @@ static struct rte_vdev_driver cnxk_gpio_drv = {\n };\n \n RTE_PMD_REGISTER_VDEV(cnxk_gpio, cnxk_gpio_drv);\n-RTE_PMD_REGISTER_PARAM_STRING(cnxk_gpio, \"gpiochip=<int>\");\n+RTE_PMD_REGISTER_PARAM_STRING(cnxk_gpio,\n+\t\t\"gpiochip=<int> \"\n+\t\t\"allowlist=<list>\");\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.h b/drivers/raw/cnxk_gpio/cnxk_gpio.h\nindex 1b31b5a486..e62f78a760 100644\n--- a/drivers/raw/cnxk_gpio/cnxk_gpio.h\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.h\n@@ -20,7 +20,9 @@ struct cnxk_gpiochip {\n \tint num;\n \tint base;\n \tint num_gpios;\n+\tint num_queues;\n \tstruct cnxk_gpio **gpios;\n+\tint *allowlist;\n };\n \n int cnxk_gpio_selftest(uint16_t dev_id);\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c b/drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c\nindex 6502902f86..7fccc48f30 100644\n--- a/drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c\n@@ -302,12 +302,13 @@ cnxk_gpio_test_output(uint16_t dev_id, int base, int gpio)\n int\n cnxk_gpio_selftest(uint16_t dev_id)\n {\n+\tstruct cnxk_gpio_queue_conf conf;\n \tstruct cnxk_gpiochip *gpiochip;\n-\tunsigned int queues, i, size;\n \tchar buf[CNXK_GPIO_BUFSZ];\n \tstruct rte_rawdev *rawdev;\n+\tunsigned int queues, i;\n \tstruct cnxk_gpio *gpio;\n-\tint ret;\n+\tint ret, ret2;\n \n \trawdev = rte_rawdev_pmd_get_named_dev(\"cnxk_gpio\");\n \tgpiochip = rawdev->dev_private;\n@@ -325,62 +326,68 @@ cnxk_gpio_selftest(uint16_t dev_id)\n \t\treturn -errno;\n \n \tfor (i = 0; i < queues; i++) {\n-\t\tRTE_LOG(INFO, PMD, \"testing queue %d (gpio%d)\\n\", i,\n-\t\t\tgpiochip->base + i);\n-\n-\t\tret = rte_rawdev_queue_conf_get(dev_id, i, &size, sizeof(size));\n+\t\tret = rte_rawdev_queue_conf_get(dev_id, i, &conf, sizeof(conf));\n \t\tif (ret) {\n \t\t\tRTE_LOG(ERR, PMD,\n \t\t\t\t\"failed to read queue configuration (%d)\\n\",\n \t\t\t\tret);\n-\t\t\tcontinue;\n+\t\t\tgoto out;\n \t\t}\n \n-\t\tif (size != 1) {\n+\t\tRTE_LOG(INFO, PMD, \"testing queue%d (gpio%d)\\n\", i, conf.gpio);\n+\n+\t\tif (conf.size != 1) {\n \t\t\tRTE_LOG(ERR, PMD, \"wrong queue size received\\n\");\n-\t\t\tcontinue;\n+\t\t\tret = -EIO;\n+\t\t\tgoto out;\n \t\t}\n \n \t\tret = rte_rawdev_queue_setup(dev_id, i, NULL, 0);\n \t\tif (ret) {\n \t\t\tRTE_LOG(ERR, PMD, \"failed to setup queue (%d)\\n\", ret);\n-\t\t\tcontinue;\n+\t\t\tgoto out;\n \t\t}\n \n-\t\tgpio = gpiochip->gpios[i];\n+\t\tgpio = gpiochip->gpios[conf.gpio];\n \t\tsnprintf(buf, sizeof(buf), CNXK_GPIO_PATH_FMT, gpio->num);\n \t\tif (!cnxk_gpio_attr_exists(buf)) {\n \t\t\tRTE_LOG(ERR, PMD, \"%s does not exist\\n\", buf);\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tret = cnxk_gpio_test_input(dev_id, gpiochip->base, i);\n-\t\tif (ret)\n+\t\t\tret = -ENOENT;\n \t\t\tgoto release;\n+\t\t}\n \n-\t\tret = cnxk_gpio_test_irq(dev_id, i);\n+\t\tret = cnxk_gpio_test_input(dev_id, gpiochip->base, conf.gpio);\n \t\tif (ret)\n \t\t\tgoto release;\n \n-\t\tret = cnxk_gpio_test_output(dev_id, gpiochip->base, i);\n+\t\tret = cnxk_gpio_test_irq(dev_id, conf.gpio);\n \t\tif (ret)\n \t\t\tgoto release;\n \n+\t\tret = cnxk_gpio_test_output(dev_id, gpiochip->base, conf.gpio);\n release:\n+\t\tret2 = ret;\n \t\tret = rte_rawdev_queue_release(dev_id, i);\n \t\tif (ret) {\n \t\t\tRTE_LOG(ERR, PMD, \"failed to release queue (%d)\\n\",\n \t\t\t\tret);\n-\t\t\tcontinue;\n+\t\t\tbreak;\n \t\t}\n \n \t\tif (cnxk_gpio_attr_exists(buf)) {\n \t\t\tRTE_LOG(ERR, PMD, \"%s still exists\\n\", buf);\n-\t\t\tcontinue;\n+\t\t\tret = -EIO;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (ret2) {\n+\t\t\tret = ret2;\n+\t\t\tbreak;\n \t\t}\n \t}\n \n+out:\n \tclose(fd);\n \n-\treturn 0;\n+\treturn ret;\n }\ndiff --git a/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h b/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\nindex e3096dc14f..80a37be9c7 100644\n--- a/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\n+++ b/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\n@@ -22,6 +22,14 @@\n extern \"C\" {\n #endif\n \n+/* Queue default configuration */\n+struct cnxk_gpio_queue_conf {\n+\t/** Queue size */\n+\tint size;\n+\t/** GPIO number as seen by hardware */\n+\tint gpio;\n+};\n+\n /** Available message types */\n enum cnxk_gpio_msg_type {\n \t/** Type used to set output value */\n", "prefixes": [ "v6", "11/11" ] }