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GET /api/patches/107445/?format=api
{ "id": 107445, "url": "http://patches.dpdk.org/api/patches/107445/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220214101001.498992-1-skori@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220214101001.498992-1-skori@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220214101001.498992-1-skori@marvell.com", "date": "2022-02-14T10:10:00", "name": "[v9,1/2] common/cnxk: support priority flow ctrl config API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dda0446de51704ccb31a95b597b4beb5ce8c520c", "submitter": { "id": 1318, "url": "http://patches.dpdk.org/api/people/1318/?format=api", "name": "Sunil Kumar Kori", "email": "skori@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220214101001.498992-1-skori@marvell.com/mbox/", "series": [ { "id": 21655, "url": "http://patches.dpdk.org/api/series/21655/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21655", "date": "2022-02-14T10:10:01", "name": "[v9,1/2] common/cnxk: support priority flow ctrl config API", "version": 9, "mbox": "http://patches.dpdk.org/series/21655/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/107445/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/107445/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DC6A9A00C4;\n\tMon, 14 Feb 2022 11:10:18 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3838E4114A;\n\tMon, 14 Feb 2022 11:10:15 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 33F26410F6\n for <dev@dpdk.org>; Mon, 14 Feb 2022 11:10:12 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 21E9fEl3008905;\n Mon, 14 Feb 2022 02:10:09 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e6d9qwphh-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 14 Feb 2022 02:10:09 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 14 Feb 2022 02:10:07 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 14 Feb 2022 02:10:07 -0800", "from localhost.localdomain (unknown [10.28.34.25])\n by maili.marvell.com (Postfix) with ESMTP id E1DBF3F7085;\n Mon, 14 Feb 2022 02:10:04 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=AvXTRo+6hod5ffgFhlDFW6k/MFWKyZvH3GnhSq2s/+8=;\n b=N6TQCpIsuLVOURI1IU33B4Tjq6LeOIpKdENCcf/MyImXXyKHarWWHFChfj/OIGTo72pk\n tocxW1W2+SIzLaLaaHu245vLPqVWuhOyIRNWzeyGzabiSeUuwh8pPiiH6ewEK+UtmgK0\n DtIWRgVFgW5ymXJiknk3lC/iHCFGWrf9aH3M9mHmNQMD04bmSyCTL4YePLKEqT4Xnw6v\n mJdR0idDwaN+kZvP0yiRLxk+rR3szivOHvkNfrCt/iOXkt8jG/Qw+zRuLfZl9DUsDEEe\n 3zBrQ9m1cvYZ+f2MsehnD33gfCTQW+WUgKY72bzYPDpNoqIinsI1VVTwTRcxCzczuOMV Ug==", "From": "<skori@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v9 1/2] common/cnxk: support priority flow ctrl config API", "Date": "Mon, 14 Feb 2022 15:40:00 +0530", "Message-ID": "<20220214101001.498992-1-skori@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220214090247.493995-2-skori@marvell.com>", "References": "<20220214090247.493995-2-skori@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "7FN-shVFvrWIiBABYThJE9N4V0pJII-l", "X-Proofpoint-ORIG-GUID": "7FN-shVFvrWIiBABYThJE9N4V0pJII-l", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-02-14_02,2022-02-14_02,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nCNXK platforms support priority flow control(802.1qbb) to pause\nrespective traffic per class on that link.\n\nPatch adds RoC interface to configure priority flow control on MAC\nblock i.e. CGX on cn9k and RPM on cn10k.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\nv1..v2:\n - fix RoC API naming convention.\n\nv2..v3:\n - fix pause quanta configuration for cn10k.\n - remove unnecessary code\n\nv3..v4:\n - fix PFC configuration with other type of TM tree\n i.e. default, user and rate limit tree.\n\nv4..v5:\n - rebase on top of tree\n - fix review comments\n - fix initialization error for LBK devices \n\nv5..v6:\n - fix review comments\n\nv6..v7:\n - no change\n\nv7..v8:\n - rebase on top of 22.03-rc1\n\nv8..v9:\n - no change\n\n drivers/common/cnxk/roc_mbox.h | 19 ++-\n drivers/common/cnxk/roc_nix.h | 21 ++++\n drivers/common/cnxk/roc_nix_fc.c | 95 +++++++++++++--\n drivers/common/cnxk/roc_nix_priv.h | 6 +-\n drivers/common/cnxk/roc_nix_tm.c | 171 ++++++++++++++++++++++++++-\n drivers/common/cnxk/roc_nix_tm_ops.c | 14 ++-\n drivers/common/cnxk/version.map | 4 +\n 7 files changed, 310 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex 8967858914..b608f58357 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -95,6 +95,8 @@ struct mbox_msghdr {\n \t msg_rsp) \\\n \tM(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \\\n \tM(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \\\n+\tM(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \\\n+\t cgx_pfc_rsp) \\\n \t/* NPA mbox IDs (range 0x400 - 0x5FF) */ \\\n \tM(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \\\n \t npa_lf_alloc_rsp) \\\n@@ -551,6 +553,19 @@ struct cgx_pause_frm_cfg {\n \tuint8_t __io tx_pause;\n };\n \n+struct cgx_pfc_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rx_pause;\n+\tuint8_t __io tx_pause;\n+\tuint16_t __io pfc_en; /* bitmap indicating enabled traffic classes */\n+};\n+\n+struct cgx_pfc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rx_pause;\n+\tuint8_t __io tx_pause;\n+};\n+\n struct sfp_eeprom_s {\n #define SFP_EEPROM_SIZE 256\n \tuint16_t __io sff_id;\n@@ -1125,7 +1140,9 @@ struct nix_bp_cfg_req {\n /* PF can be mapped to either CGX or LBK interface,\n * so maximum 64 channels are possible.\n */\n-#define NIX_MAX_CHAN 64\n+#define NIX_MAX_CHAN\t 64\n+#define NIX_CGX_MAX_CHAN 16\n+#define NIX_LBK_MAX_CHAN 1\n struct nix_bp_cfg_rsp {\n \tstruct mbox_msghdr hdr;\n \t/* Channel and bpid mapping */\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 755212c8f9..680a34cdcd 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -165,16 +165,27 @@ struct roc_nix_fc_cfg {\n \n \t\tstruct {\n \t\t\tuint32_t rq;\n+\t\t\tuint16_t tc;\n \t\t\tuint16_t cq_drop;\n \t\t\tbool enable;\n \t\t} cq_cfg;\n \n \t\tstruct {\n+\t\t\tuint32_t sq;\n+\t\t\tuint16_t tc;\n \t\t\tbool enable;\n \t\t} tm_cfg;\n \t};\n };\n \n+struct roc_nix_pfc_cfg {\n+\tenum roc_nix_fc_mode mode;\n+\t/* For SET, tc must be [0, 15].\n+\t * For GET, TC will represent bitmap\n+\t */\n+\tuint16_t tc;\n+};\n+\n struct roc_nix_eeprom_info {\n #define ROC_NIX_EEPROM_SIZE 256\n \tuint16_t sff_id;\n@@ -478,6 +489,7 @@ void __roc_api roc_nix_unregister_cq_irqs(struct roc_nix *roc_nix);\n enum roc_nix_tm_tree {\n \tROC_NIX_TM_DEFAULT = 0,\n \tROC_NIX_TM_RLIMIT,\n+\tROC_NIX_TM_PFC,\n \tROC_NIX_TM_USER,\n \tROC_NIX_TM_TREE_MAX,\n };\n@@ -624,6 +636,7 @@ roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node,\n int __roc_api roc_nix_tm_lvl_cnt_get(struct roc_nix *roc_nix);\n int __roc_api roc_nix_tm_lvl_have_link_access(struct roc_nix *roc_nix, int lvl);\n int __roc_api roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_tm_pfc_prepare_tree(struct roc_nix *roc_nix);\n bool __roc_api roc_nix_tm_is_user_hierarchy_enabled(struct roc_nix *nix);\n int __roc_api roc_nix_tm_tree_type_get(struct roc_nix *nix);\n \n@@ -739,6 +752,14 @@ int __roc_api roc_nix_fc_config_get(struct roc_nix *roc_nix,\n int __roc_api roc_nix_fc_mode_set(struct roc_nix *roc_nix,\n \t\t\t\t enum roc_nix_fc_mode mode);\n \n+int __roc_api roc_nix_pfc_mode_set(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_pfc_cfg *pfc_cfg);\n+\n+int __roc_api roc_nix_pfc_mode_get(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_pfc_cfg *pfc_cfg);\n+\n+uint16_t __roc_api roc_nix_chan_count_get(struct roc_nix *roc_nix);\n+\n enum roc_nix_fc_mode __roc_api roc_nix_fc_mode_get(struct roc_nix *roc_nix);\n \n void __roc_api rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id,\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex d31137188e..8e31443b8f 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -36,7 +36,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \tstruct mbox *mbox = get_mbox(roc_nix);\n \tstruct nix_bp_cfg_req *req;\n \tstruct nix_bp_cfg_rsp *rsp;\n-\tint rc = -ENOSPC;\n+\tint rc = -ENOSPC, i;\n \n \tif (roc_nix_is_sdp(roc_nix))\n \t\treturn 0;\n@@ -45,22 +45,28 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \t\treq = mbox_alloc_msg_nix_bp_enable(mbox);\n \t\tif (req == NULL)\n \t\t\treturn rc;\n+\n \t\treq->chan_base = 0;\n-\t\treq->chan_cnt = 1;\n-\t\treq->bpid_per_chan = 0;\n+\t\tif (roc_nix_is_lbk(roc_nix))\n+\t\t\treq->chan_cnt = NIX_LBK_MAX_CHAN;\n+\t\telse\n+\t\t\treq->chan_cnt = NIX_CGX_MAX_CHAN;\n+\n+\t\treq->bpid_per_chan = true;\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n \t\tif (rc || (req->chan_cnt != rsp->chan_cnt))\n \t\t\tgoto exit;\n \n-\t\tnix->bpid[0] = rsp->chan_bpid[0];\n \t\tnix->chan_cnt = rsp->chan_cnt;\n+\t\tfor (i = 0; i < rsp->chan_cnt; i++)\n+\t\t\tnix->bpid[i] = rsp->chan_bpid[i] & 0x1FF;\n \t} else {\n \t\treq = mbox_alloc_msg_nix_bp_disable(mbox);\n \t\tif (req == NULL)\n \t\t\treturn rc;\n \t\treq->chan_base = 0;\n-\t\treq->chan_cnt = 1;\n+\t\treq->chan_cnt = nix->chan_cnt;\n \n \t\trc = mbox_process(mbox);\n \t\tif (rc)\n@@ -161,7 +167,7 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n \n \t\tif (fc_cfg->cq_cfg.enable) {\n-\t\t\taq->cq.bpid = nix->bpid[0];\n+\t\t\taq->cq.bpid = nix->bpid[fc_cfg->cq_cfg.tc];\n \t\t\taq->cq_mask.bpid = ~(aq->cq_mask.bpid);\n \t\t\taq->cq.bp = fc_cfg->cq_cfg.cq_drop;\n \t\t\taq->cq_mask.bp = ~(aq->cq_mask.bp);\n@@ -181,7 +187,7 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n \n \t\tif (fc_cfg->cq_cfg.enable) {\n-\t\t\taq->cq.bpid = nix->bpid[0];\n+\t\t\taq->cq.bpid = nix->bpid[fc_cfg->cq_cfg.tc];\n \t\t\taq->cq_mask.bpid = ~(aq->cq_mask.bpid);\n \t\t\taq->cq.bp = fc_cfg->cq_cfg.cq_drop;\n \t\t\taq->cq_mask.bp = ~(aq->cq_mask.bp);\n@@ -222,7 +228,9 @@ roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\treturn nix_fc_rxchan_bpid_set(roc_nix,\n \t\t\t\t\t fc_cfg->rxchan_cfg.enable);\n \telse if (fc_cfg->type == ROC_NIX_FC_TM_CFG)\n-\t\treturn nix_tm_bp_config_set(roc_nix, fc_cfg->tm_cfg.enable);\n+\t\treturn nix_tm_bp_config_set(roc_nix, fc_cfg->tm_cfg.sq,\n+\t\t\t\t\t fc_cfg->tm_cfg.tc,\n+\t\t\t\t\t fc_cfg->tm_cfg.enable);\n \n \treturn -EINVAL;\n }\n@@ -403,3 +411,74 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \n \tmbox_process(mbox);\n }\n+\n+int\n+roc_nix_pfc_mode_set(struct roc_nix *roc_nix, struct roc_nix_pfc_cfg *pfc_cfg)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tuint8_t tx_pause, rx_pause;\n+\tstruct cgx_pfc_cfg *req;\n+\tstruct cgx_pfc_rsp *rsp;\n+\tint rc = -ENOSPC;\n+\n+\tif (roc_nix_is_lbk(roc_nix))\n+\t\treturn NIX_ERR_OP_NOTSUP;\n+\n+\trx_pause = (pfc_cfg->mode == ROC_NIX_FC_FULL) ||\n+\t\t (pfc_cfg->mode == ROC_NIX_FC_RX);\n+\ttx_pause = (pfc_cfg->mode == ROC_NIX_FC_FULL) ||\n+\t\t (pfc_cfg->mode == ROC_NIX_FC_TX);\n+\n+\treq = mbox_alloc_msg_cgx_prio_flow_ctrl_cfg(mbox);\n+\tif (req == NULL)\n+\t\tgoto exit;\n+\n+\treq->pfc_en = pfc_cfg->tc;\n+\treq->rx_pause = rx_pause;\n+\treq->tx_pause = tx_pause;\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tnix->rx_pause = rsp->rx_pause;\n+\tnix->tx_pause = rsp->tx_pause;\n+\tif (rsp->tx_pause)\n+\t\tnix->cev |= BIT(pfc_cfg->tc);\n+\telse\n+\t\tnix->cev &= ~BIT(pfc_cfg->tc);\n+\n+exit:\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_pfc_mode_get(struct roc_nix *roc_nix, struct roc_nix_pfc_cfg *pfc_cfg)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (roc_nix_is_lbk(roc_nix))\n+\t\treturn NIX_ERR_OP_NOTSUP;\n+\n+\tpfc_cfg->tc = nix->cev;\n+\n+\tif (nix->rx_pause && nix->tx_pause)\n+\t\tpfc_cfg->mode = ROC_NIX_FC_FULL;\n+\telse if (nix->rx_pause)\n+\t\tpfc_cfg->mode = ROC_NIX_FC_RX;\n+\telse if (nix->tx_pause)\n+\t\tpfc_cfg->mode = ROC_NIX_FC_TX;\n+\telse\n+\t\tpfc_cfg->mode = ROC_NIX_FC_NONE;\n+\n+\treturn 0;\n+}\n+\n+uint16_t\n+roc_nix_chan_count_get(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->chan_cnt;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex deb2a6ba11..f3889424c4 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -33,6 +33,7 @@ struct nix_qint {\n /* Traffic Manager */\n #define NIX_TM_MAX_HW_TXSCHQ 512\n #define NIX_TM_HW_ID_INVALID UINT32_MAX\n+#define NIX_TM_CHAN_INVALID UINT16_MAX\n \n /* TM flags */\n #define NIX_TM_HIERARCHY_ENA BIT_ULL(0)\n@@ -56,6 +57,7 @@ struct nix_tm_node {\n \tuint32_t priority;\n \tuint32_t weight;\n \tuint16_t lvl;\n+\tuint16_t rel_chan;\n \tuint32_t parent_id;\n \tuint32_t shaper_profile_id;\n \tvoid (*free_fn)(void *node);\n@@ -139,6 +141,7 @@ struct nix {\n \tuint16_t msixoff;\n \tuint8_t rx_pause;\n \tuint8_t tx_pause;\n+\tuint16_t cev;\n \tuint64_t rx_cfg;\n \tstruct dev dev;\n \tuint16_t cints;\n@@ -376,7 +379,8 @@ int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \t bool ena);\n int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable);\n int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled);\n-int nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable);\n+int nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n+\t\t\t bool enable);\n void nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval);\n \n /*\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex a0448bec61..670cf66db4 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -121,7 +121,7 @@ nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree)\n \t\t\tif (is_pf_or_lbk && !skip_bp &&\n \t\t\t node->hw_lvl == nix->tm_link_cfg_lvl) {\n \t\t\t\tnode->bp_capa = 1;\n-\t\t\t\tskip_bp = true;\n+\t\t\t\tskip_bp = false;\n \t\t\t}\n \n \t\t\trc = nix_tm_node_reg_conf(nix, node);\n@@ -317,21 +317,38 @@ nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node)\n }\n \n int\n-nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable)\n+nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n+\t\t bool enable)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tenum roc_nix_tm_tree tree = nix->tm_tree;\n \tstruct mbox *mbox = (&nix->dev)->mbox;\n \tstruct nix_txschq_config *req = NULL;\n \tstruct nix_tm_node_list *list;\n+\tstruct nix_tm_node *sq_node;\n+\tstruct nix_tm_node *parent;\n \tstruct nix_tm_node *node;\n \tuint8_t k = 0;\n \tuint16_t link;\n \tint rc = 0;\n \n+\tsq_node = nix_tm_node_search(nix, sq, nix->tm_tree);\n+\tparent = sq_node->parent;\n+\twhile (parent) {\n+\t\tif (parent->lvl == ROC_TM_LVL_SCH2)\n+\t\t\tbreak;\n+\n+\t\tparent = parent->parent;\n+\t}\n+\n \tlist = nix_tm_node_list(nix, tree);\n \tlink = nix->tx_link;\n \n+\tif (parent->rel_chan != NIX_TM_CHAN_INVALID && parent->rel_chan != tc) {\n+\t\trc = -EINVAL;\n+\t\tgoto err;\n+\t}\n+\n \tTAILQ_FOREACH(node, list, node) {\n \t\tif (node->hw_lvl != nix->tm_link_cfg_lvl)\n \t\t\tcontinue;\n@@ -339,6 +356,9 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable)\n \t\tif (!(node->flags & NIX_TM_NODE_HWRES) || !node->bp_capa)\n \t\t\tcontinue;\n \n+\t\tif (node->hw_id != parent->hw_id)\n+\t\t\tcontinue;\n+\n \t\tif (!req) {\n \t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n \t\t\treq->lvl = nix->tm_link_cfg_lvl;\n@@ -346,8 +366,9 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable)\n \t\t}\n \n \t\treq->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(node->hw_id, link);\n-\t\treq->regval[k] = enable ? BIT_ULL(13) : 0;\n-\t\treq->regval_mask[k] = ~BIT_ULL(13);\n+\t\treq->regval[k] = enable ? tc : 0;\n+\t\treq->regval[k] |= enable ? BIT_ULL(13) : 0;\n+\t\treq->regval_mask[k] = ~(BIT_ULL(13) | GENMASK_ULL(7, 0));\n \t\tk++;\n \n \t\tif (k >= MAX_REGS_PER_MBOX_MSG) {\n@@ -366,6 +387,7 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable)\n \t\t\tgoto err;\n \t}\n \n+\tparent->rel_chan = enable ? tc : NIX_TM_CHAN_INVALID;\n \treturn 0;\n err:\n \tplt_err(\"Failed to %s bp on link %u, rc=%d(%s)\",\n@@ -602,7 +624,7 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \t}\n \n \t/* Disable backpressure */\n-\trc = nix_tm_bp_config_set(roc_nix, false);\n+\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false);\n \tif (rc) {\n \t\tplt_err(\"Failed to disable backpressure for flush, rc=%d\", rc);\n \t\treturn rc;\n@@ -731,7 +753,7 @@ nix_tm_sq_flush_post(struct roc_nix_sq *sq)\n \t\treturn 0;\n \n \t/* Restore backpressure */\n-\trc = nix_tm_bp_config_set(roc_nix, true);\n+\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, true);\n \tif (rc) {\n \t\tplt_err(\"Failed to restore backpressure, rc=%d\", rc);\n \t\treturn rc;\n@@ -1299,6 +1321,7 @@ nix_tm_prepare_default_tree(struct roc_nix *roc_nix)\n \t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n \t\tnode->lvl = lvl;\n \t\tnode->tree = ROC_NIX_TM_DEFAULT;\n+\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n \n \t\trc = nix_tm_node_add(roc_nix, node);\n \t\tif (rc)\n@@ -1325,6 +1348,7 @@ nix_tm_prepare_default_tree(struct roc_nix *roc_nix)\n \t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n \t\tnode->lvl = leaf_lvl;\n \t\tnode->tree = ROC_NIX_TM_DEFAULT;\n+\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n \n \t\trc = nix_tm_node_add(roc_nix, node);\n \t\tif (rc)\n@@ -1365,6 +1389,7 @@ roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix)\n \t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n \t\tnode->lvl = lvl;\n \t\tnode->tree = ROC_NIX_TM_RLIMIT;\n+\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n \n \t\trc = nix_tm_node_add(roc_nix, node);\n \t\tif (rc)\n@@ -1390,6 +1415,7 @@ roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix)\n \t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n \t\tnode->lvl = lvl;\n \t\tnode->tree = ROC_NIX_TM_RLIMIT;\n+\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n \n \t\trc = nix_tm_node_add(roc_nix, node);\n \t\tif (rc)\n@@ -1414,6 +1440,139 @@ roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix)\n \t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n \t\tnode->lvl = leaf_lvl;\n \t\tnode->tree = ROC_NIX_TM_RLIMIT;\n+\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n+\n+\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t}\n+\n+\treturn 0;\n+error:\n+\tnix_tm_node_free(node);\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_tm_pfc_prepare_tree(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint32_t nonleaf_id = nix->nb_tx_queues;\n+\tstruct nix_tm_node *node = NULL;\n+\tuint8_t leaf_lvl, lvl, lvl_end;\n+\tuint32_t tl2_node_id;\n+\tuint32_t parent, i;\n+\tint rc = -ENOMEM;\n+\n+\tparent = ROC_NIX_TM_NODE_ID_INVALID;\n+\tlvl_end = ROC_TM_LVL_SCH3;\n+\tleaf_lvl = ROC_TM_LVL_QUEUE;\n+\n+\t/* TL1 node */\n+\tnode = nix_tm_node_alloc();\n+\tif (!node)\n+\t\tgoto error;\n+\n+\tnode->id = nonleaf_id;\n+\tnode->parent_id = parent;\n+\tnode->priority = 0;\n+\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\tnode->lvl = ROC_TM_LVL_ROOT;\n+\tnode->tree = ROC_NIX_TM_PFC;\n+\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n+\n+\trc = nix_tm_node_add(roc_nix, node);\n+\tif (rc)\n+\t\tgoto error;\n+\n+\tparent = nonleaf_id;\n+\tnonleaf_id++;\n+\n+\t/* TL2 node */\n+\trc = -ENOMEM;\n+\tnode = nix_tm_node_alloc();\n+\tif (!node)\n+\t\tgoto error;\n+\n+\tnode->id = nonleaf_id;\n+\tnode->parent_id = parent;\n+\tnode->priority = 0;\n+\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\tnode->lvl = ROC_TM_LVL_SCH1;\n+\tnode->tree = ROC_NIX_TM_PFC;\n+\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n+\n+\trc = nix_tm_node_add(roc_nix, node);\n+\tif (rc)\n+\t\tgoto error;\n+\n+\ttl2_node_id = nonleaf_id;\n+\tnonleaf_id++;\n+\n+\tfor (i = 0; i < nix->nb_tx_queues; i++) {\n+\t\tparent = tl2_node_id;\n+\t\tfor (lvl = ROC_TM_LVL_SCH2; lvl <= lvl_end; lvl++) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tnode = nix_tm_node_alloc();\n+\t\t\tif (!node)\n+\t\t\t\tgoto error;\n+\n+\t\t\tnode->id = nonleaf_id;\n+\t\t\tnode->parent_id = parent;\n+\t\t\tnode->priority = 0;\n+\t\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\t\tnode->shaper_profile_id =\n+\t\t\t\tROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\t\tnode->lvl = lvl;\n+\t\t\tnode->tree = ROC_NIX_TM_PFC;\n+\t\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n+\n+\t\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\t\tif (rc)\n+\t\t\t\tgoto error;\n+\n+\t\t\tparent = nonleaf_id;\n+\t\t\tnonleaf_id++;\n+\t\t}\n+\n+\t\tlvl = ROC_TM_LVL_SCH4;\n+\n+\t\trc = -ENOMEM;\n+\t\tnode = nix_tm_node_alloc();\n+\t\tif (!node)\n+\t\t\tgoto error;\n+\n+\t\tnode->id = nonleaf_id;\n+\t\tnode->parent_id = parent;\n+\t\tnode->priority = 0;\n+\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\tnode->lvl = lvl;\n+\t\tnode->tree = ROC_NIX_TM_PFC;\n+\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n+\n+\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\n+\t\tparent = nonleaf_id;\n+\t\tnonleaf_id++;\n+\n+\t\trc = -ENOMEM;\n+\t\tnode = nix_tm_node_alloc();\n+\t\tif (!node)\n+\t\t\tgoto error;\n+\n+\t\tnode->id = i;\n+\t\tnode->parent_id = parent;\n+\t\tnode->priority = 0;\n+\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\tnode->lvl = leaf_lvl;\n+\t\tnode->tree = ROC_NIX_TM_PFC;\n+\t\tnode->rel_chan = NIX_TM_CHAN_INVALID;\n \n \t\trc = nix_tm_node_add(roc_nix, node);\n \t\tif (rc)\ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex 3d81247a12..d3d39eeb99 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -464,10 +464,16 @@ roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix)\n \t/* Disable backpressure, it will be enabled back if needed on\n \t * hierarchy enable\n \t */\n-\trc = nix_tm_bp_config_set(roc_nix, false);\n-\tif (rc) {\n-\t\tplt_err(\"Failed to disable backpressure for flush, rc=%d\", rc);\n-\t\tgoto cleanup;\n+\tfor (i = 0; i < sq_cnt; i++) {\n+\t\tsq = nix->sqs[i];\n+\t\tif (!sq)\n+\t\t\tcontinue;\n+\n+\t\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to disable backpressure, rc=%d\", rc);\n+\t\t\tgoto cleanup;\n+\t\t}\n \t}\n \n \t/* Flush all tx queues */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex ad1b5e8476..37ec100451 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -107,6 +107,7 @@ INTERNAL {\n \troc_nix_bpf_stats_reset;\n \troc_nix_bpf_stats_to_idx;\n \troc_nix_bpf_timeunit_get;\n+\troc_nix_chan_count_get;\n \troc_nix_cq_dump;\n \troc_nix_cq_fini;\n \troc_nix_cq_head_tail_get;\n@@ -198,6 +199,8 @@ INTERNAL {\n \troc_nix_npc_promisc_ena_dis;\n \troc_nix_npc_rx_ena_dis;\n \troc_nix_npc_mcast_config;\n+\troc_nix_pfc_mode_get;\n+\troc_nix_pfc_mode_set;\n \troc_nix_ptp_clock_read;\n \troc_nix_ptp_info_cb_register;\n \troc_nix_ptp_info_cb_unregister;\n@@ -263,6 +266,7 @@ INTERNAL {\n \troc_nix_tm_node_stats_get;\n \troc_nix_tm_node_suspend_resume;\n \troc_nix_tm_prealloc_res;\n+\troc_nix_tm_pfc_prepare_tree;\n \troc_nix_tm_prepare_rate_limited_tree;\n \troc_nix_tm_rlimit_sq;\n \troc_nix_tm_root_has_sp;\n", "prefixes": [ "v9", "1/2" ] }