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GET /api/patches/107288/?format=api
{ "id": 107288, "url": "http://patches.dpdk.org/api/patches/107288/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220210162926.20436-5-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220210162926.20436-5-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220210162926.20436-5-suanmingm@nvidia.com", "date": "2022-02-10T16:29:17", "name": "[04/13] net/mlx5: add pattern template management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d24b6a916fb1935f7972bbde224dbbc48c989211", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220210162926.20436-5-suanmingm@nvidia.com/mbox/", "series": [ { "id": 21609, "url": "http://patches.dpdk.org/api/series/21609/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21609", "date": "2022-02-10T16:29:13", "name": "net/mlx5: add hardware steering", "version": 1, "mbox": "http://patches.dpdk.org/series/21609/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/107288/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/107288/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 347C5A00BE;\n\tThu, 10 Feb 2022 17:30:15 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D21344117E;\n\tThu, 10 Feb 2022 17:29:59 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2044.outbound.protection.outlook.com [40.107.237.44])\n by mails.dpdk.org (Postfix) with ESMTP id C485641176\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH 04/13] net/mlx5: add pattern template management", "Date": "Thu, 10 Feb 2022 18:29:17 +0200", "Message-ID": "<20220210162926.20436-5-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220210162926.20436-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e20e2963-cdf0-4c4b-4aa1-08d9ecb291d7", "X-MS-TrafficTypeDiagnostic": "PH0PR12MB5420:EE_", "X-Microsoft-Antispam-PRVS": "\n <PH0PR12MB54204E36DB535E93D4B7E434C12F9@PH0PR12MB5420.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:901;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n itvO0DMQ/8BrglrNCrjRoj50rr7bJALGGeZdFti6pRUC1dRzI7LDXxxHMhMw58S7WGScsnBbZdGruFqaMN4dfYtFXKaMlCQMEg3QEy0MciSmbgZ6DYZ/z3M4C+ihD97hqaCPUH5Xw1kFbrzCsghiGlXuLRWiW9SrlBYzR4GRHY0DA3hn3atY+AqvT6gkbqp5m6cTkDwwNQpMICx3tzWdQWZ5P2OJQH/FPFkmrbBp9l2HlYj/rX0PjWAxqnyYVT6K/tXmx/oGX9ErLttcEICNX2vBPD8faxtkTlL0VhbHXy7r81kxgRT3nnrR9TA4qUok/qAH87uVBDvhPW0RELtTeoeTN/q+cYuyIq+LykznGcSpgkjd8viPZvj1/NTZyLDzQwd7XohIoOjn7GKfVIchCAR+wYemetf1QWeIC3rCY8M13EDrD6MxpwlgpsMA/9bEvZlUAaxtpmxBZzaf8lRbwxZztriYrHa2SMIRlMHqauxJpCfEnyKV7eZqwX+MzixiRvyoNpiq7q4/W9yla9rLQ9cpCRuGBmVmlb6KmlKVjfHGmxh60IjhKg6GhQylP7U+V9iZpPvncz8OaxjUQiXEKvRznJ9h/MIOl68qHTcX4Gz06tBM+JLbOC6WKXOUW7v8UFpzSe3OPlZj3bbw9rqSI5+Wcpco/dCuJImPg8hQ9j5mGdmy4FZDOfOxSHxV3P7A+9Hob0c6mYYI+3gtttlpSQ==", "X-Forefront-Antispam-Report": "CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(86362001)(316002)(8936002)(54906003)(2906002)(6636002)(8676002)(508600001)(82310400004)(2616005)(40460700003)(110136005)(356005)(6286002)(1076003)(26005)(186003)(336012)(426003)(16526019)(70586007)(5660300002)(47076005)(36860700001)(70206006)(55016003)(83380400001)(81166007)(6666004)(4326008)(7696005)(36756003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Feb 2022 16:29:54.3056 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e20e2963-cdf0-4c4b-4aa1-08d9ecb291d7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT008.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB5420", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The pattern template defines flows that have the same matching\nfields but with different matching values.\nFor example, matching on 5 tuple TCP flow, the template will be\n(eth(null) + IPv4(source + dest) + TCP(s_port + d_port) while\nthe values for each rule will be different.\n\nDue to the pattern template can be used in different domains, the\nitems will only be cached in pattern template create stage, while\nthe template is binded to a dedicated table, the HW criteria\nwill be created and saved to the table. And different tables\nmay create the same criteria and will not shared between each\nother in order to have better performance.\n\nThis commit adds pattern template management.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_flow.c | 64 +++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 20 ++++++++\n drivers/net/mlx5/mlx5_flow_hw.c | 82 +++++++++++++++++++++++++++++++++\n 4 files changed, 168 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 31a13ca69a..96048ad0ea 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1500,6 +1500,8 @@ struct mlx5_priv {\n \tstruct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM];\n \t/* Flex items have been created on the port. */\n \tuint32_t flex_item_map; /* Map of allocated flex item elements. */\n+\t/* Item template list. */\n+\tLIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt;\n \tstruct mlx5dr_context *dr_ctx; /**< HW steering DR context. */\n \tuint32_t nb_queue; /* HW steering queue number. */\n \t/* HW steering queue polling mechanism job descriptor LIFO. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 5ff96642b4..27a40a9627 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -812,6 +812,17 @@ mlx5_flow_port_configure(struct rte_eth_dev *dev,\n \t\t\t const struct rte_flow_queue_attr *queue_attr[],\n \t\t\t struct rte_flow_error *err);\n \n+static struct rte_flow_pattern_template *\n+mlx5_flow_pattern_template_create(struct rte_eth_dev *dev,\n+\t\tconst struct rte_flow_pattern_template_attr *attr,\n+\t\tconst struct rte_flow_item items[],\n+\t\tstruct rte_flow_error *error);\n+\n+static int\n+mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_flow_pattern_template *template,\n+\t\t\t\t struct rte_flow_error *error);\n+\n static const struct rte_flow_ops mlx5_flow_ops = {\n \t.validate = mlx5_flow_validate,\n \t.create = mlx5_flow_create,\n@@ -833,6 +844,8 @@ static const struct rte_flow_ops mlx5_flow_ops = {\n \t.flex_item_create = mlx5_flow_flex_item_create,\n \t.flex_item_release = mlx5_flow_flex_item_release,\n \t.configure = mlx5_flow_port_configure,\n+\t.pattern_template_create = mlx5_flow_pattern_template_create,\n+\t.pattern_template_destroy = mlx5_flow_pattern_template_destroy,\n };\n \n /* Tunnel information. */\n@@ -7851,6 +7864,57 @@ mlx5_flow_port_configure(struct rte_eth_dev *dev,\n \treturn fops->configure(dev, port_attr, nb_queue, queue_attr, err);\n }\n \n+/**\n+ * Create flow item template.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] attr\n+ * Pointer to the item template attributes.\n+ * @param[in] items\n+ * The template item pattern.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static struct rte_flow_pattern_template *\n+mlx5_flow_pattern_template_create(struct rte_eth_dev *dev,\n+\t\tconst struct rte_flow_pattern_template_attr *attr,\n+\t\tconst struct rte_flow_item items[],\n+\t\tstruct rte_flow_error *error)\n+{\n+\tconst struct mlx5_flow_driver_ops *fops =\n+\t\t\tflow_get_drv_ops(MLX5_FLOW_TYPE_HW);\n+\n+\treturn fops->pattern_template_create(dev, attr, items, error);\n+}\n+\n+/**\n+ * Destroy flow item template.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] template\n+ * Pointer to the item template to be destroyed.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_flow_pattern_template *template,\n+\t\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct mlx5_flow_driver_ops *fops =\n+\t\t\tflow_get_drv_ops(MLX5_FLOW_TYPE_HW);\n+\n+\treturn fops->pattern_template_destroy(dev, template, error);\n+}\n+\n /**\n * Allocate a new memory for the counter values wrapped by all the needed\n * management.\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 731478ff05..88102f0991 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1015,6 +1015,15 @@ struct rte_flow {\n \tuint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */\n } __rte_packed;\n \n+/* Flow item template struct. */\n+struct rte_flow_pattern_template {\n+\tLIST_ENTRY(rte_flow_pattern_template) next;\n+\t/* Template attributes. */\n+\tstruct rte_flow_pattern_template_attr attr;\n+\tstruct mlx5dr_match_template *mt; /* mlx5 match template. */\n+\tuint32_t refcnt; /* Reference counter. */\n+};\n+\n /*\n * Define list of valid combinations of RX Hash fields\n * (see enum ibv_rx_hash_fields).\n@@ -1263,6 +1272,15 @@ typedef int (*mlx5_flow_port_configure_t)\n \t\t\t uint16_t nb_queue,\n \t\t\t const struct rte_flow_queue_attr *queue_attr[],\n \t\t\t struct rte_flow_error *err);\n+typedef struct rte_flow_pattern_template *(*mlx5_flow_pattern_template_create_t)\n+\t\t\t(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_pattern_template_attr *attr,\n+\t\t\t const struct rte_flow_item items[],\n+\t\t\t struct rte_flow_error *error);\n+typedef int (*mlx5_flow_pattern_template_destroy_t)\n+\t\t\t(struct rte_eth_dev *dev,\n+\t\t\t struct rte_flow_pattern_template *template,\n+\t\t\t struct rte_flow_error *error);\n \n struct mlx5_flow_driver_ops {\n \tmlx5_flow_validate_t validate;\n@@ -1302,6 +1320,8 @@ struct mlx5_flow_driver_ops {\n \tmlx5_flow_item_release_t item_release;\n \tmlx5_flow_item_update_t item_update;\n \tmlx5_flow_port_configure_t configure;\n+\tmlx5_flow_pattern_template_create_t pattern_template_create;\n+\tmlx5_flow_pattern_template_destroy_t pattern_template_destroy;\n };\n \n /* mlx5_flow.c */\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 4194f81ee9..c984e520cd 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -12,6 +12,81 @@\n \n const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;\n \n+/**\n+ * Create flow item template.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] attr\n+ * Pointer to the item template attributes.\n+ * @param[in] items\n+ * The template item pattern.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * Item template pointer on success, NULL otherwise and rte_errno is set.\n+ */\n+static struct rte_flow_pattern_template *\n+flow_hw_pattern_template_create(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_pattern_template_attr *attr,\n+\t\t\t const struct rte_flow_item items[],\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct rte_flow_pattern_template *it;\n+\n+\tit = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*it), 0, SOCKET_ID_ANY);\n+\tif (!it) {\n+\t\trte_flow_error_set(error, ENOMEM,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t NULL,\n+\t\t\t\t \"cannot allocate item template\");\n+\t\treturn NULL;\n+\t}\n+\tit->attr = *attr;\n+\tit->mt = mlx5dr_match_template_create(items, attr->relaxed_matching);\n+\tif (!it->mt) {\n+\t\tmlx5_free(it);\n+\t\treturn NULL;\n+\t}\n+\t__atomic_fetch_add(&it->refcnt, 1, __ATOMIC_RELAXED);\n+\tLIST_INSERT_HEAD(&priv->flow_hw_itt, it, next);\n+\treturn it;\n+}\n+\n+/**\n+ * Destroy flow item template.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] template\n+ * Pointer to the item template to be destroyed.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+flow_hw_pattern_template_destroy(struct rte_eth_dev *dev __rte_unused,\n+\t\t\t struct rte_flow_pattern_template *template,\n+\t\t\t struct rte_flow_error *error __rte_unused)\n+{\n+\tif (__atomic_load_n(&template->refcnt, __ATOMIC_RELAXED) > 1) {\n+\t\tDRV_LOG(WARNING, \"Item template %p is still in use.\",\n+\t\t\t(void *)template);\n+\t\treturn rte_flow_error_set(error, EBUSY,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t NULL,\n+\t\t\t\t \"item template in using\");\n+\t}\n+\tLIST_REMOVE(template, next);\n+\tclaim_zero(mlx5dr_match_template_destroy(template->mt));\n+\tmlx5_free(template);\n+\treturn 0;\n+}\n+\n /**\n * Configure port HWS resources.\n *\n@@ -128,9 +203,14 @@ void\n flow_hw_resource_release(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct rte_flow_pattern_template *it;\n \n \tif (!priv->dr_ctx)\n \t\treturn;\n+\twhile (!LIST_EMPTY(&priv->flow_hw_itt)) {\n+\t\tit = LIST_FIRST(&priv->flow_hw_itt);\n+\t\tflow_hw_pattern_template_destroy(dev, it, NULL);\n+\t}\n \tmlx5_free(priv->hw_q);\n \tpriv->hw_q = NULL;\n \tclaim_zero(mlx5dr_context_close(priv->dr_ctx));\n@@ -140,6 +220,8 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \n const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = {\n \t.configure = flow_hw_configure,\n+\t.pattern_template_create = flow_hw_pattern_template_create,\n+\t.pattern_template_destroy = flow_hw_pattern_template_destroy,\n };\n \n #endif\n", "prefixes": [ "04/13" ] }