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{
    "id": 107113,
    "url": "http://patches.dpdk.org/api/patches/107113/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220209104213.602728-7-jiawenwu@trustnetic.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220209104213.602728-7-jiawenwu@trustnetic.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220209104213.602728-7-jiawenwu@trustnetic.com",
    "date": "2022-02-09T10:42:07",
    "name": "[v2,06/12] net/ngbe: add support to custom PHY interfaces",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "345f26903bd57771e922fcddf9b5efa589d86494",
    "submitter": {
        "id": 1932,
        "url": "http://patches.dpdk.org/api/people/1932/?format=api",
        "name": "Jiawen Wu",
        "email": "jiawenwu@trustnetic.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220209104213.602728-7-jiawenwu@trustnetic.com/mbox/",
    "series": [
        {
            "id": 21561,
            "url": "http://patches.dpdk.org/api/series/21561/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21561",
            "date": "2022-02-09T10:42:01",
            "name": "Wangxun fixes and supports",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/21561/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/107113/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/107113/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 15889A04A6;\n\tWed,  9 Feb 2022 11:36:09 +0100 (CET)",
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            "from wxdbg.localdomain.com (unknown [183.129.236.74])\n by bizesmtp.qq.com (ESMTP) with\n id ; Wed, 09 Feb 2022 18:35:44 +0800 (CST)"
        ],
        "X-QQ-mid": "bizesmtp37t1644402945tb64gmx2",
        "X-QQ-SSF": "01400000002000F0L000B00A0000000",
        "X-QQ-FEAT": "1vYwxPNStGmf9bON1C5sDZ6EjmgnuYPWATcbVHq7QmpSkCKh/IFuxd8ldOhHW\n piotFq77SOm+xlACOsiVNaCQGdY+FWrAA9wyPtETGtr9uI7I5uExmQ3w/WzCBFaUGyvX/5A\n oZ0nznvQ6rltEtDAz4wKIAyg09F02whaiXytdb1+1u3fGys6DNBKSyM//f4DCsCdgMPxe2h\n cITiDp6sP1P8ZkNuvgu73tUSpJMyFaInaecd4Puv3vMk+uiTXC+oOoZFhDK+LIdD00JMQXs\n Q2MoAZh4a+UYefg28TQ74Y1N1KFSKYlCv1VuK4Ap/d3sczAzUhFhWYVOEswJLe8cFiDwwkc\n P1KkhZhEfnv3k8CecJXDXuvlhVWre+I8J+vIY7D6SV1KQmgvIc=",
        "X-QQ-GoodBg": "2",
        "From": "Jiawen Wu <jiawenwu@trustnetic.com>",
        "To": "dev@dpdk.org",
        "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>",
        "Subject": "[PATCH v2 06/12] net/ngbe: add support to custom PHY interfaces",
        "Date": "Wed,  9 Feb 2022 18:42:07 +0800",
        "Message-Id": "<20220209104213.602728-7-jiawenwu@trustnetic.com>",
        "X-Mailer": "git-send-email 2.27.0",
        "In-Reply-To": "<20220209104213.602728-1-jiawenwu@trustnetic.com>",
        "References": "<20220209104213.602728-1-jiawenwu@trustnetic.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-QQ-SENDSIZE": "520",
        "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign1",
        "X-QQ-Bgrelay": "1",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
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    },
    "content": "Support sub_device ID 61/62/64 for YT8521S SFP, and 51/52 for M88E1512\nPHY.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/rel_notes/release_22_03.rst |   7 +\n drivers/net/ngbe/base/ngbe_devids.h    |  12 +-\n drivers/net/ngbe/base/ngbe_hw.c        |  50 +++++--\n drivers/net/ngbe/base/ngbe_phy.c       |  27 ++--\n drivers/net/ngbe/base/ngbe_phy.h       |   2 +-\n drivers/net/ngbe/base/ngbe_phy_mvl.c   |  55 +++++++-\n drivers/net/ngbe/base/ngbe_phy_mvl.h   |   5 +\n drivers/net/ngbe/base/ngbe_phy_yt.c    | 182 +++++++++++++++++++++----\n drivers/net/ngbe/base/ngbe_phy_yt.h    |  19 ++-\n drivers/net/ngbe/base/ngbe_type.h      |   8 ++\n drivers/net/ngbe/ngbe_ethdev.c         |   6 +-\n 11 files changed, 314 insertions(+), 59 deletions(-)",
    "diff": "diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst\nindex 746f50e84f..233c34a2d0 100644\n--- a/doc/guides/rel_notes/release_22_03.rst\n+++ b/doc/guides/rel_notes/release_22_03.rst\n@@ -69,6 +69,13 @@ New Features\n   * Added AES-XCBC support in lookaside protocol (IPsec) for CN9K & CN10K.\n   * Added AES-CMAC support in CN9K & CN10K.\n \n+* **Updated Wangxun ngbe driver.**\n+\n+  * Added support for devices of custom PHY interfaces.\n+    - M88E1512 PHY connects to RJ45\n+    - M88E1512 PHY connects to RGMII combo\n+    - YT8521S PHY connects to SFP\n+\n * **Added an API to retrieve event port id of ethdev Rx adapter.**\n \n   The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added.\ndiff --git a/drivers/net/ngbe/base/ngbe_devids.h b/drivers/net/ngbe/base/ngbe_devids.h\nindex 6010cc050e..83eedf423e 100644\n--- a/drivers/net/ngbe/base/ngbe_devids.h\n+++ b/drivers/net/ngbe/base/ngbe_devids.h\n@@ -19,9 +19,11 @@\n #define   NGBE_SUB_DEV_ID_EM_VF\t\t\t0x0110\n #define NGBE_DEV_ID_EM\t\t\t\t0x0100\n #define   NGBE_SUB_DEV_ID_EM_MVL_RGMII\t\t0x0200\n+#define   NGBE_SUB_DEV_ID_EM_MVL_MIX\t\t0x0252\n #define   NGBE_SUB_DEV_ID_EM_MVL_SFP\t\t0x0403\n #define   NGBE_SUB_DEV_ID_EM_RTL_SGMII\t\t0x0410\n #define   NGBE_SUB_DEV_ID_EM_YT8521S_SFP\t0x0460\n+#define   NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP\t0x0461\n \n #define NGBE_DEV_ID_EM_WX1860AL_W\t\t0x0100\n #define NGBE_DEV_ID_EM_WX1860AL_W_VF\t\t0x0110\n@@ -67,15 +69,19 @@\n #define   NGBE_SUB_DEV_ID_EM_SF400_LY_YT\t0x0470\n \n /* Assign excessive id with masks */\n-#define NGBE_INTERNAL_MASK\t\t\t0x000F\n-#define NGBE_OEM_MASK\t\t\t\t0x00F0\n+#define NGBE_OEM_MASK\t\t\t\t0x00FF\n #define NGBE_WOL_SUP_MASK\t\t\t0x4000\n #define NGBE_NCSI_SUP_MASK\t\t\t0x8000\n \n-#define NGBE_INTERNAL_SFP\t\t\t0x0003\n+#define NGBE_M88E1512_SFP\t\t\t0x0003\n #define NGBE_OCP_CARD\t\t\t\t0x0040\n #define NGBE_LY_M88E1512_SFP\t\t\t0x0050\n+#define NGBE_M88E1512_RJ45\t\t\t0x0051\n+#define NGBE_M88E1512_MIX\t\t\t0x0052\n #define NGBE_YT8521S_SFP\t\t\t0x0060\n+#define NGBE_INTERNAL_YT8521S_SFP\t\t0x0061\n+#define NGBE_YT8521S_SFP_GPIO\t\t\t0x0062\n+#define NGBE_INTERNAL_YT8521S_SFP_GPIO\t\t0x0064\n #define NGBE_LY_YT8521S_SFP\t\t\t0x0070\n #define NGBE_WOL_SUP\t\t\t\t0x4000\n #define NGBE_NCSI_SUP\t\t\t\t0x8000\ndiff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c\nindex 72d475ccf9..67e4b4a6fd 100644\n--- a/drivers/net/ngbe/base/ngbe_hw.c\n+++ b/drivers/net/ngbe/base/ngbe_hw.c\n@@ -124,8 +124,7 @@ ngbe_reset_misc_em(struct ngbe_hw *hw)\n \n \twr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);\n \n-\tif ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||\n-\t\t(hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {\n+\tif (hw->gpio_ctl) {\n \t\t/* gpio0 is used to power on/off control*/\n \t\twr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));\n \t\twr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);\n@@ -1617,19 +1616,21 @@ s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,\n \t\t\t\t      bool *autoneg)\n {\n \ts32 status = 0;\n-\n+\tu16 value = 0;\n \tDEBUGFUNC(\"\\n\");\n \n \thw->mac.autoneg = *autoneg;\n \n-\tswitch (hw->sub_device_id) {\n-\tcase NGBE_SUB_DEV_ID_EM_RTL_SGMII:\n+\tif (hw->phy.type == ngbe_phy_rtl) {\n \t\t*speed = NGBE_LINK_SPEED_1GB_FULL |\n \t\t\tNGBE_LINK_SPEED_100M_FULL |\n \t\t\tNGBE_LINK_SPEED_10M_FULL;\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n+\t}\n+\n+\tif (hw->phy.type == ngbe_phy_yt8521s_sfi) {\n+\t\tngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);\n+\t\tif ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1))\n+\t\t\t*speed = NGBE_LINK_SPEED_1GB_FULL;\n \t}\n \n \treturn status;\n@@ -1815,11 +1816,23 @@ s32 ngbe_set_mac_type(struct ngbe_hw *hw)\n \tcase NGBE_SUB_DEV_ID_EM_MVL_RGMII:\n \t\thw->phy.media_type = ngbe_media_type_copper;\n \t\thw->mac.type = ngbe_mac_em;\n+\t\thw->mac.link_type = ngbe_link_copper;\n+\t\tbreak;\n+\tcase NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP:\n+\t\thw->phy.media_type = ngbe_media_type_copper;\n+\t\thw->mac.type = ngbe_mac_em;\n+\t\thw->mac.link_type = ngbe_link_fiber;\n \t\tbreak;\n \tcase NGBE_SUB_DEV_ID_EM_MVL_SFP:\n \tcase NGBE_SUB_DEV_ID_EM_YT8521S_SFP:\n \t\thw->phy.media_type = ngbe_media_type_fiber;\n \t\thw->mac.type = ngbe_mac_em;\n+\t\thw->mac.link_type = ngbe_link_fiber;\n+\t\tbreak;\n+\tcase NGBE_SUB_DEV_ID_EM_MVL_MIX:\n+\t\thw->phy.media_type = ngbe_media_type_unknown;\n+\t\thw->mac.type = ngbe_mac_em;\n+\t\thw->mac.link_type = ngbe_link_type_unknown;\n \t\tbreak;\n \tcase NGBE_SUB_DEV_ID_EM_VF:\n \t\thw->phy.media_type = ngbe_media_type_virtual;\n@@ -1871,7 +1884,7 @@ s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)\n void ngbe_map_device_id(struct ngbe_hw *hw)\n {\n \tu16 oem = hw->sub_system_id & NGBE_OEM_MASK;\n-\tu16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK;\n+\n \thw->is_pf = true;\n \n \t/* move subsystem_device_id to device_id */\n@@ -1905,20 +1918,31 @@ void ngbe_map_device_id(struct ngbe_hw *hw)\n \tcase NGBE_DEV_ID_EM_WX1860A1:\n \tcase NGBE_DEV_ID_EM_WX1860A1L:\n \t\thw->device_id = NGBE_DEV_ID_EM;\n-\t\tif (oem == NGBE_LY_M88E1512_SFP ||\n-\t\t\t\tinternal == NGBE_INTERNAL_SFP)\n+\t\tif (oem == NGBE_M88E1512_SFP || oem == NGBE_LY_M88E1512_SFP)\n \t\t\thw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;\n-\t\telse if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)\n+\t\telse if (oem == NGBE_M88E1512_RJ45 ||\n+\t\t\t(hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45))\n \t\t\thw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;\n+\t\telse if (oem == NGBE_M88E1512_MIX)\n+\t\t\thw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_MIX;\n \t\telse if (oem == NGBE_YT8521S_SFP ||\n-\t\t\t\toem == NGBE_LY_YT8521S_SFP)\n+\t\t\t oem == NGBE_YT8521S_SFP_GPIO ||\n+\t\t\t oem == NGBE_LY_YT8521S_SFP)\n \t\t\thw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;\n+\t\telse if (oem == NGBE_INTERNAL_YT8521S_SFP ||\n+\t\t\t oem == NGBE_INTERNAL_YT8521S_SFP_GPIO)\n+\t\t\thw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP;\n \t\telse\n \t\t\thw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n+\n+\tif (oem == NGBE_LY_M88E1512_SFP || oem == NGBE_YT8521S_SFP_GPIO ||\n+\t\t\toem == NGBE_INTERNAL_YT8521S_SFP_GPIO ||\n+\t\t\toem == NGBE_LY_YT8521S_SFP)\n+\t\thw->gpio_ctl = true;\n }\n \n /**\ndiff --git a/drivers/net/ngbe/base/ngbe_phy.c b/drivers/net/ngbe/base/ngbe_phy.c\nindex 51b0a2ec60..93450b2977 100644\n--- a/drivers/net/ngbe/base/ngbe_phy.c\n+++ b/drivers/net/ngbe/base/ngbe_phy.c\n@@ -54,8 +54,7 @@ static bool ngbe_probe_phy(struct ngbe_hw *hw, u16 phy_addr)\n \tif (ngbe_get_phy_id(hw))\n \t\treturn false;\n \n-\thw->phy.type = ngbe_get_phy_type_from_id(hw);\n-\tif (hw->phy.type == ngbe_phy_unknown)\n+\tif (ngbe_get_phy_type_from_id(hw))\n \t\treturn false;\n \n \treturn true;\n@@ -174,37 +173,39 @@ s32 ngbe_get_phy_id(struct ngbe_hw *hw)\n \n /**\n  *  ngbe_get_phy_type_from_id - Get the phy type\n- *  @phy_id: PHY ID information\n  *\n  **/\n-enum ngbe_phy_type ngbe_get_phy_type_from_id(struct ngbe_hw *hw)\n+s32 ngbe_get_phy_type_from_id(struct ngbe_hw *hw)\n {\n-\tenum ngbe_phy_type phy_type;\n+\ts32 status = 0;\n \n \tDEBUGFUNC(\"ngbe_get_phy_type_from_id\");\n \n \tswitch (hw->phy.id) {\n \tcase NGBE_PHYID_RTL:\n-\t\tphy_type = ngbe_phy_rtl;\n+\t\thw->phy.type = ngbe_phy_rtl;\n \t\tbreak;\n \tcase NGBE_PHYID_MVL:\n \t\tif (hw->phy.media_type == ngbe_media_type_fiber)\n-\t\t\tphy_type = ngbe_phy_mvl_sfi;\n+\t\t\thw->phy.type = ngbe_phy_mvl_sfi;\n+\t\telse if (hw->phy.media_type == ngbe_media_type_copper)\n+\t\t\thw->phy.type = ngbe_phy_mvl;\n \t\telse\n-\t\t\tphy_type = ngbe_phy_mvl;\n+\t\t\tstatus = ngbe_check_phy_mode_mvl(hw);\n \t\tbreak;\n \tcase NGBE_PHYID_YT:\n \t\tif (hw->phy.media_type == ngbe_media_type_fiber)\n-\t\t\tphy_type = ngbe_phy_yt8521s_sfi;\n+\t\t\thw->phy.type = ngbe_phy_yt8521s_sfi;\n \t\telse\n-\t\t\tphy_type = ngbe_phy_yt8521s;\n+\t\t\thw->phy.type = ngbe_phy_yt8521s;\n \t\tbreak;\n \tdefault:\n-\t\tphy_type = ngbe_phy_unknown;\n+\t\thw->phy.type = ngbe_phy_unknown;\n+\t\tstatus = NGBE_ERR_DEVICE_NOT_SUPPORTED;\n \t\tbreak;\n \t}\n \n-\treturn phy_type;\n+\treturn status;\n }\n \n /**\n@@ -400,11 +401,13 @@ s32 ngbe_init_phy(struct ngbe_hw *hw)\n \n \tswitch (hw->sub_device_id) {\n \tcase NGBE_SUB_DEV_ID_EM_RTL_SGMII:\n+\tcase NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP:\n \t\thw->phy.read_reg_unlocked = ngbe_read_phy_reg_rtl;\n \t\thw->phy.write_reg_unlocked = ngbe_write_phy_reg_rtl;\n \t\tbreak;\n \tcase NGBE_SUB_DEV_ID_EM_MVL_RGMII:\n \tcase NGBE_SUB_DEV_ID_EM_MVL_SFP:\n+\tcase NGBE_SUB_DEV_ID_EM_MVL_MIX:\n \t\thw->phy.read_reg_unlocked = ngbe_read_phy_reg_mvl;\n \t\thw->phy.write_reg_unlocked = ngbe_write_phy_reg_mvl;\n \t\tbreak;\ndiff --git a/drivers/net/ngbe/base/ngbe_phy.h b/drivers/net/ngbe/base/ngbe_phy.h\nindex f262ff3350..e93d6a4c4a 100644\n--- a/drivers/net/ngbe/base/ngbe_phy.h\n+++ b/drivers/net/ngbe/base/ngbe_phy.h\n@@ -48,7 +48,7 @@ typedef struct mdi_reg mdi_reg_t;\n s32 ngbe_mdi_map_register(mdi_reg_t *reg, mdi_reg_22_t *reg22);\n \n bool ngbe_validate_phy_addr(struct ngbe_hw *hw, u32 phy_addr);\n-enum ngbe_phy_type ngbe_get_phy_type_from_id(struct ngbe_hw *hw);\n+s32 ngbe_get_phy_type_from_id(struct ngbe_hw *hw);\n s32 ngbe_get_phy_id(struct ngbe_hw *hw);\n s32 ngbe_identify_phy(struct ngbe_hw *hw);\n s32 ngbe_reset_phy(struct ngbe_hw *hw);\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c\nindex 2eb351d258..8a4df90a42 100644\n--- a/drivers/net/ngbe/base/ngbe_phy_mvl.c\n+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c\n@@ -48,6 +48,31 @@ s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw,\n \treturn 0;\n }\n \n+s32 ngbe_check_phy_mode_mvl(struct ngbe_hw *hw)\n+{\n+\tu16 value = 0;\n+\n+\t/* select page 18 reg 20 */\n+\tngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 18);\n+\tngbe_read_phy_reg_mdi(hw, MVL_GEN_CTL, 0, &value);\n+\tif (MVL_GEN_CTL_MODE(value) == MVL_GEN_CTL_MODE_COPPER) {\n+\t\t/* mode select to RGMII-to-copper */\n+\t\thw->phy.type = ngbe_phy_mvl;\n+\t\thw->phy.media_type = ngbe_media_type_copper;\n+\t\thw->mac.link_type = ngbe_link_copper;\n+\t} else if (MVL_GEN_CTL_MODE(value) == MVL_GEN_CTL_MODE_FIBER) {\n+\t\t/* mode select to RGMII-to-sfi */\n+\t\thw->phy.type = ngbe_phy_mvl_sfi;\n+\t\thw->phy.media_type = ngbe_media_type_fiber;\n+\t\thw->mac.link_type = ngbe_link_fiber;\n+\t} else {\n+\t\tDEBUGOUT(\"marvell 88E1512 mode %x is not supported.\\n\", value);\n+\t\treturn NGBE_ERR_DEVICE_NOT_SUPPORTED;\n+\t}\n+\n+\treturn 0;\n+}\n+\n s32 ngbe_init_phy_mvl(struct ngbe_hw *hw)\n {\n \ts32 ret_val = 0;\n@@ -125,6 +150,29 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,\n \thw->phy.autoneg_advertised = 0;\n \n \tif (hw->phy.type == ngbe_phy_mvl) {\n+\t\tif (!hw->mac.autoneg) {\n+\t\t\tswitch (speed) {\n+\t\t\tcase NGBE_LINK_SPEED_1GB_FULL:\n+\t\t\t\tvalue = MVL_CTRL_SPEED_SELECT1;\n+\t\t\t\tbreak;\n+\t\t\tcase NGBE_LINK_SPEED_100M_FULL:\n+\t\t\t\tvalue = MVL_CTRL_SPEED_SELECT0;\n+\t\t\t\tbreak;\n+\t\t\tcase NGBE_LINK_SPEED_10M_FULL:\n+\t\t\t\tvalue = 0;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tvalue = MVL_CTRL_SPEED_SELECT0 |\n+\t\t\t\t\tMVL_CTRL_SPEED_SELECT1;\n+\t\t\t\tDEBUGOUT(\"unknown speed = 0x%x.\\n\", speed);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\t/* duplex full */\n+\t\t\tvalue |= MVL_CTRL_DUPLEX | MVL_CTRL_RESET;\n+\t\t\tngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);\n+\n+\t\t\tgoto skip_an;\n+\t\t}\n \t\tif (speed & NGBE_LINK_SPEED_1GB_FULL) {\n \t\t\tvalue_r9 |= MVL_PHY_1000BASET_FULL;\n \t\t\thw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;\n@@ -162,7 +210,12 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,\n \t\thw->phy.write_reg(hw, MVL_ANA, 0, value);\n \t}\n \n-\tvalue = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE;\n+\tvalue = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | MVL_CTRL_RESET;\n+\tngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);\n+\n+skip_an:\n+\tngbe_read_phy_reg_mdi(hw, MVL_CTRL, 0, &value);\n+\tvalue |= MVL_CTRL_PWDN;\n \tngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);\n \n \thw->phy.read_reg(hw, MVL_INTR, 0, &value);\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.h b/drivers/net/ngbe/base/ngbe_phy_mvl.h\nindex a2b5202d4b..8aee236390 100644\n--- a/drivers/net/ngbe/base/ngbe_phy_mvl.h\n+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.h\n@@ -12,8 +12,12 @@\n /* Page 0 for Copper, Page 1 for Fiber */\n #define MVL_CTRL\t\t\t0x0\n #define   MVL_CTRL_RESET\t\tMS16(15, 0x1)\n+#define\t  MVL_CTRL_SPEED_SELECT0\tMS16(13, 0x1)\n #define   MVL_CTRL_ANE\t\t\tMS16(12, 0x1)\n+#define   MVL_CTRL_PWDN\t\t\tMS16(11, 0x1)\n #define   MVL_CTRL_RESTART_AN\t\tMS16(9, 0x1)\n+#define   MVL_CTRL_DUPLEX\t\tMS16(8, 0x1)\n+#define\t  MVL_CTRL_SPEED_SELECT1\tMS16(6, 0x1)\n #define MVL_ANA\t\t\t\t0x4\n /* copper */\n #define   MVL_CANA_ASM_PAUSE\t\tMS16(11, 0x1)\n@@ -86,6 +90,7 @@ s32 ngbe_read_phy_reg_mvl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n \t\t\tu16 *phy_data);\n s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n \t\t\tu16 phy_data);\n+s32 ngbe_check_phy_mode_mvl(struct ngbe_hw *hw);\n s32 ngbe_init_phy_mvl(struct ngbe_hw *hw);\n \n s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw);\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c\nindex 8db0f9ce48..2d184a1c30 100644\n--- a/drivers/net/ngbe/base/ngbe_phy_yt.c\n+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c\n@@ -104,23 +104,22 @@ s32 ngbe_init_phy_yt(struct ngbe_hw *hw)\n \n \tDEBUGFUNC(\"ngbe_init_phy_yt\");\n \n-\tif (hw->phy.type != ngbe_phy_yt8521s_sfi)\n-\t\treturn 0;\n-\n-\t/* select sds area register */\n+\t/* close sds area register */\n \tngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);\n \t/* enable interrupts */\n-\tngbe_write_phy_reg_mdi(hw, YT_INTR, 0, YT_INTR_ENA_MASK);\n-\n-\t/* select fiber_to_rgmii first in multiplex */\n-\tngbe_read_phy_reg_ext_yt(hw, YT_MISC, 0, &value);\n-\tvalue |= YT_MISC_FIBER_PRIO;\n-\tngbe_write_phy_reg_ext_yt(hw, YT_MISC, 0, value);\n+\tngbe_write_phy_reg_mdi(hw, YT_INTR, 0,\n+\t\t\t\tYT_INTR_ENA_MASK | YT_SDS_INTR_ENA_MASK);\n \n+\t/* power down in fiber mode */\n \thw->phy.read_reg(hw, YT_BCR, 0, &value);\n \tvalue |= YT_BCR_PWDN;\n \thw->phy.write_reg(hw, YT_BCR, 0, value);\n \n+\t/* power down in UTP mode */\n+\tngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);\n+\tvalue |= YT_BCR_PWDN;\n+\tngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);\n+\n \treturn 0;\n }\n \n@@ -136,15 +135,44 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \n \thw->phy.autoneg_advertised = 0;\n \n-\tif (hw->phy.type == ngbe_phy_yt8521s) {\n+\t/* check chip_mode first */\n+\tngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);\n+\tif ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(0)) {\n+\t\t/* UTP to rgmii */\n+\t\tif (!hw->mac.autoneg) {\n+\t\t\tswitch (speed) {\n+\t\t\tcase NGBE_LINK_SPEED_1GB_FULL:\n+\t\t\t\tvalue = YT_BCR_SPEED_SELECT1;\n+\t\t\t\tbreak;\n+\t\t\tcase NGBE_LINK_SPEED_100M_FULL:\n+\t\t\t\tvalue = YT_BCR_SPEED_SELECT0;\n+\t\t\t\tbreak;\n+\t\t\tcase NGBE_LINK_SPEED_10M_FULL:\n+\t\t\t\tvalue = 0;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tvalue = YT_BCR_SPEED_SELECT0 |\n+\t\t\t\t\tYT_BCR_SPEED_SELECT1;\n+\t\t\t\tDEBUGOUT(\"unknown speed = 0x%x.\\n\",\n+\t\t\t\t\tspeed);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\t/* duplex full */\n+\t\t\tvalue |= YT_BCR_DUPLEX | YT_BCR_RESET;\n+\t\t\thw->phy.write_reg(hw, YT_BCR, 0, value);\n+\n+\t\t\tgoto skip_an;\n+\t\t}\n+\n \t\t/*disable 100/10base-T Self-negotiation ability*/\n \t\thw->phy.read_reg(hw, YT_ANA, 0, &value);\n-\t\tvalue &= ~(YT_ANA_100BASET_FULL | YT_ANA_10BASET_FULL);\n+\t\tvalue &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |\n+\t\t\tYT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);\n \t\thw->phy.write_reg(hw, YT_ANA, 0, value);\n \n \t\t/*disable 1000base-T Self-negotiation ability*/\n \t\thw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);\n-\t\tvalue &= ~YT_MS_1000BASET_FULL;\n+\t\tvalue &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);\n \t\thw->phy.write_reg(hw, YT_MS_CTRL, 0, value);\n \n \t\tif (speed & NGBE_LINK_SPEED_1GB_FULL) {\n@@ -172,9 +200,15 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \n \t\t/* software reset to make the above configuration take effect*/\n \t\thw->phy.read_reg(hw, YT_BCR, 0, &value);\n-\t\tvalue |= YT_BCR_RESET;\n+\t\tvalue |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;\n \t\thw->phy.write_reg(hw, YT_BCR, 0, value);\n-\t} else {\n+skip_an:\n+\t\t/* power on in UTP mode */\n+\t\tngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);\n+\t\tvalue &= ~YT_BCR_PWDN;\n+\t\tngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);\n+\t} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) {\n+\t\t/* fiber to rgmii */\n \t\thw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;\n \n \t\t/* RGMII_Config1 : Config rx and tx training delay */\n@@ -190,6 +224,88 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,\n \t\t/* software reset */\n \t\tngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140);\n \n+\t\t/* power on phy */\n+\t\thw->phy.read_reg(hw, YT_BCR, 0, &value);\n+\t\tvalue &= ~YT_BCR_PWDN;\n+\t\thw->phy.write_reg(hw, YT_BCR, 0, value);\n+\t} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) {\n+\t\t/* power on in UTP mode */\n+\t\tngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);\n+\t\tvalue &= ~YT_BCR_PWDN;\n+\t\tngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);\n+\t\t/* power down in fiber mode */\n+\t\thw->phy.read_reg(hw, YT_BCR, 0, &value);\n+\t\tvalue &= ~YT_BCR_PWDN;\n+\t\thw->phy.write_reg(hw, YT_BCR, 0, value);\n+\n+\t\thw->phy.read_reg(hw, YT_SPST, 0, &value);\n+\t\tif (value & YT_SPST_LINK) {\n+\t\t\t/* fiber up */\n+\t\t\thw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;\n+\t\t} else {\n+\t\t\t/* utp up */\n+\t\t\t/*disable 100/10base-T Self-negotiation ability*/\n+\t\t\thw->phy.read_reg(hw, YT_ANA, 0, &value);\n+\t\t\tvalue &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |\n+\t\t\t\tYT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);\n+\t\t\thw->phy.write_reg(hw, YT_ANA, 0, value);\n+\n+\t\t\t/*disable 1000base-T Self-negotiation ability*/\n+\t\t\thw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);\n+\t\t\tvalue &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);\n+\t\t\thw->phy.write_reg(hw, YT_MS_CTRL, 0, value);\n+\n+\t\t\tif (speed & NGBE_LINK_SPEED_1GB_FULL) {\n+\t\t\t\thw->phy.autoneg_advertised |=\n+\t\t\t\t\t\tNGBE_LINK_SPEED_1GB_FULL;\n+\t\t\t\tvalue_r9 |= YT_MS_1000BASET_FULL;\n+\t\t\t}\n+\t\t\tif (speed & NGBE_LINK_SPEED_100M_FULL) {\n+\t\t\t\thw->phy.autoneg_advertised |=\n+\t\t\t\t\t\tNGBE_LINK_SPEED_100M_FULL;\n+\t\t\t\tvalue_r4 |= YT_ANA_100BASET_FULL;\n+\t\t\t}\n+\t\t\tif (speed & NGBE_LINK_SPEED_10M_FULL) {\n+\t\t\t\thw->phy.autoneg_advertised |=\n+\t\t\t\t\t\tNGBE_LINK_SPEED_10M_FULL;\n+\t\t\t\tvalue_r4 |= YT_ANA_10BASET_FULL;\n+\t\t\t}\n+\n+\t\t\t/* enable 1000base-T Self-negotiation ability */\n+\t\t\thw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);\n+\t\t\tvalue |= value_r9;\n+\t\t\thw->phy.write_reg(hw, YT_MS_CTRL, 0, value);\n+\n+\t\t\t/* enable 100/10base-T Self-negotiation ability */\n+\t\t\thw->phy.read_reg(hw, YT_ANA, 0, &value);\n+\t\t\tvalue |= value_r4;\n+\t\t\thw->phy.write_reg(hw, YT_ANA, 0, value);\n+\n+\t\t\t/* software reset to make the above configuration\n+\t\t\t * take effect\n+\t\t\t */\n+\t\t\thw->phy.read_reg(hw, YT_BCR, 0, &value);\n+\t\t\tvalue |= YT_BCR_RESET;\n+\t\t\thw->phy.write_reg(hw, YT_BCR, 0, value);\n+\t\t}\n+\t} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) {\n+\t\thw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;\n+\n+\t\tngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, &value);\n+\t\tvalue |= YT_RGMII_CONF1_MODE;\n+\t\tngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value);\n+\n+\t\tngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF2, 0, &value);\n+\t\tvalue &= ~(YT_RGMII_CONF2_SPEED_MASK | YT_RGMII_CONF2_DUPLEX |\n+\t\t\tYT_RGMII_CONF2_LINKUP);\n+\t\tvalue |= YT_RGMII_CONF2_SPEED(2) | YT_RGMII_CONF2_DUPLEX |\n+\t\t\tYT_RGMII_CONF2_LINKUP;\n+\t\tngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF2, 0, value);\n+\n+\t\tngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);\n+\t\tvalue &= ~YT_SMI_PHY_SW_RST;\n+\t\tngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);\n+\n \t\t/* power on phy */\n \t\thw->phy.read_reg(hw, YT_BCR, 0, &value);\n \t\tvalue &= ~YT_BCR_PWDN;\n@@ -214,16 +330,34 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)\n \t\thw->phy.type != ngbe_phy_yt8521s_sfi)\n \t\treturn NGBE_ERR_PHY_TYPE;\n \n-\tstatus = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);\n-\t/* sds software reset */\n-\tctrl |= YT_BCR_RESET;\n-\tstatus = hw->phy.write_reg(hw, YT_BCR, 0, ctrl);\n-\n-\tfor (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) {\n+\t/* check chip_mode first */\n+\tngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &ctrl);\n+\tif (ctrl & YT_CHIP_MODE_MASK) {\n+\t\t/* fiber to rgmii */\n \t\tstatus = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);\n-\t\tif (!(ctrl & YT_BCR_RESET))\n-\t\t\tbreak;\n-\t\tmsleep(1);\n+\t\t/* sds software reset */\n+\t\tctrl |= YT_BCR_RESET;\n+\t\tstatus = hw->phy.write_reg(hw, YT_BCR, 0, ctrl);\n+\n+\t\tfor (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) {\n+\t\t\tstatus = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);\n+\t\t\tif (!(ctrl & YT_BCR_RESET))\n+\t\t\t\tbreak;\n+\t\t\tmsleep(1);\n+\t\t}\n+\t} else {\n+\t\t/* UTP to rgmii */\n+\t\tstatus = ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &ctrl);\n+\t\t/* sds software reset */\n+\t\tctrl |= YT_BCR_RESET;\n+\t\tstatus = ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, ctrl);\n+\n+\t\tfor (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) {\n+\t\t\tstatus = ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &ctrl);\n+\t\t\tif (!(ctrl & YT_BCR_RESET))\n+\t\t\t\tbreak;\n+\t\t\tmsleep(1);\n+\t\t}\n \t}\n \n \tif (i == YT_PHY_RST_WAIT_PERIOD) {\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h\nindex e729e0c854..c8763a90df 100644\n--- a/drivers/net/ngbe/base/ngbe_phy_yt.h\n+++ b/drivers/net/ngbe/base/ngbe_phy_yt.h\n@@ -11,26 +11,41 @@\n \n /* Common EXT */\n #define YT_SMI_PHY\t\t\t0xA000\n+#define   YT_SMI_PHY_SW_RST\t\tMS16(15, 0x1)\n #define   YT_SMI_PHY_SDS\t\tMS16(1, 0x1) /* 0 for UTP */\n #define YT_CHIP\t\t\t\t0xA001\n #define   YT_CHIP_SW_RST\t\tMS16(15, 0x1)\n #define   YT_CHIP_SW_LDO_EN\t\tMS16(6, 0x1)\n+#define   YT_CHIP_MODE_MASK\t\tMS16(0, 0x7)\n #define   YT_CHIP_MODE_SEL(v)\t\tLS16(v, 0, 0x7)\n #define YT_RGMII_CONF1\t\t\t0xA003\n+#define   YT_RGMII_CONF1_MODE\t\tMS16(15, 0x1)\n #define   YT_RGMII_CONF1_RXDELAY\tMS16(10, 0xF)\n #define   YT_RGMII_CONF1_TXDELAY_FE\tMS16(4, 0xF)\n #define   YT_RGMII_CONF1_TXDELAY\tMS16(0, 0x1)\n+#define YT_RGMII_CONF2\t\t\t0xA004\n+#define   YT_RGMII_CONF2_SPEED_MASK\tMS16(6, 0x3)\n+#define   YT_RGMII_CONF2_SPEED(v)\tLS16(v, 6, 0x3)\n+#define   YT_RGMII_CONF2_DUPLEX\t\tMS16(5, 0x1)\n+#define   YT_RGMII_CONF2_LINKUP\t\tMS16(4, 0x1)\n #define YT_MISC\t\t\t\t0xA006\n #define   YT_MISC_FIBER_PRIO\t\tMS16(8, 0x1) /* 0 for UTP */\n \n /* MII common registers in UTP and SDS */\n #define YT_BCR\t\t\t\t0x0\n #define   YT_BCR_RESET\t\t\tMS16(15, 0x1)\n+#define\t  YT_BCR_SPEED_SELECT0\t\tMS16(13, 0x1)\n+#define   YT_BCR_ANE\t\t\tMS16(12, 0x1)\n #define   YT_BCR_PWDN\t\t\tMS16(11, 0x1)\n+#define   YT_BCR_RESTART_AN\t\tMS16(9, 0x1)\n+#define   YT_BCR_DUPLEX\t\t\tMS16(8, 0x1)\n+#define   YT_BCR_SPEED_SELECT1\t\tMS16(6, 0x1)\n #define YT_ANA\t\t\t\t0x4\n /* copper */\n #define   YT_ANA_100BASET_FULL\t\tMS16(8, 0x1)\n+#define   YT_ANA_100BASET_HALF\t\tMS16(7, 0x1)\n #define   YT_ANA_10BASET_FULL\t\tMS16(6, 0x1)\n+#define   YT_ANA_10BASET_HALF\t\tMS16(5, 0x1)\n /* fiber */\n #define   YT_FANA_PAUSE_MASK\t\tMS16(7, 0x3)\n \n@@ -41,6 +56,7 @@\n \n #define YT_MS_CTRL\t\t\t0x9\n #define   YT_MS_1000BASET_FULL\t\tMS16(9, 0x1)\n+#define   YT_MS_1000BASET_HALF\t\tMS16(8, 0x1)\n #define YT_SPST\t\t\t\t0x11\n #define   YT_SPST_SPEED_MASK\t\tMS16(14, 0x3)\n #define\t    YT_SPST_SPEED_1000M\t\tLS16(2, 14, 0x3)\n@@ -50,7 +66,8 @@\n \n /* UTP only */\n #define YT_INTR\t\t\t\t0x12\n-#define   YT_INTR_ENA_MASK\t\tMS16(2, 0x3)\n+#define   YT_INTR_ENA_MASK\t\tMS16(10, 0x3)\n+#define   YT_SDS_INTR_ENA_MASK\t\tMS16(2, 0x3)\n #define YT_INTR_STATUS\t\t\t0x13\n \n s32 ngbe_read_phy_reg_yt(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\ndiff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h\nindex 4c995e7397..cb8d65ff27 100644\n--- a/drivers/net/ngbe/base/ngbe_type.h\n+++ b/drivers/net/ngbe/base/ngbe_type.h\n@@ -44,6 +44,12 @@ enum ngbe_eeprom_type {\n \tngbe_eeprom_none /* No NVM support */\n };\n \n+enum ngbe_link_type {\n+\tngbe_link_type_unknown = 0,\n+\tngbe_link_fiber,\n+\tngbe_link_copper\n+};\n+\n enum ngbe_mac_type {\n \tngbe_mac_unknown = 0,\n \tngbe_mac_em,\n@@ -312,6 +318,7 @@ struct ngbe_mac_info {\n \ts32 (*check_overtemp)(struct ngbe_hw *hw);\n \n \tenum ngbe_mac_type type;\n+\tenum ngbe_link_type link_type;\n \tu8 addr[ETH_ADDR_LEN];\n \tu8 perm_addr[ETH_ADDR_LEN];\n #define NGBE_MAX_MTA\t\t\t128\n@@ -422,6 +429,7 @@ struct ngbe_hw {\n \tu32 q_tx_regs[8 * 4];\n \tbool offset_loaded;\n \tbool is_pf;\n+\tbool gpio_ctl;\n \tstruct {\n \t\tu64 rx_qp_packets;\n \t\tu64 tx_qp_packets;\ndiff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c\nindex cc530fdced..9f42c26f9b 100644\n--- a/drivers/net/ngbe/ngbe_ethdev.c\n+++ b/drivers/net/ngbe/ngbe_ethdev.c\n@@ -1097,8 +1097,7 @@ ngbe_dev_start(struct rte_eth_dev *dev)\n \t/* resume enabled intr since HW reset */\n \tngbe_enable_intr(dev);\n \n-\tif ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||\n-\t\t(hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {\n+\tif (hw->gpio_ctl) {\n \t\t/* gpio0 is used to power on/off control*/\n \t\twr32(hw, NGBE_GPIODATA, 0);\n \t}\n@@ -1141,8 +1140,7 @@ ngbe_dev_stop(struct rte_eth_dev *dev)\n \n \trte_eal_alarm_cancel(ngbe_dev_setup_link_alarm_handler, dev);\n \n-\tif ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||\n-\t\t(hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {\n+\tif (hw->gpio_ctl) {\n \t\t/* gpio0 is used to power on/off control*/\n \t\twr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);\n \t}\n",
    "prefixes": [
        "v2",
        "06/12"
    ]
}