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{
    "id": 107036,
    "url": "http://patches.dpdk.org/api/patches/107036/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220208181454.69121-6-kai.ji@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220208181454.69121-6-kai.ji@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220208181454.69121-6-kai.ji@intel.com",
    "date": "2022-02-08T18:14:49",
    "name": "[v7,05/10] crypto/qat: rework asymmetric crypto build operation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "188434914857c05190b58d2c7bef4616e641a675",
    "submitter": {
        "id": 2202,
        "url": "http://patches.dpdk.org/api/people/2202/?format=api",
        "name": "Ji, Kai",
        "email": "kai.ji@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220208181454.69121-6-kai.ji@intel.com/mbox/",
    "series": [
        {
            "id": 21530,
            "url": "http://patches.dpdk.org/api/series/21530/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21530",
            "date": "2022-02-08T18:14:44",
            "name": "drivers/qat: QAT symmetric crypto datapatch rework",
            "version": 7,
            "mbox": "http://patches.dpdk.org/series/21530/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/107036/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/107036/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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            "E=Sophos;i=\"5.88,353,1635231600\"; d=\"scan'208\";a=\"540720184\""
        ],
        "X-ExtLoop1": "1",
        "From": "Kai Ji <kai.ji@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "gakhil@marvell.com,\n\tKai Ji <kai.ji@intel.com>",
        "Subject": "[dpdk-dev v7 05/10] crypto/qat: rework asymmetric crypto build\n operation",
        "Date": "Wed,  9 Feb 2022 02:14:49 +0800",
        "Message-Id": "<20220208181454.69121-6-kai.ji@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20220208181454.69121-1-kai.ji@intel.com>",
        "References": "<20220204185057.29893-11-kai.ji@intel.com>\n <20220208181454.69121-1-kai.ji@intel.com>",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "This patch reworks the asymmetric crypto data path\nimplementation to QAT driver. The change includes separation\nof different QAT generations' asymmetric crypto data path\nimplementations and shrink the device capabilities declaration\ncode size.\n\nSigned-off-by: Kai Ji <kai.ji@intel.com>\n---\n drivers/common/qat/qat_qp.c   |   5 +-\n drivers/crypto/qat/qat_asym.c | 624 +++++++++++++++++-----------------\n drivers/crypto/qat/qat_asym.h |  63 +++-\n 3 files changed, 380 insertions(+), 312 deletions(-)",
    "diff": "diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex ed632b5ebe..c3265241a3 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -622,7 +622,7 @@ qat_enqueue_op_burst(void *qp,\n #ifdef BUILD_QAT_ASYM\n \t\t\tret = qat_asym_build_request(*ops, base_addr + tail,\n \t\t\t\ttmp_qp->op_cookies[tail >> queue->trailz],\n-\t\t\t\ttmp_qp->qat_dev_gen);\n+\t\t\t\tNULL, tmp_qp->qat_dev_gen);\n #endif\n \t\t}\n \t\tif (ret != 0) {\n@@ -850,7 +850,8 @@ qat_dequeue_op_burst(void *qp, void **ops,\n #ifdef BUILD_QAT_ASYM\n \t\telse if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC)\n \t\t\tqat_asym_process_response(ops, resp_msg,\n-\t\t\t\ttmp_qp->op_cookies[head >> rx_queue->trailz]);\n+\t\t\t\ttmp_qp->op_cookies[head >> rx_queue->trailz],\n+\t\t\t\tNULL);\n #endif\n \n \t\thead = adf_modulo(head + rx_queue->msg_size,\ndiff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c\nindex 09d8761c5f..3d7aecd7c0 100644\n--- a/drivers/crypto/qat/qat_asym.c\n+++ b/drivers/crypto/qat/qat_asym.c\n@@ -1,69 +1,119 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019 Intel Corporation\n+ * Copyright(c) 2019 - 2022 Intel Corporation\n  */\n \n #include <stdarg.h>\n \n-#include \"qat_asym.h\"\n+#include <cryptodev_pmd.h>\n+\n #include \"icp_qat_fw_pke.h\"\n #include \"icp_qat_fw.h\"\n #include \"qat_pke_functionality_arrays.h\"\n \n-#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))\n+#include \"qat_device.h\"\n \n-static int qat_asym_get_sz_and_func_id(const uint32_t arr[][2],\n-\t\tsize_t arr_sz, size_t *size, uint32_t *func_id)\n+#include \"qat_logs.h\"\n+#include \"qat_asym.h\"\n+\n+uint8_t qat_asym_driver_id;\n+\n+struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[QAT_N_GENS];\n+\n+int\n+qat_asym_session_configure(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_asym_xform *xform,\n+\t\tstruct rte_cryptodev_asym_session *sess,\n+\t\tstruct rte_mempool *mempool)\n {\n-\tsize_t i;\n+\tint err = 0;\n+\tvoid *sess_private_data;\n+\tstruct qat_asym_session *session;\n \n-\tfor (i = 0; i < arr_sz; i++) {\n-\t\tif (*size <= arr[i][0]) {\n-\t\t\t*size = arr[i][0];\n-\t\t\t*func_id = arr[i][1];\n-\t\t\treturn 0;\n+\tif (rte_mempool_get(mempool, &sess_private_data)) {\n+\t\tQAT_LOG(ERR,\n+\t\t\t\"Couldn't get object from session mempool\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tsession = sess_private_data;\n+\tif (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {\n+\t\tif (xform->modex.exponent.length == 0 ||\n+\t\t\t\txform->modex.modulus.length == 0) {\n+\t\t\tQAT_LOG(ERR, \"Invalid mod exp input parameter\");\n+\t\t\terr = -EINVAL;\n+\t\t\tgoto error;\n+\t\t}\n+\t} else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {\n+\t\tif (xform->modinv.modulus.length == 0) {\n+\t\t\tQAT_LOG(ERR, \"Invalid mod inv input parameter\");\n+\t\t\terr = -EINVAL;\n+\t\t\tgoto error;\n+\t\t}\n+\t} else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) {\n+\t\tif (xform->rsa.n.length == 0) {\n+\t\t\tQAT_LOG(ERR, \"Invalid rsa input parameter\");\n+\t\t\terr = -EINVAL;\n+\t\t\tgoto error;\n \t\t}\n+\t} else if (xform->xform_type >= RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END\n+\t\t\t|| xform->xform_type <= RTE_CRYPTO_ASYM_XFORM_NONE) {\n+\t\tQAT_LOG(ERR, \"Invalid asymmetric crypto xform\");\n+\t\terr = -EINVAL;\n+\t\tgoto error;\n+\t} else {\n+\t\tQAT_LOG(ERR, \"Asymmetric crypto xform not implemented\");\n+\t\terr = -EINVAL;\n+\t\tgoto error;\n \t}\n-\treturn -1;\n-}\n \n-static inline void qat_fill_req_tmpl(struct icp_qat_fw_pke_request *qat_req)\n-{\n-\tmemset(qat_req, 0, sizeof(*qat_req));\n-\tqat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;\n+\tsession->xform = xform;\n+\tqat_asym_build_req_tmpl(sess_private_data);\n+\tset_asym_session_private_data(sess, dev->driver_id,\n+\t\tsess_private_data);\n \n-\tqat_req->pke_hdr.hdr_flags =\n-\t\t\tICP_QAT_FW_COMN_HDR_FLAGS_BUILD\n-\t\t\t(ICP_QAT_FW_COMN_REQ_FLAG_SET);\n+\treturn 0;\n+error:\n+\trte_mempool_put(mempool, sess_private_data);\n+\treturn err;\n }\n \n-static inline void qat_asym_build_req_tmpl(void *sess_private_data)\n+unsigned int\n+qat_asym_session_get_private_size(\n+\t\tstruct rte_cryptodev *dev __rte_unused)\n {\n-\tstruct icp_qat_fw_pke_request *qat_req;\n-\tstruct qat_asym_session *session = sess_private_data;\n-\n-\tqat_req = &session->req_tmpl;\n-\tqat_fill_req_tmpl(qat_req);\n+\treturn RTE_ALIGN_CEIL(sizeof(struct qat_asym_session), 8);\n }\n \n-static size_t max_of(int n, ...)\n+void\n+qat_asym_session_clear(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_asym_session *sess)\n {\n-\tva_list args;\n-\tsize_t len = 0, num;\n-\tint i;\n+\tuint8_t index = dev->driver_id;\n+\tvoid *sess_priv = get_asym_session_private_data(sess, index);\n+\tstruct qat_asym_session *s = (struct qat_asym_session *)sess_priv;\n \n-\tva_start(args, n);\n-\tlen = va_arg(args, size_t);\n+\tif (sess_priv) {\n+\t\tmemset(s, 0, qat_asym_session_get_private_size(dev));\n+\t\tstruct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);\n \n-\tfor (i = 0; i < n - 1; i++) {\n-\t\tnum = va_arg(args, size_t);\n-\t\tif (num > len)\n-\t\t\tlen = num;\n+\t\tset_asym_session_private_data(sess, index, NULL);\n+\t\trte_mempool_put(sess_mp, sess_priv);\n \t}\n-\tva_end(args);\n-\n-\treturn len;\n }\n \n+/* An rte_driver is needed in the registration of both the device and the driver\n+ * with cryptodev.\n+ * The actual qat pci's rte_driver can't be used as its name represents\n+ * the whole pci device with all services. Think of this as a holder for a name\n+ * for the crypto part of the pci device.\n+ */\n+static const char qat_asym_drv_name[] = RTE_STR(CRYPTODEV_NAME_QAT_ASYM_PMD);\n+static const struct rte_driver cryptodev_qat_asym_driver = {\n+\t.name = qat_asym_drv_name,\n+\t.alias = qat_asym_drv_name\n+};\n+\n+\n static void qat_clear_arrays(struct qat_asym_op_cookie *cookie,\n \t\tint in_count, int out_count, int alg_size)\n {\n@@ -106,7 +156,230 @@ static void qat_clear_arrays_by_alg(struct qat_asym_op_cookie *cookie,\n \t}\n }\n \n-static int qat_asym_check_nonzero(rte_crypto_param n)\n+static void qat_asym_collect_response(struct rte_crypto_op *rx_op,\n+\t\tstruct qat_asym_op_cookie *cookie,\n+\t\tstruct rte_crypto_asym_xform *xform)\n+{\n+\tsize_t alg_size, alg_size_in_bytes = 0;\n+\tstruct rte_crypto_asym_op *asym_op = rx_op->asym;\n+\n+\tif (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {\n+\t\trte_crypto_param n = xform->modex.modulus;\n+\n+\t\talg_size = cookie->alg_size;\n+\t\talg_size_in_bytes = alg_size >> 3;\n+\t\tuint8_t *modexp_result = asym_op->modex.result.data;\n+\n+\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) {\n+\t\t\trte_memcpy(modexp_result +\n+\t\t\t\t(asym_op->modex.result.length -\n+\t\t\t\t\tn.length),\n+\t\t\t\tcookie->output_array[0] + alg_size_in_bytes\n+\t\t\t\t- n.length, n.length\n+\t\t\t\t);\n+\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"ModExp result\",\n+\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\talg_size_in_bytes);\n+\n+#endif\n+\t\t}\n+\t} else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {\n+\t\trte_crypto_param n = xform->modinv.modulus;\n+\n+\t\talg_size = cookie->alg_size;\n+\t\talg_size_in_bytes = alg_size >> 3;\n+\t\tuint8_t *modinv_result = asym_op->modinv.result.data;\n+\n+\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) {\n+\t\t\trte_memcpy(modinv_result +\n+\t\t\t\t(asym_op->modinv.result.length\n+\t\t\t\t- n.length),\n+\t\t\t\tcookie->output_array[0] + alg_size_in_bytes\n+\t\t\t\t- n.length, n.length);\n+\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"ModInv result\",\n+\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\talg_size_in_bytes);\n+#endif\n+\t\t}\n+\t} else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) {\n+\n+\t\talg_size = cookie->alg_size;\n+\t\talg_size_in_bytes = alg_size >> 3;\n+\t\tif (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT ||\n+\t\t\t\tasym_op->rsa.op_type ==\n+\t\t\t\t\tRTE_CRYPTO_ASYM_OP_VERIFY) {\n+\t\t\tif (asym_op->rsa.op_type ==\n+\t\t\t\t\tRTE_CRYPTO_ASYM_OP_ENCRYPT) {\n+\t\t\t\tuint8_t *rsa_result = asym_op->rsa.cipher.data;\n+\n+\t\t\t\trte_memcpy(rsa_result,\n+\t\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\t\talg_size_in_bytes);\n+\t\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\t\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"RSA Encrypted data\",\n+\t\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\t\talg_size_in_bytes);\n+#endif\n+\t\t\t} else if (asym_op->rsa.op_type ==\n+\t\t\t\t\tRTE_CRYPTO_ASYM_OP_VERIFY) {\n+\t\t\t\tuint8_t *rsa_result = asym_op->rsa.cipher.data;\n+\n+\t\t\t\tswitch (asym_op->rsa.pad) {\n+\t\t\t\tcase RTE_CRYPTO_RSA_PADDING_NONE:\n+\t\t\t\t\trte_memcpy(rsa_result,\n+\t\t\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\t\t\talg_size_in_bytes);\n+\t\t\t\t\trx_op->status =\n+\t\t\t\t\t\tRTE_CRYPTO_OP_STATUS_SUCCESS;\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\t\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"RSA Signature\",\n+\t\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\t\talg_size_in_bytes);\n+#endif\n+\t\t\t\t\tbreak;\n+\t\t\t\tdefault:\n+\t\t\t\t\tQAT_LOG(ERR, \"Padding not supported\");\n+\t\t\t\t\trx_op->status =\n+\t\t\t\t\t\tRTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else {\n+\t\t\tif (asym_op->rsa.op_type ==\n+\t\t\t\t\tRTE_CRYPTO_ASYM_OP_DECRYPT) {\n+\t\t\t\tuint8_t *rsa_result = asym_op->rsa.message.data;\n+\n+\t\t\t\tswitch (asym_op->rsa.pad) {\n+\t\t\t\tcase RTE_CRYPTO_RSA_PADDING_NONE:\n+\t\t\t\t\trte_memcpy(rsa_result,\n+\t\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\t\talg_size_in_bytes);\n+\t\t\t\t\trx_op->status =\n+\t\t\t\t\t\tRTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t\t\t\tbreak;\n+\t\t\t\tdefault:\n+\t\t\t\t\tQAT_LOG(ERR, \"Padding not supported\");\n+\t\t\t\t\trx_op->status =\n+\t\t\t\t\t\tRTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\t\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"RSA Decrypted Message\",\n+\t\t\t\t\t\trsa_result, alg_size_in_bytes);\n+#endif\n+\t\t\t} else if (asym_op->rsa.op_type ==\n+\t\t\t\t\tRTE_CRYPTO_ASYM_OP_SIGN) {\n+\t\t\t\tuint8_t *rsa_result = asym_op->rsa.sign.data;\n+\n+\t\t\t\trte_memcpy(rsa_result,\n+\t\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\t\talg_size_in_bytes);\n+\t\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\t\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"RSA Signature\",\n+\t\t\t\t\t\tcookie->output_array[0],\n+\t\t\t\t\t\talg_size_in_bytes);\n+#endif\n+\t\t\t}\n+\t\t}\n+\t}\n+\tqat_clear_arrays_by_alg(cookie, xform, alg_size_in_bytes);\n+}\n+\n+int\n+qat_asym_process_response(void __rte_unused * *op, uint8_t *resp,\n+\t\tvoid *op_cookie, __rte_unused uint64_t *dequeue_err_count)\n+{\n+\tstruct qat_asym_session *ctx;\n+\tstruct icp_qat_fw_pke_resp *resp_msg =\n+\t\t\t(struct icp_qat_fw_pke_resp *)resp;\n+\tstruct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)\n+\t\t\t(resp_msg->opaque);\n+\tstruct qat_asym_op_cookie *cookie = op_cookie;\n+\n+\tif (cookie->error) {\n+\t\tcookie->error = 0;\n+\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED)\n+\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\tQAT_DP_LOG(ERR, \"Cookie status returned error\");\n+\t} else {\n+\t\tif (ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(\n+\t\t\tresp_msg->pke_resp_hdr.resp_status.pke_resp_flags)) {\n+\t\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED)\n+\t\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\tQAT_DP_LOG(ERR, \"Asymmetric response status\"\n+\t\t\t\t\t\" returned error\");\n+\t\t}\n+\t\tif (resp_msg->pke_resp_hdr.resp_status.comn_err_code) {\n+\t\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED)\n+\t\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\tQAT_DP_LOG(ERR, \"Asymmetric common status\"\n+\t\t\t\t\t\" returned error\");\n+\t\t}\n+\t}\n+\n+\tif (rx_op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n+\t\tctx = (struct qat_asym_session *)get_asym_session_private_data(\n+\t\t\trx_op->asym->session, qat_asym_driver_id);\n+\t\tqat_asym_collect_response(rx_op, cookie, ctx->xform);\n+\t} else if (rx_op->sess_type == RTE_CRYPTO_OP_SESSIONLESS) {\n+\t\tqat_asym_collect_response(rx_op, cookie, rx_op->asym->xform);\n+\t}\n+\t*op = rx_op;\n+\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tQAT_DP_HEXDUMP_LOG(DEBUG, \"resp_msg:\", resp_msg,\n+\t\t\tsizeof(struct icp_qat_fw_pke_resp));\n+#endif\n+\n+\treturn 1;\n+}\n+\n+#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))\n+\n+static int\n+qat_asym_get_sz_and_func_id(const uint32_t arr[][2],\n+\t\tsize_t arr_sz, size_t *size, uint32_t *func_id)\n+{\n+\tsize_t i;\n+\n+\tfor (i = 0; i < arr_sz; i++) {\n+\t\tif (*size <= arr[i][0]) {\n+\t\t\t*size = arr[i][0];\n+\t\t\t*func_id = arr[i][1];\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\treturn -1;\n+}\n+\n+static size_t\n+max_of(int n, ...)\n+{\n+\tva_list args;\n+\tsize_t len = 0, num;\n+\tint i;\n+\n+\tva_start(args, n);\n+\tlen = va_arg(args, size_t);\n+\n+\tfor (i = 0; i < n - 1; i++) {\n+\t\tnum = va_arg(args, size_t);\n+\t\tif (num > len)\n+\t\t\tlen = num;\n+\t}\n+\tva_end(args);\n+\n+\treturn len;\n+}\n+\n+static int\n+qat_asym_check_nonzero(rte_crypto_param n)\n {\n \tif (n.length < 8) {\n \t\t/* Not a case for any cryptographic function except for DH\n@@ -475,10 +748,9 @@ qat_asym_fill_arrays(struct rte_crypto_asym_op *asym_op,\n }\n \n int\n-qat_asym_build_request(void *in_op,\n-\t\t\tuint8_t *out_msg,\n-\t\t\tvoid *op_cookie,\n-\t\t\t__rte_unused enum qat_device_gen qat_dev_gen)\n+qat_asym_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,\n+\t\t__rte_unused uint64_t *opaque,\n+\t\t__rte_unused enum qat_device_gen dev_gen)\n {\n \tstruct qat_asym_session *ctx;\n \tstruct rte_crypto_op *op = (struct rte_crypto_op *)in_op;\n@@ -545,263 +817,7 @@ qat_asym_build_request(void *in_op,\n \treturn 0;\n }\n \n-static void qat_asym_collect_response(struct rte_crypto_op *rx_op,\n-\t\tstruct qat_asym_op_cookie *cookie,\n-\t\tstruct rte_crypto_asym_xform *xform)\n-{\n-\tsize_t alg_size, alg_size_in_bytes = 0;\n-\tstruct rte_crypto_asym_op *asym_op = rx_op->asym;\n-\n-\tif (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {\n-\t\trte_crypto_param n = xform->modex.modulus;\n-\n-\t\talg_size = cookie->alg_size;\n-\t\talg_size_in_bytes = alg_size >> 3;\n-\t\tuint8_t *modexp_result = asym_op->modex.result.data;\n-\n-\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) {\n-\t\t\trte_memcpy(modexp_result +\n-\t\t\t\t(asym_op->modex.result.length -\n-\t\t\t\t\tn.length),\n-\t\t\t\tcookie->output_array[0] + alg_size_in_bytes\n-\t\t\t\t- n.length, n.length\n-\t\t\t\t);\n-\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"ModExp result\",\n-\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\talg_size_in_bytes);\n-\n-#endif\n-\t\t}\n-\t} else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {\n-\t\trte_crypto_param n = xform->modinv.modulus;\n-\n-\t\talg_size = cookie->alg_size;\n-\t\talg_size_in_bytes = alg_size >> 3;\n-\t\tuint8_t *modinv_result = asym_op->modinv.result.data;\n-\n-\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) {\n-\t\t\trte_memcpy(modinv_result + (asym_op->modinv.result.length\n-\t\t\t\t- n.length),\n-\t\t\t\tcookie->output_array[0] + alg_size_in_bytes\n-\t\t\t\t- n.length, n.length);\n-\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"ModInv result\",\n-\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\talg_size_in_bytes);\n-#endif\n-\t\t}\n-\t} else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) {\n-\n-\t\talg_size = cookie->alg_size;\n-\t\talg_size_in_bytes = alg_size >> 3;\n-\t\tif (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT ||\n-\t\t\t\tasym_op->rsa.op_type ==\n-\t\t\t\t\tRTE_CRYPTO_ASYM_OP_VERIFY) {\n-\t\t\tif (asym_op->rsa.op_type ==\n-\t\t\t\t\tRTE_CRYPTO_ASYM_OP_ENCRYPT) {\n-\t\t\t\tuint8_t *rsa_result = asym_op->rsa.cipher.data;\n-\n-\t\t\t\trte_memcpy(rsa_result,\n-\t\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\t\talg_size_in_bytes);\n-\t\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\t\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"RSA Encrypted data\",\n-\t\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\t\talg_size_in_bytes);\n-#endif\n-\t\t\t} else if (asym_op->rsa.op_type ==\n-\t\t\t\t\tRTE_CRYPTO_ASYM_OP_VERIFY) {\n-\t\t\t\tuint8_t *rsa_result = asym_op->rsa.cipher.data;\n-\n-\t\t\t\tswitch (asym_op->rsa.pad) {\n-\t\t\t\tcase RTE_CRYPTO_RSA_PADDING_NONE:\n-\t\t\t\t\trte_memcpy(rsa_result,\n-\t\t\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\t\t\talg_size_in_bytes);\n-\t\t\t\t\trx_op->status =\n-\t\t\t\t\t\tRTE_CRYPTO_OP_STATUS_SUCCESS;\n-#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\t\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"RSA Signature\",\n-\t\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\t\talg_size_in_bytes);\n-#endif\n-\t\t\t\t\tbreak;\n-\t\t\t\tdefault:\n-\t\t\t\t\tQAT_LOG(ERR, \"Padding not supported\");\n-\t\t\t\t\trx_op->status =\n-\t\t\t\t\t\tRTE_CRYPTO_OP_STATUS_ERROR;\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t} else {\n-\t\t\tif (asym_op->rsa.op_type ==\n-\t\t\t\t\tRTE_CRYPTO_ASYM_OP_DECRYPT) {\n-\t\t\t\tuint8_t *rsa_result = asym_op->rsa.message.data;\n-\n-\t\t\t\tswitch (asym_op->rsa.pad) {\n-\t\t\t\tcase RTE_CRYPTO_RSA_PADDING_NONE:\n-\t\t\t\t\trte_memcpy(rsa_result,\n-\t\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\t\talg_size_in_bytes);\n-\t\t\t\t\trx_op->status =\n-\t\t\t\t\t\tRTE_CRYPTO_OP_STATUS_SUCCESS;\n-\t\t\t\t\tbreak;\n-\t\t\t\tdefault:\n-\t\t\t\t\tQAT_LOG(ERR, \"Padding not supported\");\n-\t\t\t\t\trx_op->status =\n-\t\t\t\t\t\tRTE_CRYPTO_OP_STATUS_ERROR;\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\t\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"RSA Decrypted Message\",\n-\t\t\t\t\t\trsa_result, alg_size_in_bytes);\n-#endif\n-\t\t\t} else if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_SIGN) {\n-\t\t\t\tuint8_t *rsa_result = asym_op->rsa.sign.data;\n-\n-\t\t\t\trte_memcpy(rsa_result,\n-\t\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\t\talg_size_in_bytes);\n-\t\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\t\t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"RSA Signature\",\n-\t\t\t\t\t\tcookie->output_array[0],\n-\t\t\t\t\t\talg_size_in_bytes);\n-#endif\n-\t\t\t}\n-\t\t}\n-\t}\n-\tqat_clear_arrays_by_alg(cookie, xform, alg_size_in_bytes);\n-}\n-\n-void\n-qat_asym_process_response(void **op, uint8_t *resp,\n-\t\tvoid *op_cookie)\n-{\n-\tstruct qat_asym_session *ctx;\n-\tstruct icp_qat_fw_pke_resp *resp_msg =\n-\t\t\t(struct icp_qat_fw_pke_resp *)resp;\n-\tstruct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)\n-\t\t\t(resp_msg->opaque);\n-\tstruct qat_asym_op_cookie *cookie = op_cookie;\n-\n-\tif (cookie->error) {\n-\t\tcookie->error = 0;\n-\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED)\n-\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n-\t\tQAT_DP_LOG(ERR, \"Cookie status returned error\");\n-\t} else {\n-\t\tif (ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(\n-\t\t\tresp_msg->pke_resp_hdr.resp_status.pke_resp_flags)) {\n-\t\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED)\n-\t\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n-\t\t\tQAT_DP_LOG(ERR, \"Asymmetric response status\"\n-\t\t\t\t\t\" returned error\");\n-\t\t}\n-\t\tif (resp_msg->pke_resp_hdr.resp_status.comn_err_code) {\n-\t\t\tif (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED)\n-\t\t\t\trx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n-\t\t\tQAT_DP_LOG(ERR, \"Asymmetric common status\"\n-\t\t\t\t\t\" returned error\");\n-\t\t}\n-\t}\n-\n-\tif (rx_op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n-\t\tctx = (struct qat_asym_session *)get_asym_session_private_data(\n-\t\t\trx_op->asym->session, qat_asym_driver_id);\n-\t\tqat_asym_collect_response(rx_op, cookie, ctx->xform);\n-\t} else if (rx_op->sess_type == RTE_CRYPTO_OP_SESSIONLESS) {\n-\t\tqat_asym_collect_response(rx_op, cookie, rx_op->asym->xform);\n-\t}\n-\t*op = rx_op;\n-\n-#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\tQAT_DP_HEXDUMP_LOG(DEBUG, \"resp_msg:\", resp_msg,\n-\t\t\tsizeof(struct icp_qat_fw_pke_resp));\n-#endif\n-}\n-\n-int\n-qat_asym_session_configure(struct rte_cryptodev *dev,\n-\t\tstruct rte_crypto_asym_xform *xform,\n-\t\tstruct rte_cryptodev_asym_session *sess,\n-\t\tstruct rte_mempool *mempool)\n-{\n-\tint err = 0;\n-\tvoid *sess_private_data;\n-\tstruct qat_asym_session *session;\n-\n-\tif (rte_mempool_get(mempool, &sess_private_data)) {\n-\t\tQAT_LOG(ERR,\n-\t\t\t\"Couldn't get object from session mempool\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tsession = sess_private_data;\n-\tif (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {\n-\t\tif (xform->modex.exponent.length == 0 ||\n-\t\t\t\txform->modex.modulus.length == 0) {\n-\t\t\tQAT_LOG(ERR, \"Invalid mod exp input parameter\");\n-\t\t\terr = -EINVAL;\n-\t\t\tgoto error;\n-\t\t}\n-\t} else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {\n-\t\tif (xform->modinv.modulus.length == 0) {\n-\t\t\tQAT_LOG(ERR, \"Invalid mod inv input parameter\");\n-\t\t\terr = -EINVAL;\n-\t\t\tgoto error;\n-\t\t}\n-\t} else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) {\n-\t\tif (xform->rsa.n.length == 0) {\n-\t\t\tQAT_LOG(ERR, \"Invalid rsa input parameter\");\n-\t\t\terr = -EINVAL;\n-\t\t\tgoto error;\n-\t\t}\n-\t} else if (xform->xform_type >= RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END\n-\t\t\t|| xform->xform_type <= RTE_CRYPTO_ASYM_XFORM_NONE) {\n-\t\tQAT_LOG(ERR, \"Invalid asymmetric crypto xform\");\n-\t\terr = -EINVAL;\n-\t\tgoto error;\n-\t} else {\n-\t\tQAT_LOG(ERR, \"Asymmetric crypto xform not implemented\");\n-\t\terr = -EINVAL;\n-\t\tgoto error;\n-\t}\n-\n-\tsession->xform = xform;\n-\tqat_asym_build_req_tmpl(sess_private_data);\n-\tset_asym_session_private_data(sess, dev->driver_id,\n-\t\tsess_private_data);\n-\n-\treturn 0;\n-error:\n-\trte_mempool_put(mempool, sess_private_data);\n-\treturn err;\n-}\n-\n-unsigned int qat_asym_session_get_private_size(\n-\t\tstruct rte_cryptodev *dev __rte_unused)\n-{\n-\treturn RTE_ALIGN_CEIL(sizeof(struct qat_asym_session), 8);\n-}\n-\n-void\n-qat_asym_session_clear(struct rte_cryptodev *dev,\n-\t\tstruct rte_cryptodev_asym_session *sess)\n-{\n-\tuint8_t index = dev->driver_id;\n-\tvoid *sess_priv = get_asym_session_private_data(sess, index);\n-\tstruct qat_asym_session *s = (struct qat_asym_session *)sess_priv;\n-\n-\tif (sess_priv) {\n-\t\tmemset(s, 0, qat_asym_session_get_private_size(dev));\n-\t\tstruct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);\n-\n-\t\tset_asym_session_private_data(sess, index, NULL);\n-\t\trte_mempool_put(sess_mp, sess_priv);\n-\t}\n-}\n+static struct cryptodev_driver qat_crypto_drv;\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,\n+\t\tcryptodev_qat_asym_driver,\n+\t\tqat_asym_driver_id);\ndiff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h\nindex 308b6b2e0b..aba49d57cb 100644\n--- a/drivers/crypto/qat/qat_asym.h\n+++ b/drivers/crypto/qat/qat_asym.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019 Intel Corporation\n+ * Copyright(c) 2022 Intel Corporation\n  */\n \n #ifndef _QAT_ASYM_H_\n@@ -8,10 +8,13 @@\n #include <cryptodev_pmd.h>\n #include <rte_crypto_asym.h>\n #include \"icp_qat_fw_pke.h\"\n-#include \"qat_common.h\"\n-#include \"qat_asym_pmd.h\"\n+#include \"qat_device.h\"\n+#include \"qat_crypto.h\"\n #include \"icp_qat_fw.h\"\n \n+/** Intel(R) QAT Asymmetric Crypto PMD driver name */\n+#define CRYPTODEV_NAME_QAT_ASYM_PMD\tcrypto_qat_asym\n+\n typedef uint64_t large_int_ptr;\n #define MAX_PKE_PARAMS\t8\n #define QAT_PKE_MAX_LN_SIZE 512\n@@ -26,6 +29,28 @@ typedef uint64_t large_int_ptr;\n #define QAT_ASYM_RSA_NUM_OUT_PARAMS\t\t1\n #define QAT_ASYM_RSA_QT_NUM_IN_PARAMS\t\t6\n \n+/**\n+ * helper function to add an asym capability\n+ * <name> <op type> <modlen (min, max, increment)>\n+ **/\n+#define QAT_ASYM_CAP(n, o, l, r, i)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\t\t\t\\\n+\t\t{.asym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_capa = {\t\t\t\t\t\\\n+\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_##n,\\\n+\t\t\t\t.op_types = o,\t\t\t\t\\\n+\t\t\t\t{\t\t\t\t\t\\\n+\t\t\t\t.modlen = {\t\t\t\t\\\n+\t\t\t\t.min = l,\t\t\t\t\\\n+\t\t\t\t.max = r,\t\t\t\t\\\n+\t\t\t\t.increment = i\t\t\t\t\\\n+\t\t\t\t}, }\t\t\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t}\n+\n struct qat_asym_op_cookie {\n \tsize_t alg_size;\n \tuint64_t error;\n@@ -45,6 +70,27 @@ struct qat_asym_session {\n \tstruct rte_crypto_asym_xform *xform;\n };\n \n+static inline void\n+qat_fill_req_tmpl(struct icp_qat_fw_pke_request *qat_req)\n+{\n+\tmemset(qat_req, 0, sizeof(*qat_req));\n+\tqat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;\n+\n+\tqat_req->pke_hdr.hdr_flags =\n+\t\t\tICP_QAT_FW_COMN_HDR_FLAGS_BUILD\n+\t\t\t(ICP_QAT_FW_COMN_REQ_FLAG_SET);\n+}\n+\n+static inline void\n+qat_asym_build_req_tmpl(void *sess_private_data)\n+{\n+\tstruct icp_qat_fw_pke_request *qat_req;\n+\tstruct qat_asym_session *session = sess_private_data;\n+\n+\tqat_req = &session->req_tmpl;\n+\tqat_fill_req_tmpl(qat_req);\n+}\n+\n int\n qat_asym_session_configure(struct rte_cryptodev *dev,\n \t\tstruct rte_crypto_asym_xform *xform,\n@@ -76,7 +122,9 @@ qat_asym_session_clear(struct rte_cryptodev *dev,\n  */\n int\n qat_asym_build_request(void *in_op, uint8_t *out_msg,\n-\t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen);\n+\t\tvoid *op_cookie,\n+\t\t__rte_unused uint64_t *opaque,\n+\t\tenum qat_device_gen qat_dev_gen);\n \n /*\n  * Process PKE response received from outgoing queue of QAT\n@@ -88,8 +136,11 @@ qat_asym_build_request(void *in_op, uint8_t *out_msg,\n  * @param\top_cookie\tCookie pointer that holds private metadata\n  *\n  */\n+int\n+qat_asym_process_response(void __rte_unused * *op, uint8_t *resp,\n+\t\tvoid *op_cookie, __rte_unused uint64_t *dequeue_err_count);\n+\n void\n-qat_asym_process_response(void __rte_unused **op, uint8_t *resp,\n-\t\tvoid *op_cookie);\n+qat_asym_init_op_cookie(void *cookie);\n \n #endif /* _QAT_ASYM_H_ */\n",
    "prefixes": [
        "v7",
        "05/10"
    ]
}