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GET /api/patches/107018/?format=api
{ "id": 107018, "url": "http://patches.dpdk.org/api/patches/107018/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220208101129.69173-4-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220208101129.69173-4-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220208101129.69173-4-jiawenwu@trustnetic.com", "date": "2022-02-08T10:11:23", "name": "[3/9] net/ngbe: fix Tx pending", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "4a3d501040ebbbaa4e81177efb956b4176fd4856", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220208101129.69173-4-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 21520, "url": "http://patches.dpdk.org/api/series/21520/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21520", "date": "2022-02-08T10:11:20", "name": "Wangxun fixes and supports", "version": 1, "mbox": "http://patches.dpdk.org/series/21520/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/107018/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/107018/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9FC83A04AD;\n\tTue, 8 Feb 2022 11:05:54 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7AF5B41183;\n\tTue, 8 Feb 2022 11:05:22 +0100 (CET)", "from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166])\n by mails.dpdk.org (Postfix) with ESMTP id 20C1741154\n for <dev@dpdk.org>; Tue, 8 Feb 2022 11:05:17 +0100 (CET)", "from wxdbg.localdomain.com (unknown [183.129.236.74])\n by bizesmtp.qq.com (ESMTP) with\n id ; Tue, 08 Feb 2022 18:05:02 +0800 (CST)" ], "X-QQ-mid": "bizesmtp46t1644314703ts763cbv", "X-QQ-SSF": "01400000002000F0L000B00A0000000", "X-QQ-FEAT": "Lg5IqoGaTUjXFxakUhb4TI2M/tbcndf2cbswOaK0VLXFWvEe6pLU286jWlQoi\n FEp6YZu6kTAbE7rhVfcJHnMPE7OciKeaXHaa3w5ge15oG2HLYeYqqueVE22Q/+dcnF9c6X6\n 030SiJtCebSl8OROqkUCEBou7EfrTU1uA5bAhcaKBXva7sYJ9ruW5MjKinbwr/3JA7UaVK9\n qgwe/I24/Zzei3BmqaOQgz7MemhdJ3aggSn/as0s7I/HIf3pnTeefVZmQRKhXb29UdLl/jJ\n xX4fhwvyX75Ek+/E7IveuA++R6Jgk3nSwGSxq8r+yWtR5k9f8bAyyGDIofStRc/wOtGpL6f\n cUXpyzGNL99jOSd0oD1AWf3GA0IxvzGNuiAACQ2", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>,\n\tstable@dpdk.org", "Subject": "[PATCH 3/9] net/ngbe: fix Tx pending", "Date": "Tue, 8 Feb 2022 18:11:23 +0800", "Message-Id": "<20220208101129.69173-4-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220208101129.69173-1-jiawenwu@trustnetic.com>", "References": "<20220208101129.69173-1-jiawenwu@trustnetic.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign2", "X-QQ-Bgrelay": "1", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add commands requesting firmware to enable or disable PCIe bus master.\nDisable PCIe master access to clear BME when stop hardware, and verify\nthere are no pending requests.\n\nFixes: 78710873c2f3 (\"net/ngbe: add HW initialization\")\nCc: stable@dpdk.org\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/ngbe/base/ngbe_hw.c | 76 +++++++++++++++++++++++++++----\n drivers/net/ngbe/base/ngbe_hw.h | 1 +\n drivers/net/ngbe/base/ngbe_mng.c | 57 +++++++++++++++++++++++\n drivers/net/ngbe/base/ngbe_mng.h | 21 +++++++++\n drivers/net/ngbe/base/ngbe_regs.h | 3 ++\n drivers/net/ngbe/base/ngbe_type.h | 3 ++\n drivers/net/ngbe/ngbe_ethdev.c | 7 ++-\n 7 files changed, 158 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c\nindex 0b22ea0fb3..782fd71d29 100644\n--- a/drivers/net/ngbe/base/ngbe_hw.c\n+++ b/drivers/net/ngbe/base/ngbe_hw.c\n@@ -350,8 +350,8 @@ void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)\n **/\n s32 ngbe_stop_hw(struct ngbe_hw *hw)\n {\n-\tu32 reg_val;\n \tu16 i;\n+\ts32 status = 0;\n \n \tDEBUGFUNC(\"ngbe_stop_hw\");\n \n@@ -372,16 +372,27 @@ s32 ngbe_stop_hw(struct ngbe_hw *hw)\n \twr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);\n \twr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);\n \n-\t/* Disable the transmit unit. Each queue must be disabled. */\n-\tfor (i = 0; i < hw->mac.max_tx_queues; i++)\n-\t\twr32(hw, NGBE_TXCFG(i), NGBE_TXCFG_FLUSH);\n+\twr32(hw, NGBE_BMECTL, 0x3);\n \n \t/* Disable the receive unit by stopping each queue */\n-\tfor (i = 0; i < hw->mac.max_rx_queues; i++) {\n-\t\treg_val = rd32(hw, NGBE_RXCFG(i));\n-\t\treg_val &= ~NGBE_RXCFG_ENA;\n-\t\twr32(hw, NGBE_RXCFG(i), reg_val);\n-\t}\n+\tfor (i = 0; i < hw->mac.max_rx_queues; i++)\n+\t\twr32(hw, NGBE_RXCFG(i), 0);\n+\n+\t/* flush all queues disables */\n+\tngbe_flush(hw);\n+\tmsec_delay(2);\n+\n+\t/*\n+\t * Prevent the PCI-E bus from hanging by disabling PCI-E master\n+\t * access and verify no pending requests\n+\t */\n+\tstatus = ngbe_set_pcie_master(hw, false);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Disable the transmit unit. Each queue must be disabled. */\n+\tfor (i = 0; i < hw->mac.max_tx_queues; i++)\n+\t\twr32(hw, NGBE_TXCFG(i), 0);\n \n \t/* flush all queues disables */\n \tngbe_flush(hw);\n@@ -1076,6 +1087,53 @@ void ngbe_fc_autoneg(struct ngbe_hw *hw)\n \t}\n }\n \n+/**\n+ * ngbe_set_pcie_master - Disable or Enable PCI-express master access\n+ * @hw: pointer to hardware structure\n+ *\n+ * Disables PCI-Express master access and verifies there are no pending\n+ * requests. NGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable\n+ * bit hasn't caused the master requests to be disabled, else 0\n+ * is returned signifying master requests disabled.\n+ **/\n+s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)\n+{\n+\ts32 status = 0;\n+\tu16 addr = 0x04;\n+\tu32 data, i;\n+\n+\tDEBUGFUNC(\"ngbe_set_pcie_master\");\n+\n+\tngbe_hic_pcie_read(hw, addr, &data, 4);\n+\tif (enable)\n+\t\tdata |= 0x04;\n+\telse\n+\t\tdata &= ~0x04;\n+\n+\tngbe_hic_pcie_write(hw, addr, &data, 4);\n+\n+\tif (enable)\n+\t\tgoto out;\n+\n+\t/* Exit if master requests are blocked */\n+\tif (!(rd32(hw, NGBE_BMEPEND)) ||\n+\t NGBE_REMOVED(hw->hw_addr))\n+\t\tgoto out;\n+\n+\t/* Poll for master request bit to clear */\n+\tfor (i = 0; i < NGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {\n+\t\tusec_delay(100);\n+\t\tif (!(rd32(hw, NGBE_BMEPEND)))\n+\t\t\tgoto out;\n+\t}\n+\n+\tDEBUGOUT(\"PCIe transaction pending bit also did not clear.\\n\");\n+\tstatus = NGBE_ERR_MASTER_REQUESTS_PENDING;\n+\n+out:\n+\treturn status;\n+}\n+\n /**\n * ngbe_acquire_swfw_sync - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\ndiff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h\nindex b32cf87ff4..7e0e23b195 100644\n--- a/drivers/net/ngbe/base/ngbe_hw.h\n+++ b/drivers/net/ngbe/base/ngbe_hw.h\n@@ -54,6 +54,7 @@ void ngbe_fc_autoneg(struct ngbe_hw *hw);\n s32 ngbe_validate_mac_addr(u8 *mac_addr);\n s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask);\n void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask);\n+s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable);\n \n s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq);\n s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq);\ndiff --git a/drivers/net/ngbe/base/ngbe_mng.c b/drivers/net/ngbe/base/ngbe_mng.c\nindex a3dd8093ce..68e06e2c24 100644\n--- a/drivers/net/ngbe/base/ngbe_mng.c\n+++ b/drivers/net/ngbe/base/ngbe_mng.c\n@@ -243,6 +243,63 @@ s32 ngbe_hic_sr_write(struct ngbe_hw *hw, u32 addr, u8 *buf, int len)\n \treturn err;\n }\n \n+s32 ngbe_hic_pcie_read(struct ngbe_hw *hw, u16 addr, u32 *buf, int len)\n+{\n+\tstruct ngbe_hic_read_pcie command;\n+\tu32 value = 0;\n+\tint err, i = 0;\n+\n+\tif (len > NGBE_PMMBX_DATA_SIZE)\n+\t\treturn NGBE_ERR_HOST_INTERFACE_COMMAND;\n+\n+\tmemset(&command, 0, sizeof(command));\n+\tcommand.hdr.cmd = FW_PCIE_READ_CMD;\n+\tcommand.hdr.buf_len = sizeof(command) - sizeof(command.hdr);\n+\tcommand.hdr.checksum = FW_DEFAULT_CHECKSUM;\n+\tcommand.lan_id = hw->bus.lan_id;\n+\tcommand.addr = addr;\n+\n+\terr = ngbe_host_interface_command(hw, (u32 *)&command,\n+\t\t\tsizeof(command), NGBE_HI_COMMAND_TIMEOUT, false);\n+\tif (err)\n+\t\treturn err;\n+\n+\twhile (i < (len >> 2)) {\n+\t\tvalue = rd32a(hw, NGBE_MNGMBX, FW_PCIE_BUSMASTER_OFFSET + i);\n+\t\t((u32 *)buf)[i] = value;\n+\t\ti++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_hic_pcie_write(struct ngbe_hw *hw, u16 addr, u32 *buf, int len)\n+{\n+\tstruct ngbe_hic_write_pcie command;\n+\tu32 value = 0;\n+\tint err, i = 0;\n+\n+\twhile (i < (len >> 2)) {\n+\t\tvalue = ((u32 *)buf)[i];\n+\t\ti++;\n+\t}\n+\n+\tmemset(&command, 0, sizeof(command));\n+\tcommand.hdr.cmd = FW_PCIE_WRITE_CMD;\n+\tcommand.hdr.buf_len = sizeof(command) - sizeof(command.hdr);\n+\tcommand.hdr.checksum = FW_DEFAULT_CHECKSUM;\n+\tcommand.lan_id = hw->bus.lan_id;\n+\tcommand.addr = addr;\n+\tcommand.data = value;\n+\n+\terr = ngbe_host_interface_command(hw, (u32 *)&command,\n+\t\t\tsizeof(command), NGBE_HI_COMMAND_TIMEOUT, false);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn 0;\n+}\n+\n s32 ngbe_hic_check_cap(struct ngbe_hw *hw)\n {\n \tstruct ngbe_hic_read_shadow_ram command;\ndiff --git a/drivers/net/ngbe/base/ngbe_mng.h b/drivers/net/ngbe/base/ngbe_mng.h\nindex e3d0309cbc..321338a051 100644\n--- a/drivers/net/ngbe/base/ngbe_mng.h\n+++ b/drivers/net/ngbe/base/ngbe_mng.h\n@@ -20,6 +20,9 @@\n #define FW_READ_SHADOW_RAM_LEN 0x6\n #define FW_WRITE_SHADOW_RAM_CMD 0x33\n #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */\n+#define FW_PCIE_READ_CMD\t\t0xEC\n+#define FW_PCIE_WRITE_CMD\t\t0xED\n+#define FW_PCIE_BUSMASTER_OFFSET 2\n #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */\n #define FW_NVM_DATA_OFFSET 3\n #define FW_EEPROM_CHECK_STATUS\t\t0xE9\n@@ -76,8 +79,26 @@ struct ngbe_hic_write_shadow_ram {\n \tu16 pad3;\n };\n \n+struct ngbe_hic_read_pcie {\n+\tstruct ngbe_hic_hdr hdr;\n+\tu8 lan_id;\n+\tu8 rsvd;\n+\tu16 addr;\n+\tu32 data;\n+};\n+\n+struct ngbe_hic_write_pcie {\n+\tstruct ngbe_hic_hdr hdr;\n+\tu8 lan_id;\n+\tu8 rsvd;\n+\tu16 addr;\n+\tu32 data;\n+};\n+\n s32 ngbe_hic_sr_read(struct ngbe_hw *hw, u32 addr, u8 *buf, int len);\n s32 ngbe_hic_sr_write(struct ngbe_hw *hw, u32 addr, u8 *buf, int len);\n+s32 ngbe_hic_pcie_read(struct ngbe_hw *hw, u16 addr, u32 *buf, int len);\n+s32 ngbe_hic_pcie_write(struct ngbe_hw *hw, u16 addr, u32 *buf, int len);\n \n s32 ngbe_hic_check_cap(struct ngbe_hw *hw);\n #endif /* _NGBE_MNG_H_ */\ndiff --git a/drivers/net/ngbe/base/ngbe_regs.h b/drivers/net/ngbe/base/ngbe_regs.h\nindex 872b008c46..e84bfdf88a 100644\n--- a/drivers/net/ngbe/base/ngbe_regs.h\n+++ b/drivers/net/ngbe/base/ngbe_regs.h\n@@ -866,6 +866,9 @@ enum ngbe_5tuple_protocol {\n * PF(Physical Function) Registers\n ******************************************************************************/\n /* Interrupt */\n+#define NGBE_BMECTL\t\t0x012020\n+#define NGBE_BMECTL_VFDRP\tMS(1, 0x1)\n+#define NGBE_BMECTL_PFDRP\tMS(0, 0x1)\n #define NGBE_ICRMISC\t\t0x000100\n #define NGBE_ICRMISC_MASK\tMS(8, 0xFFFFFF)\n #define NGBE_ICRMISC_RST\tMS(10, 0x1) /* device reset event */\ndiff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h\nindex 269e087d50..4c995e7397 100644\n--- a/drivers/net/ngbe/base/ngbe_type.h\n+++ b/drivers/net/ngbe/base/ngbe_type.h\n@@ -17,6 +17,9 @@\n #define NGBE_MAX_QP (8)\n #define NGBE_MAX_UTA 128\n \n+#define NGBE_PCI_MASTER_DISABLE_TIMEOUT\t800\n+\n+\n #define NGBE_ALIGN\t\t128 /* as intel did */\n #define NGBE_ISB_SIZE\t\t16\n \ndiff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c\nindex 8e31234442..30c9e68579 100644\n--- a/drivers/net/ngbe/ngbe_ethdev.c\n+++ b/drivers/net/ngbe/ngbe_ethdev.c\n@@ -950,7 +950,6 @@ ngbe_dev_start(struct rte_eth_dev *dev)\n \n \t/* stop adapter */\n \thw->adapter_stopped = 0;\n-\tngbe_stop_hw(hw);\n \n \t/* reinitialize adapter, this calls reset and start */\n \thw->nb_rx_queues = dev->data->nb_rx_queues;\n@@ -961,6 +960,8 @@ ngbe_dev_start(struct rte_eth_dev *dev)\n \thw->mac.start_hw(hw);\n \thw->mac.get_link_status = true;\n \n+\tngbe_set_pcie_master(hw, true);\n+\n \t/* configure PF module if SRIOV enabled */\n \tngbe_pf_host_configure(dev);\n \n@@ -1174,6 +1175,8 @@ ngbe_dev_stop(struct rte_eth_dev *dev)\n \trte_intr_efd_disable(intr_handle);\n \trte_intr_vec_list_free(intr_handle);\n \n+\tngbe_set_pcie_master(hw, true);\n+\n \tadapter->rss_reta_updated = 0;\n \n \thw->adapter_stopped = true;\n@@ -1202,6 +1205,8 @@ ngbe_dev_close(struct rte_eth_dev *dev)\n \n \tngbe_dev_free_queues(dev);\n \n+\tngbe_set_pcie_master(hw, false);\n+\n \t/* reprogram the RAR[0] in case user changed it. */\n \tngbe_set_rar(hw, 0, hw->mac.addr, 0, true);\n \n", "prefixes": [ "3/9" ] }