Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/10697/?format=api
{ "id": 10697, "url": "http://patches.dpdk.org/api/patches/10697/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1455880025-6912-18-git-send-email-xiao.w.wang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1455880025-6912-18-git-send-email-xiao.w.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1455880025-6912-18-git-send-email-xiao.w.wang@intel.com", "date": "2016-02-19T11:07:04", "name": "[dpdk-dev,v3,17/18] fm10k/base: minor cleanups", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6666e72d7d97842c06ad2c21437a7a2c4f8d99ca", "submitter": { "id": 281, "url": "http://patches.dpdk.org/api/people/281/?format=api", "name": "Xiao Wang", "email": "xiao.w.wang@intel.com" }, "delegate": { "id": 10, "url": "http://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1455880025-6912-18-git-send-email-xiao.w.wang@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/10697/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/10697/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 27075C5AC;\n\tFri, 19 Feb 2016 12:08:56 +0100 (CET)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id A6C41C59E\n\tfor <dev@dpdk.org>; Fri, 19 Feb 2016 12:08:53 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga103.fm.intel.com with ESMTP; 19 Feb 2016 03:07:50 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 19 Feb 2016 03:07:50 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id u1JB7liJ028298;\n\tFri, 19 Feb 2016 19:07:47 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid u1JB7img007207; Fri, 19 Feb 2016 19:07:46 +0800", "(from xiaowan1@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u1JB7iN5007203; \n\tFri, 19 Feb 2016 19:07:44 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,470,1449561600\"; d=\"scan'208\";a=\"906741626\"", "From": "Wang Xiao W <xiao.w.wang@intel.com>", "To": "jing.d.chen@intel.com", "Date": "Fri, 19 Feb 2016 19:07:04 +0800", "Message-Id": "<1455880025-6912-18-git-send-email-xiao.w.wang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1455880025-6912-1-git-send-email-xiao.w.wang@intel.com>", "References": "<1453866647-16215-2-git-send-email-xiao.w.wang@intel.com>\n\t<1455880025-6912-1-git-send-email-xiao.w.wang@intel.com>", "Cc": "dev@dpdk.org", "Subject": "[dpdk-dev] [PATCH v3 17/18] fm10k/base: minor cleanups", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Some cleanups to better reflect the code that was actually pushed out to\nthe upstream Linux community.\n\nAmong the above cleanups, a few macros such as FM10K_RXINT_TIMER_SHIFT are\nremoved, but they are needed in dpdk/fm10k, so we have to put all these\nnecessary macros into fm10k_osdep.h.\n\nSigned-off-by: Wang Xiao W <xiao.w.wang@intel.com>\n---\n drivers/net/fm10k/base/fm10k_mbx.h | 7 --\n drivers/net/fm10k/base/fm10k_osdep.h | 32 +++++++++\n drivers/net/fm10k/base/fm10k_pf.h | 4 --\n drivers/net/fm10k/base/fm10k_type.h | 132 -----------------------------------\n 4 files changed, 32 insertions(+), 143 deletions(-)", "diff": "diff --git a/drivers/net/fm10k/base/fm10k_mbx.h b/drivers/net/fm10k/base/fm10k_mbx.h\nindex e642c2f..edc57df 100644\n--- a/drivers/net/fm10k/base/fm10k_mbx.h\n+++ b/drivers/net/fm10k/base/fm10k_mbx.h\n@@ -48,7 +48,6 @@ struct fm10k_mbx_info;\n /* XOR provides means of switching from Tx to Rx FIFO */\n #define FM10K_MBMEM_PF_XOR\t(FM10K_MBMEM_SM(0) ^ FM10K_MBMEM_PF(0))\n #define FM10K_MBX(_n)\t\t((_n) + 0x18800)\n-#define FM10K_MBX_OWNER\t\t\t\t0x00000001\n #define FM10K_MBX_REQ\t\t\t\t0x00000002\n #define FM10K_MBX_ACK\t\t\t\t0x00000004\n #define FM10K_MBX_REQ_INTERRUPT\t\t\t0x00000008\n@@ -213,7 +212,6 @@ enum fm10k_msg_type {\n /* version number for switch manager mailboxes */\n #define FM10K_SM_MBX_VERSION\t\t1\n #define FM10K_SM_MBX_FIFO_LEN\t\t(FM10K_MBMEM_PF_XOR - 1)\n-#define FM10K_SM_MBX_FIFO_HDR_LEN\t1\n \n /* offsets shared between all SM FIFO headers */\n #define FM10K_MSG_SM_TAIL_SHIFT\t\t\t0\n@@ -233,18 +231,13 @@ enum fm10k_msg_type {\n */\n #define FM10K_MBX_ERR(_n) ((_n) - 512)\n #define FM10K_MBX_ERR_NO_MBX\t\tFM10K_MBX_ERR(0x01)\n-#define FM10K_MBX_ERR_NO_MSG\t\tFM10K_MBX_ERR(0x02)\n #define FM10K_MBX_ERR_NO_SPACE\t\tFM10K_MBX_ERR(0x03)\n-#define FM10K_MBX_ERR_LOCK\t\tFM10K_MBX_ERR(0x04)\n #define FM10K_MBX_ERR_TAIL\t\tFM10K_MBX_ERR(0x05)\n #define FM10K_MBX_ERR_HEAD\t\tFM10K_MBX_ERR(0x06)\n-#define FM10K_MBX_ERR_DST\t\tFM10K_MBX_ERR(0x07)\n #define FM10K_MBX_ERR_SRC\t\tFM10K_MBX_ERR(0x08)\n #define FM10K_MBX_ERR_TYPE\t\tFM10K_MBX_ERR(0x09)\n-#define FM10K_MBX_ERR_LEN\t\tFM10K_MBX_ERR(0x0A)\n #define FM10K_MBX_ERR_SIZE\t\tFM10K_MBX_ERR(0x0B)\n #define FM10K_MBX_ERR_BUSY\t\tFM10K_MBX_ERR(0x0C)\n-#define FM10K_MBX_ERR_VALUE\t\tFM10K_MBX_ERR(0x0D)\n #define FM10K_MBX_ERR_RSVD0\t\tFM10K_MBX_ERR(0x0E)\n #define FM10K_MBX_ERR_CRC\t\tFM10K_MBX_ERR(0x0F)\n \ndiff --git a/drivers/net/fm10k/base/fm10k_osdep.h b/drivers/net/fm10k/base/fm10k_osdep.h\nindex 6852ef0..a21daa2 100644\n--- a/drivers/net/fm10k/base/fm10k_osdep.h\n+++ b/drivers/net/fm10k/base/fm10k_osdep.h\n@@ -150,6 +150,38 @@ typedef int bool;\n #define fm10k_read_reg FM10K_READ_REG\n #endif\n \n+#define FM10K_INTEL_VENDOR_ID 0x8086\n+#define FM10K_DMA_CTRL_MINMSS_SHIFT\t\t9\n+#define FM10K_EICR_PCA_FAULT\t\t\t0x00000001\n+#define FM10K_EICR_THI_FAULT\t\t\t0x00000004\n+#define FM10K_EICR_FUM_FAULT\t\t\t0x00000020\n+#define FM10K_EICR_SRAMERROR\t\t\t0x00000400\n+#define FM10K_SRAM_IP\t\t0x13003\n+#define FM10K_RXINT_TIMER_SHIFT\t\t\t8\n+#define FM10K_TXINT_TIMER_SHIFT\t\t\t8\n+#define FM10K_RXD_PKTTYPE_MASK\t\t0x03F0\n+#define FM10K_RXD_PKTTYPE_SHIFT\t\t4\n+\n+enum fm10k_rdesc_pkt_type {\n+\t/* L3 type */\n+\tFM10K_PKTTYPE_OTHER\t= 0x00,\n+\tFM10K_PKTTYPE_IPV4\t= 0x01,\n+\tFM10K_PKTTYPE_IPV4_EX\t= 0x02,\n+\tFM10K_PKTTYPE_IPV6\t= 0x03,\n+\tFM10K_PKTTYPE_IPV6_EX\t= 0x04,\n+\n+\t/* L4 type */\n+\tFM10K_PKTTYPE_TCP\t= 0x08,\n+\tFM10K_PKTTYPE_UDP\t= 0x10,\n+\tFM10K_PKTTYPE_GRE\t= 0x18,\n+\tFM10K_PKTTYPE_VXLAN\t= 0x20,\n+\tFM10K_PKTTYPE_NVGRE\t= 0x28,\n+\tFM10K_PKTTYPE_GENEVE\t= 0x30\n+};\n+\n+#define FM10K_RXD_STATUS_IPCS\t\t0x0008 /* Indicates IPv4 csum */\n+#define FM10K_RXD_STATUS_HBO\t\t0x0400 /* header buffer overrun */\n+\n #define FM10K_TSO_MINMSS \\\n \t(FM10K_DMA_CTRL_MINMSS_64 >> FM10K_DMA_CTRL_MINMSS_SHIFT)\n #define FM10K_TSO_MIN_HEADERLEN\t\t\t54\ndiff --git a/drivers/net/fm10k/base/fm10k_pf.h b/drivers/net/fm10k/base/fm10k_pf.h\nindex ee8527a..c84b1bc 100644\n--- a/drivers/net/fm10k/base/fm10k_pf.h\n+++ b/drivers/net/fm10k/base/fm10k_pf.h\n@@ -140,10 +140,6 @@ struct fm10k_swapi_1588_clock_owner {\n #pragma pack()\n #endif /* C99 */\n \n-#define FM10K_PF_MSG_LPORT_CREATE_HANDLER(func) \\\n-\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_LPORT_CREATE, NULL, func)\n-#define FM10K_PF_MSG_LPORT_DELETE_HANDLER(func) \\\n-\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_LPORT_DELETE, NULL, func)\n s32 fm10k_msg_lport_map_pf(struct fm10k_hw *, u32 **, struct fm10k_mbx_info *);\n extern const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[];\n #define FM10K_PF_MSG_LPORT_MAP_HANDLER(func) \\\ndiff --git a/drivers/net/fm10k/base/fm10k_type.h b/drivers/net/fm10k/base/fm10k_type.h\nindex c4e5450..f807216 100644\n--- a/drivers/net/fm10k/base/fm10k_type.h\n+++ b/drivers/net/fm10k/base/fm10k_type.h\n@@ -40,7 +40,6 @@ struct fm10k_hw;\n #include \"fm10k_osdep.h\"\n #include \"fm10k_mbx.h\"\n \n-#define FM10K_INTEL_VENDOR_ID\t\t0x8086\n #define FM10K_DEV_ID_PF\t\t\t0x15A4\n #define FM10K_DEV_ID_VF\t\t\t0x15A5\n #ifdef BOULDER_RAPIDS_HW\n@@ -121,28 +120,16 @@ struct fm10k_hw;\n #define FM10K_CTRL_BAR4_ALLOWED\t\t\t0x00000004\n \n #define FM10K_CTRL_EXT\t\t0x0001\n-#define FM10K_CTRL_EXT_NS_DIS\t\t\t0x00000001\n-#define FM10K_CTRL_EXT_RO_DIS\t\t\t0x00000002\n-#define FM10K_CTRL_EXT_SWITCH_LOOPBACK\t\t0x00000004\n-#define FM10K_EXVET\t\t0x0002\n-#define FM10K_EXVET_ETHERTYPE_MASK\t\t0x000000FF\n-#define FM10K_EXVET_TAG_SIZE_SHIFT\t\t16\n-#define FM10K_EXVET_AFTER_VLAN\t\t\t0x00040000\n #define FM10K_GCR\t\t0x0003\n-#define FM10K_FACTPS\t\t0x0004\n #define FM10K_GCR_EXT\t\t0x0005\n \n /* Interrupt control registers */\n #define FM10K_EICR\t\t0x0006\n-#define FM10K_EICR_PCA_FAULT\t\t\t0x00000001\n-#define FM10K_EICR_THI_FAULT\t\t\t0x00000004\n-#define FM10K_EICR_FUM_FAULT\t\t\t0x00000020\n #define FM10K_EICR_FAULT_MASK\t\t\t0x0000003F\n #define FM10K_EICR_MAILBOX\t\t\t0x00000040\n #define FM10K_EICR_SWITCHREADY\t\t\t0x00000080\n #define FM10K_EICR_SWITCHNOTREADY\t\t0x00000100\n #define FM10K_EICR_SWITCHINTERRUPT\t\t0x00000200\n-#define FM10K_EICR_SRAMERROR\t\t\t0x00000400\n #define FM10K_EICR_VFLR\t\t\t\t0x00000800\n #define FM10K_EICR_MAXHOLDTIME\t\t\t0x00001000\n #define FM10K_EIMR\t\t0x0007\n@@ -196,7 +183,6 @@ struct fm10k_hw;\n #define FM10K_DGLORTDEC_INNERRSS_ENABLE\t\t0x08000000\n #define FM10K_TUNNEL_CFG\t0x0040\n #define FM10K_TUNNEL_CFG_NVGRE_SHIFT\t\t16\n-#define FM10K_TUNNEL_CFG_GENEVE\t0x0041\n #define FM10K_SWPRI_MAP(_n)\t((_n) + 0x0050)\n #define FM10K_SWPRI_MAX\t\t16\n #define FM10K_RSSRK(_n, _m)\t(((_n) * 0x10) + (_m) + 0x0800)\n@@ -217,38 +203,23 @@ struct fm10k_hw;\n #define FM10K_TC_RATE_INTERVAL_4US_GEN1\t\t0x00020000\n #define FM10K_TC_RATE_INTERVAL_4US_GEN2\t\t0x00040000\n #define FM10K_TC_RATE_INTERVAL_4US_GEN3\t\t0x00080000\n-#define FM10K_TC_RATE_STATUS\t0x20C0\n-#define FM10K_PAUSE\t\t0x20C2\n \n /* DMA control registers */\n #define FM10K_DMA_CTRL\t\t0x20C3\n #define FM10K_DMA_CTRL_TX_ENABLE\t\t0x00000001\n-#define FM10K_DMA_CTRL_TX_HOST_PENDING\t\t0x00000002\n-#define FM10K_DMA_CTRL_TX_DATA\t\t\t0x00000004\n #define FM10K_DMA_CTRL_TX_ACTIVE\t\t0x00000008\n #define FM10K_DMA_CTRL_RX_ENABLE\t\t0x00000010\n-#define FM10K_DMA_CTRL_RX_HOST_PENDING\t\t0x00000020\n-#define FM10K_DMA_CTRL_RX_DATA\t\t\t0x00000040\n #define FM10K_DMA_CTRL_RX_ACTIVE\t\t0x00000080\n #define FM10K_DMA_CTRL_RX_DESC_SIZE\t\t0x00000100\n-#define FM10K_DMA_CTRL_MINMSS_SHIFT\t\t9\n #define FM10K_DMA_CTRL_MINMSS_64\t\t0x00008000\n-#define FM10K_DMA_CTRL_MAX_HOLD_TIME_SHIFT\t23\n #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3\t0x04800000\n #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2\t0x04000000\n #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1\t0x03800000\n #define FM10K_DMA_CTRL_DATAPATH_RESET\t\t0x20000000\n-#define FM10K_DMA_CTRL_MAXNUMOFQ_MASK\t\t0xC0000000\n #define FM10K_DMA_CTRL_32_DESC\t\t\t0x00000000\n-#define FM10K_DMA_CTRL_64_DESC\t\t\t0x40000000\n-#define FM10K_DMA_CTRL_128_DESC\t\t\t0x80000000\n \n #define FM10K_DMA_CTRL2\t\t0x20C4\n-#define FM10K_DMA_CTRL2_TX_FRAME_SPACING_SHIFT\t5\n #define FM10K_DMA_CTRL2_SWITCH_READY\t\t0x00002000\n-#define FM10K_DMA_CTRL2_RX_DESC_READ_PRIO_SHIFT\t14\n-#define FM10K_DMA_CTRL2_TX_DESC_READ_PRIO_SHIFT\t17\n-#define FM10K_DMA_CTRL2_TX_DATA_READ_PRIO_SHIFT\t20\n \n /* TSO flags configuration\n * First packet contains all flags except for fin and psh\n@@ -261,7 +232,6 @@ struct fm10k_hw;\n #define FM10K_DTXTCPFLGH\t0x20C6\n \n #define FM10K_TPH_CTRL\t\t0x20C7\n-#define FM10K_TPH_CTRL_DISABLE_READ_HINT\t0x00000080\n #define FM10K_MRQC(_n)\t\t((_n) + 0x2100)\n #define FM10K_MRQC_TCP_IPV4\t\t\t0x00000001\n #define FM10K_MRQC_IPV4\t\t\t\t0x00000002\n@@ -273,7 +243,6 @@ struct fm10k_hw;\n #define FM10K_TQMAP(_n)\t\t((_n) + 0x2800)\n #define FM10K_TQMAP_TABLE_SIZE\t\t\t2048\n #define FM10K_RQMAP(_n)\t\t((_n) + 0x3000)\n-#define FM10K_RQMAP_TABLE_SIZE\t\t\t2048\n \n /* Hardware Statistics */\n #define FM10K_STATS_TIMEOUT\t\t0x3800\n@@ -286,16 +255,11 @@ struct fm10k_hw;\n #define FM10K_STATS_NODESC_DROP\t\t0x3807\n \n /* Timesync registers */\n-#define FM10K_RRTIME_CFG\t0x3808\n-#define FM10K_RRTIME_LIMIT(_n)\t((_n) + 0x380C)\n-#define FM10K_RRTIME_COUNT(_n)\t((_n) + 0x3810)\n #define FM10K_SYSTIME\t\t0x3814\n-#define FM10K_SYSTIME0\t\t0x3816\n #define FM10K_SYSTIME_CFG\t0x3818\n #define FM10K_SYSTIME_CFG_STEP_MASK\t\t0x0000000F\n \n /* PCIe state registers */\n-#define FM10K_PFVFBME(_n)\t((_n) + 0x381A)\n #define FM10K_PHYADDR\t\t0x381C\n \n /* Rx ring registers */\n@@ -304,8 +268,6 @@ struct fm10k_hw;\n #define FM10K_RDLEN(_n)\t\t((0x40 * (_n)) + 0x4002)\n #define FM10K_TPH_RXCTRL(_n)\t((0x40 * (_n)) + 0x4003)\n #define FM10K_TPH_RXCTRL_DESC_TPHEN\t\t0x00000020\n-#define FM10K_TPH_RXCTRL_HDR_TPHEN\t\t0x00000040\n-#define FM10K_TPH_RXCTRL_DATA_TPHEN\t\t0x00000080\n #define FM10K_TPH_RXCTRL_DESC_RROEN\t\t0x00000200\n #define FM10K_TPH_RXCTRL_DATA_WROEN\t\t0x00002000\n #define FM10K_TPH_RXCTRL_HDR_WROEN\t\t0x00008000\n@@ -319,27 +281,10 @@ struct fm10k_hw;\n #define FM10K_RXQCTL_ID_MASK\t(FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)\n #define FM10K_RXDCTL(_n)\t((0x40 * (_n)) + 0x4007)\n #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY\t0x00000001\n-#define FM10K_RXDCTL_WRITE_BACK_IMM\t\t0x00000100\n #define FM10K_RXDCTL_DROP_ON_EMPTY\t\t0x00000200\n #define FM10K_RXINT(_n)\t\t((0x40 * (_n)) + 0x4008)\n-#define FM10K_RXINT_TIMER_SHIFT\t\t\t8\n #define FM10K_SRRCTL(_n)\t((0x40 * (_n)) + 0x4009)\n #define FM10K_SRRCTL_BSIZEPKT_SHIFT\t\t8 /* shift _right_ */\n-#define FM10K_SRRCTL_BSIZEHDR_SHIFT\t\t2 /* shift _left_ */\n-#define FM10K_SRRCTL_BSIZEHDR_MASK\t\t0x00003F00\n-#define FM10K_SRRCTL_DESCTYPE_HDR_SPLIT\t\t0x00004000\n-#define FM10K_SRRCTL_DESCTYPE_SIZE_SPLIT\t0x00008000\n-#define FM10K_SRRCTL_PSRTYPE_INNER_TCPHDR\t0x00010000\n-#define FM10K_SRRCTL_PSRTYPE_INNER_UDPHDR\t0x00020000\n-#define FM10K_SRRCTL_PSRTYPE_INNER_IPV4HDR\t0x00040000\n-#define FM10K_SRRCTL_PSRTYPE_INNER_IPV6HDR\t0x00080000\n-#define FM10K_SRRCTL_PSRTYPE_INNER_L2HDR\t0x00100000\n-#define FM10K_SRRCTL_PSRTYPE_ENCAPHDR\t\t0x00200000\n-#define FM10K_SRRCTL_PSRTYPE_TCPHDR\t\t0x00400000\n-#define FM10K_SRRCTL_PSRTYPE_UDPHDR\t\t0x00800000\n-#define FM10K_SRRCTL_PSRTYPE_IPV4HDR\t\t0x01000000\n-#define FM10K_SRRCTL_PSRTYPE_IPV6HDR\t\t0x02000000\n-#define FM10K_SRRCTL_PSRTYPE_L2HDR\t\t0x04000000\n #define FM10K_SRRCTL_LOOPBACK_SUPPRESS\t\t0x40000000\n #define FM10K_SRRCTL_BUFFER_CHAINING_EN\t\t0x80000000\n \n@@ -380,7 +325,6 @@ struct fm10k_hw;\n #define FM10K_TXDCTL(_n)\t((0x40 * (_n)) + 0x8006)\n #define FM10K_TXDCTL_ENABLE\t\t\t0x00004000\n #define FM10K_TXDCTL_MAX_TIME_SHIFT\t\t16\n-#define FM10K_TXDCTL_PUSH_DESC\t\t\t0x10000000\n #define FM10K_TXQCTL(_n)\t((0x40 * (_n)) + 0x8007)\n #define FM10K_TXQCTL_PF\t\t\t\t0x0000003F\n #define FM10K_TXQCTL_VF\t\t\t\t0x00000040\n@@ -388,13 +332,10 @@ struct fm10k_hw;\n #define FM10K_TXQCTL_PC_SHIFT\t\t\t7\n #define FM10K_TXQCTL_PC_MASK\t\t\t0x00000380\n #define FM10K_TXQCTL_TC_SHIFT\t\t\t10\n-#define FM10K_TXQCTL_TC_MASK\t\t\t0x0000FC00\n #define FM10K_TXQCTL_VID_SHIFT\t\t\t16\n #define FM10K_TXQCTL_VID_MASK\t\t\t0x0FFF0000\n #define FM10K_TXQCTL_UNLIMITED_BW\t\t0x10000000\n-#define FM10K_TXQCTL_PUSHMODEDIS\t\t0x20000000\n #define FM10K_TXINT(_n)\t\t((0x40 * (_n)) + 0x8008)\n-#define FM10K_TXINT_TIMER_SHIFT\t\t\t8\n \n /* Tx Statistics */\n #define FM10K_QPTC(_n)\t\t((0x40 * (_n)) + 0x8009)\n@@ -404,13 +345,7 @@ struct fm10k_hw;\n /* Tx Push registers */\n #define FM10K_TQDLOC(_n)\t((0x40 * (_n)) + 0x800C)\n #define FM10K_TQDLOC_BASE_32_DESC\t\t0x08\n-#define FM10K_TQDLOC_BASE_64_DESC\t\t0x10\n-#define FM10K_TQDLOC_BASE_128_DESC\t\t0x20\n #define FM10K_TQDLOC_SIZE_32_DESC\t\t0x00050000\n-#define FM10K_TQDLOC_SIZE_64_DESC\t\t0x00060000\n-#define FM10K_TQDLOC_SIZE_128_DESC\t\t0x00070000\n-#define FM10K_TQDLOC_SIZE_SHIFT\t\t\t16\n-#define FM10K_TX_DCACHE(_n, _m)\t((0x400 * (_n)) + (0x4 * (_m)) + 0x40000)\n \n /* Tx GLORT registers */\n #define FM10K_TX_SGLORT(_n)\t((0x40 * (_n)) + 0x800D)\n@@ -418,50 +353,27 @@ struct fm10k_hw;\n #define FM10K_PFVTCTL_FTAG_DESC_ENABLE\t\t0x00000001\n \n /* Interrupt moderation and control registers */\n-#define FM10K_PBACL(_n)\t\t((_n) + 0x10000)\n #define FM10K_INT_MAP(_n)\t((_n) + 0x10080)\n #define FM10K_INT_MAP_TIMER0\t\t\t0x00000000\n #define FM10K_INT_MAP_TIMER1\t\t\t0x00000100\n #define FM10K_INT_MAP_IMMEDIATE\t\t\t0x00000200\n #define FM10K_INT_MAP_DISABLE\t\t\t0x00000300\n-#define FM10K_MSIX_VECTOR_ADDR_LO(_n)\t((0x4 * (_n)) + 0x11000)\n-#define FM10K_MSIX_VECTOR_ADDR_HI(_n)\t((0x4 * (_n)) + 0x11001)\n-#define FM10K_MSIX_VECTOR_DATA(_n)\t((0x4 * (_n)) + 0x11002)\n #define FM10K_MSIX_VECTOR_MASK(_n)\t((0x4 * (_n)) + 0x11003)\n #define FM10K_INT_CTRL\t\t0x12000\n #define FM10K_INT_CTRL_ENABLEMODERATOR\t\t0x00000400\n #define FM10K_ITR(_n)\t\t((_n) + 0x12400)\n #define FM10K_ITR_INTERVAL1_SHIFT\t\t12\n-#define FM10K_ITR_TIMER0_EXPIRED\t\t0x01000000\n-#define FM10K_ITR_TIMER1_EXPIRED\t\t0x02000000\n-#define FM10K_ITR_PENDING0\t\t\t0x04000000\n-#define FM10K_ITR_PENDING1\t\t\t0x08000000\n #define FM10K_ITR_PENDING2\t\t\t0x10000000\n #define FM10K_ITR_AUTOMASK\t\t\t0x20000000\n #define FM10K_ITR_MASK_SET\t\t\t0x40000000\n #define FM10K_ITR_MASK_CLEAR\t\t\t0x80000000\n #define FM10K_ITR2(_n)\t\t((0x2 * (_n)) + 0x12800)\n-#define FM10K_ITR2_LP(_n)\t((0x2 * (_n)) + 0x12801)\n #define FM10K_ITR_REG_COUNT\t\t\t768\n #define FM10K_ITR_REG_COUNT_PF\t\t\t256\n \n /* Switch manager interrupt registers */\n #define FM10K_IP\t\t0x13000\n-#define FM10K_IP_HOT_RESET\t\t\t0x00000001\n-#define FM10K_IP_DEVICE_STATE_CHANGE\t\t0x00000002\n-#define FM10K_IP_MAILBOX\t\t\t0x00000004\n-#define FM10K_IP_VPD_REQUEST\t\t\t0x00000008\n-#define FM10K_IP_SRAMERROR\t\t\t0x00000010\n-#define FM10K_IP_PFLR\t\t\t\t0x00000020\n-#define FM10K_IP_DATAPATHRESET\t\t\t0x00000040\n-#define FM10K_IP_OUTOFRESET\t\t\t0x00000080\n #define FM10K_IP_NOTINRESET\t\t\t0x00000100\n-#define FM10K_IP_TIMEOUT\t\t\t0x00000200\n-#define FM10K_IP_VFLR\t\t\t\t0x00000400\n-#define FM10K_IM\t\t0x13001\n-#define FM10K_IB\t\t0x13002\n-#define FM10K_SRAM_IP\t\t0x13003\n-#define FM10K_SRAM_IM\t\t0x13004\n \n /* VLAN registers */\n #define FM10K_VLAN_TABLE(_n, _m)\t((0x80 * (_n)) + (_m) + 0x14000)\n@@ -499,12 +411,8 @@ struct fm10k_hw;\n #define FM10K_VFINT_MAP\t\t0x00030\n #define FM10K_VFSYSTIME\t\t0x00040\n #define FM10K_VFITR(_n)\t\t((_n) + 0x00060)\n-#define FM10K_VFPBACL(_n)\t((_n) + 0x00008)\n \n /* Registers contained in BAR 4 for Switch management */\n-#define FM10K_SW_SYSTIME_CFG\t0x0224C\n-#define FM10K_SW_SYSTIME_CFG_STEP_SHIFT\t\t4\n-#define FM10K_SW_SYSTIME_CFG_ADJUST_MASK\t0xFF000000\n #define FM10K_SW_SYSTIME_ADJUST\t0x0224D\n #define FM10K_SW_SYSTIME_ADJUST_MASK\t\t0x3FFFFFFF\n #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE\t0x80000000\n@@ -778,8 +686,6 @@ struct fm10k_vf_info {\n #define FM10K_VF_FLAG_CAPABLE(vf_info)\t((vf_info)->vf_flags & (u8)0xF)\n #define FM10K_VF_FLAG_ENABLED(vf_info)\t((vf_info)->vf_flags >> 4)\n #define FM10K_VF_FLAG_SET_MODE(mode)\t((u8)0x10 << (mode))\n-#define FM10K_VF_FLAG_ENABLED_MODE_SHIFT\t4\n-#define FM10K_VF_FLAG_SET_MODE_MASK\t((u8)0xF0)\n #define FM10K_VF_FLAG_SET_MODE_NONE \\\n \tFM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)\n #define FM10K_VF_FLAG_MULTI_ENABLED \\\n@@ -850,13 +756,11 @@ struct fm10k_tx_desc_cache {\n #define FM10K_TXD_FLAG_INT\t0x01\n #define FM10K_TXD_FLAG_TIME\t0x02\n #define FM10K_TXD_FLAG_CSUM\t0x04\n-#define FM10K_TXD_FLAG_CSUM2\t0x08\n #define FM10K_TXD_FLAG_FTAG\t0x10\n #define FM10K_TXD_FLAG_RS\t0x20\n #define FM10K_TXD_FLAG_LAST\t0x40\n #define FM10K_TXD_FLAG_DONE\t0x80\n \n-#define FM10K_TXD_VLAN_PRI_SHIFT\t12\n \n /* These macros are meant to enable optimal placement of the RS and INT\n * bits. It will point us to the last descriptor in the cache for either the\n@@ -865,8 +769,6 @@ struct fm10k_tx_desc_cache {\n * in the FIFO to prevent an unnecessary write.\n */\n #define FM10K_TXD_WB_FIFO_SIZE\t4\n-#define FM10K_TXD_WB_IDX(idx) \\\n-\t(((idx) - 1) | (FM10K_TXD_WB_FIFO_SIZE - 1))\n \n /* Receive Descriptor - 32B */\n union fm10k_rx_desc {\n@@ -911,29 +813,6 @@ enum fm10k_rdesc_rss_type {\n \t/* Reserved 0x9 - 0xF */\n };\n \n-#define FM10K_RXD_PKTTYPE_MASK\t\t0x03F0\n-#define FM10K_RXD_PKTTYPE_MASK_L3\t0x0070\n-#define FM10K_RXD_PKTTYPE_MASK_L4\t0x0380\n-#define FM10K_RXD_PKTTYPE_SHIFT\t\t4\n-#define FM10K_RXD_PKTTYPE_INNER_MASK_L3\t0x1C00\n-#define FM10K_RXD_PKTTYPE_INNER_MASK_L4\t0xE000\n-#define FM10K_RXD_PKTTYPE_INNER_SHIFT\t10\n-enum fm10k_rdesc_pkt_type {\n-\t/* L3 type */\n-\tFM10K_PKTTYPE_OTHER\t= 0x00,\n-\tFM10K_PKTTYPE_IPV4\t= 0x01,\n-\tFM10K_PKTTYPE_IPV4_EX\t= 0x02,\n-\tFM10K_PKTTYPE_IPV6\t= 0x03,\n-\tFM10K_PKTTYPE_IPV6_EX\t= 0x04,\n-\n-\t/* L4 type */\n-\tFM10K_PKTTYPE_TCP\t= 0x08,\n-\tFM10K_PKTTYPE_UDP\t= 0x10,\n-\tFM10K_PKTTYPE_GRE\t= 0x18,\n-\tFM10K_PKTTYPE_VXLAN\t= 0x20,\n-\tFM10K_PKTTYPE_NVGRE\t= 0x28,\n-\tFM10K_PKTTYPE_GENEVE\t= 0x30\n-};\n \n #define FM10K_RXD_HDR_INFO_XC_MASK\t0x0006\n enum fm10k_rxdesc_xc {\n@@ -942,20 +821,11 @@ enum fm10k_rxdesc_xc {\n \tFM10K_XC_BROADCAST\t= 0x6\n };\n \n-#define FM10K_RXD_HDR_INFO_LEN_SHIFT\t5\n-#define FM10K_RXD_HDR_INFO_SPH\t\t0x8000\n \n #define FM10K_RXD_STATUS_DD\t\t0x0001 /* Descriptor done */\n #define FM10K_RXD_STATUS_EOP\t\t0x0002 /* End of packet */\n-#define FM10K_RXD_STATUS_VEXT\t\t0x0004 /* A VLAN tag is present */\n-#define FM10K_RXD_STATUS_IPCS\t\t0x0008 /* Indicates IPv4 csum */\n #define FM10K_RXD_STATUS_L4CS\t\t0x0010 /* Indicates an L4 csum */\n-#define FM10K_RXD_STATUS_IPCS2\t\t0x0020 /* Inner header IPv4 csum */\n #define FM10K_RXD_STATUS_L4CS2\t\t0x0040 /* Inner header L4 csum */\n-#define FM10K_RXD_STATUS_IPFRAG_MASK\t0x0180 /* Fragment mask */\n-#define FM10K_RXD_STATUS_IPFRAG_CSUM\t0x0100 /* Fragment w/ CSUM field */\n-#define FM10K_RXD_STATUS_VEXT2\t\t0x0200 /* A custom tag is present */\n-#define FM10K_RXD_STATUS_HBO\t\t0x0400 /* header buffer overrun */\n #define FM10K_RXD_STATUS_L4E2\t\t0x0800 /* Inner header L4 csum err */\n #define FM10K_RXD_STATUS_IPE2\t\t0x1000 /* Inner header IPv4 csum err */\n #define FM10K_RXD_STATUS_RXE\t\t0x2000 /* Generic Rx error */\n@@ -968,8 +838,6 @@ enum fm10k_rxdesc_xc {\n #define FM10K_RXD_ERR_SWITCH_READY\t0x0008 /* Link transition mid-packet */\n #define FM10K_RXD_ERR_TOO_BIG\t\t0x0010 /* Pkt too big for single buf */\n \n-#define FM10K_RXD_VLAN_ID_MASK\t\t0x0FFF\n-#define FM10K_RXD_VLAN_PRI_SHIFT\tFM10K_TXD_VLAN_PRI_SHIFT\n \n struct fm10k_ftag {\n \t__be16 swpri_type_user;\n", "prefixes": [ "dpdk-dev", "v3", "17/18" ] }