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GET /api/patches/106947/?format=api
{ "id": 106947, "url": "http://patches.dpdk.org/api/patches/106947/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220207072932.22409-16-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220207072932.22409-16-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220207072932.22409-16-ndabilpuram@marvell.com", "date": "2022-02-07T07:29:28", "name": "[16/20] net/cnxk: use NPA batch burst free for meta buffers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "39120c00bc89092cbe9ab95dd10f4abe6d56bdbd", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220207072932.22409-16-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 21483, "url": "http://patches.dpdk.org/api/series/21483/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21483", "date": "2022-02-07T07:29:13", "name": "[01/20] common/cnxk: increase resource count for bitmap alloc", "version": 1, "mbox": "http://patches.dpdk.org/series/21483/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/106947/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/106947/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 29757A034F;\n\tMon, 7 Feb 2022 08:31:55 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DE966411FB;\n\tMon, 7 Feb 2022 08:30:35 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id A42A641203\n for <dev@dpdk.org>; Mon, 7 Feb 2022 08:30:34 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 216Mp8dg022472\n for <dev@dpdk.org>; Sun, 6 Feb 2022 23:30:34 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e1smr4p64-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 06 Feb 2022 23:30:33 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sun, 6 Feb 2022 23:30:31 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sun, 6 Feb 2022 23:30:31 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 5826A3F705C;\n Sun, 6 Feb 2022 23:30:29 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=5aCviEKOVbUQwUZJHJVAkRZLYltYyoKClSzjdsUEBWQ=;\n b=YusuDFTHbRKh1c0aJ0n4CJeMoUGuZzrxopZoHgB9rtqaoyQoqVqPqtd+rX/qH4IxIVTD\n BUPMp82+cya+sJHjnWESw5eQE+JcuOjXcDyxXbXzfK+wdn7p/SBUfT9ivwrv6mOrJJ8k\n LSQUupOb55H+CXEieqaZePzRS39Xx0p0c4asOllwqfcXAGDQdkBaHsNg5NLARAVA3w+d\n pos0tWCQIM+2y9ariFFM26kaETaJLgDxsWJJwJ66ca/1YG3UFFIFC3zRz1T5DHkXe3AS\n C6VOOSphykjDgRtzZ9u74St5ZzkteV8tQ020bG17qcSJ7H+j1Hn9yR4kIqkenwrzNHlC BQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori\n <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 16/20] net/cnxk: use NPA batch burst free for meta buffers", "Date": "Mon, 7 Feb 2022 12:59:28 +0530", "Message-ID": "<20220207072932.22409-16-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220207072932.22409-1-ndabilpuram@marvell.com>", "References": "<20220207072932.22409-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "B3gkJOZjiteJIEnEaIIHj44U-pK6BpW7", "X-Proofpoint-ORIG-GUID": "B3gkJOZjiteJIEnEaIIHj44U-pK6BpW7", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-02-07_02,2022-02-03_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Currently meta buffers are freed in bursts of one LMT line\ni.e 15 pointers. Instead free them in bursts of 16 LMTlines\nwhich is 240 ptrs for better perf.\n\nAlso mark mempool objects as get and put in missing places.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/event/cnxk/cn10k_worker.h | 13 ++++-\n drivers/net/cnxk/cn10k_rx.h | 114 +++++++++++++++++++++++++++++++-------\n 2 files changed, 107 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex 78d029b..42be92d 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -93,12 +93,16 @@ cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,\n }\n \n static __rte_always_inline void\n-cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,\n+cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf, uint8_t port_id,\n \t\t const uint32_t tag, const uint32_t flags,\n \t\t const void *const lookup_mem)\n {\n \tconst uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |\n \t\t\t\t (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);\n+\tstruct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;\n+\n+\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);\n \n \tcn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,\n \t\t\t (struct rte_mbuf *)mbuf, lookup_mem,\n@@ -154,6 +158,9 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n \t\tmbuf = (struct rte_mbuf *)((char *)cqe -\n \t\t\t\t\t sizeof(struct rte_mbuf));\n \n+\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);\n+\n \t\t/* Translate meta to mbuf */\n \t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n \t\t\tconst uint64_t cq_w1 = *((const uint64_t *)cqe + 1);\n@@ -275,6 +282,10 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\t\t*(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;\n \t\t\tcn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,\n \t\t\t\t\t ws->tstamp, ws->lmt_base);\n+\t\t\t/* Mark vector mempool object as get */\n+\t\t\tRTE_MEMPOOL_CHECK_COOKIES(\n+\t\t\t\trte_mempool_from_obj((void *)gw.u64[1]),\n+\t\t\t\t(void **)&gw.u64[1], 1, 1);\n \t\t}\n \t}\n \ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex a2442d3..a8a4e65 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -67,6 +67,24 @@ nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)\n }\n \n static __rte_always_inline void\n+nix_sec_flush_meta_burst(uint16_t lmt_id, uint64_t data, uint16_t lnum,\n+\t\t\t uintptr_t aura_handle)\n+{\n+\tuint64_t pa;\n+\n+\t/* Prepare PA and Data */\n+\tpa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0;\n+\tpa |= ((data & 0x7) << 4);\n+\n+\tdata >>= 3;\n+\tdata <<= 19;\n+\tdata |= (uint64_t)lmt_id;\n+\tdata |= (uint64_t)(lnum - 1) << 12;\n+\n+\troc_lmt_submit_steorl(data, pa);\n+}\n+\n+static __rte_always_inline void\n nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff,\n \t\t uintptr_t aura_handle)\n {\n@@ -82,7 +100,7 @@ nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff,\n \t*(uint64_t *)laddr = (((uint64_t)(loff & 0x1) << 32) |\n \t\t\t roc_npa_aura_handle_to_aura(aura_handle));\n \n-\tpa |= ((loff >> 1) << 4);\n+\tpa |= ((uint64_t)(loff >> 1) << 4);\n \troc_lmt_submit_steorl(lmt_id, pa);\n }\n \n@@ -122,6 +140,12 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, const uint64_t sa_base, uintptr_t laddr,\n \t\t*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;\n \t\t*loff = *loff + 1;\n \n+\t\t/* Mark meta mbuf as put */\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 0);\n+\n+\t\t/* Mark inner mbuf as get */\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);\n+\n \t\treturn inner;\n \t}\n \treturn mbuf;\n@@ -181,6 +205,12 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uintptr_t sa_base, uintptr_t laddr,\n \t\t*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;\n \t\t*loff = *loff + 1;\n \n+\t\t/* Mark meta mbuf as put */\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 0);\n+\n+\t\t/* Mark inner mbuf as get */\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);\n+\n \t\t/* Return inner mbuf */\n \t\treturn inner;\n \t}\n@@ -306,9 +336,6 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \tuint16_t len = rx->pkt_lenm1 + 1;\n \tuint64_t ol_flags = 0;\n \n-\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n-\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);\n-\n \tif (flag & NIX_RX_OFFLOAD_PTYPE_F)\n \t\tmbuf->packet_type = nix_ptype_get(lookup_mem, w1);\n \telse\n@@ -440,6 +467,9 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \n \t\tmbuf = nix_get_mbuf_from_cqe(cq, data_off);\n \n+\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);\n+\n \t\t/* Translate meta to mbuf */\n \t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n \t\t\tconst uint64_t cq_w1 = *((const uint64_t *)cq + 1);\n@@ -538,7 +568,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \tuint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);\n \tstruct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n \tuint64_t aura_handle, lbase, laddr;\n-\tuint8_t loff = 0, lnum = 0;\n+\tuint8_t loff = 0, lnum = 0, shft = 0;\n \tuint8x16_t f0, f1, f2, f3;\n \tuint16_t lmt_id, d_off;\n \tuint16_t packets = 0;\n@@ -709,6 +739,12 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\tol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1);\n \t\t}\n \n+\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1);\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1);\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1);\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1);\n+\n \t\t/* Translate meta to mbuf */\n \t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n \t\t\t/* Checksum ol_flags will be cleared if mbuf is meta */\n@@ -905,12 +941,6 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\troc_prefetch_store_keep(mbuf2);\n \t\troc_prefetch_store_keep(mbuf3);\n \n-\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1);\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1);\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1);\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1);\n-\n \t\tpackets += NIX_DESCS_PER_LOOP;\n \n \t\tif (!(flags & NIX_RX_VWQE_F)) {\n@@ -920,22 +950,68 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t}\n \n \t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n-\t\t\t/* Flush when we don't have space for 4 meta */\n-\t\t\tif ((15 - loff) < 4) {\n-\t\t\t\tnix_sec_flush_meta(laddr, lmt_id + lnum, loff,\n-\t\t\t\t\t\t aura_handle);\n+\t\t\t/* Check if lmtline border is crossed and adjust lnum */\n+\t\t\tif (loff > 15) {\n+\t\t\t\t/* Update aura handle */\n+\t\t\t\t*(uint64_t *)(laddr - 8) =\n+\t\t\t\t\t(((uint64_t)(15 & 0x1) << 32) |\n+\t\t\t\t\t roc_npa_aura_handle_to_aura(\n+\t\t\t\t\t\t aura_handle));\n+\t\t\t\tloff = loff - 15;\n+\t\t\t\tshft += 3;\n+\n \t\t\t\tlnum++;\n-\t\t\t\tlnum &= BIT_ULL(ROC_LMT_LINES_PER_CORE_LOG2) -\n-\t\t\t\t\t1;\n-\t\t\t\t/* First pointer starts at 8B offset */\n \t\t\t\tladdr = (uintptr_t)LMT_OFF(lbase, lnum, 8);\n+\t\t\t\t/* Pick the pointer from 16th index and put it\n+\t\t\t\t * at end of this new line.\n+\t\t\t\t */\n+\t\t\t\t*(uint64_t *)(laddr + (loff << 3) - 8) =\n+\t\t\t\t\t*(uint64_t *)(laddr - 8);\n+\t\t\t}\n+\n+\t\t\t/* Flush it when we are in 16th line and might\n+\t\t\t * overflow it\n+\t\t\t */\n+\t\t\tif (lnum >= 15 && loff >= 12) {\n+\t\t\t\t/* 16 LMT Line size m1 */\n+\t\t\t\tuint64_t data = BIT_ULL(48) - 1;\n+\n+\t\t\t\t/* Update aura handle */\n+\t\t\t\t*(uint64_t *)(laddr - 8) =\n+\t\t\t\t\t(((uint64_t)(loff & 0x1) << 32) |\n+\t\t\t\t\t roc_npa_aura_handle_to_aura(\n+\t\t\t\t\t\t aura_handle));\n+\n+\t\t\t\tdata = (data & ~(0x7UL << shft)) |\n+\t\t\t\t (((uint64_t)loff >> 1) << shft);\n+\n+\t\t\t\t/* Send up to 16 lmt lines of pointers */\n+\t\t\t\tnix_sec_flush_meta_burst(lmt_id, data, lnum + 1,\n+\t\t\t\t\t\t\t aura_handle);\n+\t\t\t\trte_io_wmb();\n+\t\t\t\tlnum = 0;\n \t\t\t\tloff = 0;\n+\t\t\t\tshft = 0;\n+\t\t\t\t/* First pointer starts at 8B offset */\n+\t\t\t\tladdr = (uintptr_t)LMT_OFF(lbase, lnum, 8);\n \t\t\t}\n \t\t}\n \t}\n \n \tif (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {\n-\t\tnix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle);\n+\t\t/* 16 LMT Line size m1 */\n+\t\tuint64_t data = BIT_ULL(48) - 1;\n+\n+\t\t/* Update aura handle */\n+\t\t*(uint64_t *)(laddr - 8) =\n+\t\t\t(((uint64_t)(loff & 0x1) << 32) |\n+\t\t\t roc_npa_aura_handle_to_aura(aura_handle));\n+\n+\t\tdata = (data & ~(0x7UL << shft)) |\n+\t\t (((uint64_t)loff >> 1) << shft);\n+\n+\t\t/* Send up to 16 lmt lines of pointers */\n+\t\tnix_sec_flush_meta_burst(lmt_id, data, lnum + 1, aura_handle);\n \t\tif (flags & NIX_RX_VWQE_F)\n \t\t\tplt_io_wmb();\n \t}\n", "prefixes": [ "16/20" ] }