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GET /api/patches/106940/?format=api
{ "id": 106940, "url": "http://patches.dpdk.org/api/patches/106940/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220207072932.22409-7-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220207072932.22409-7-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220207072932.22409-7-ndabilpuram@marvell.com", "date": "2022-02-07T07:29:19", "name": "[07/20] common/cnxk: support to enable aura tail drop for RQ", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "d43878368c02f9e9fe908477788751e280234583", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220207072932.22409-7-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 21483, "url": "http://patches.dpdk.org/api/series/21483/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21483", "date": "2022-02-07T07:29:13", "name": "[01/20] common/cnxk: increase resource count for bitmap alloc", "version": 1, "mbox": "http://patches.dpdk.org/series/21483/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/106940/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/106940/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AEF83A034F;\n\tMon, 7 Feb 2022 08:31:06 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0704041174;\n\tMon, 7 Feb 2022 08:30:22 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 623584114E\n for <dev@dpdk.org>; Mon, 7 Feb 2022 08:30:17 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 216MmlZs020123;\n Sun, 6 Feb 2022 23:30:14 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e1smr4p2e-9\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sun, 06 Feb 2022 23:30:14 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sun, 6 Feb 2022 23:30:08 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sun, 6 Feb 2022 23:30:08 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id ECC243F709B;\n Sun, 6 Feb 2022 23:30:04 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=h4X+jB0gi4rgClPKL24z/rvycXUuiYUS5RoYZRDGqQ0=;\n b=dPQbVzeaGY6nYWikBfLLCL+xNLoc7hpsQ2Y5xiIYWwXLZhrpkjC8w9TfjIeOzwj6IFjj\n yyzU15u49eLuHOR7l3X+BD5YhjBiNAhHF4N6ErxczcK6L1ShEHwSCqjoF7NuiUqg5WEP\n xdF7mNYASz9XqEgFGrnzTInsK781UeADeIduyEPBGYLeMjftVWpOQeC4c2qcQq1VgpME\n ZdpENC/8WvainZfWajo+lr4sDtoCgOjt1/tZSvcF6/jbOOPw6s294xKGOBEJ93WbeGkU\n q2NbIHqKrZog/+3nxiArQOIFsAzVIFTdy8GatA2MrSZ4LCdpO1MeKJqoRPa2r8WRa6yi fg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 07/20] common/cnxk: support to enable aura tail drop for RQ", "Date": "Mon, 7 Feb 2022 12:59:19 +0530", "Message-ID": "<20220207072932.22409-7-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220207072932.22409-1-ndabilpuram@marvell.com>", "References": "<20220207072932.22409-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "xuVwfgM2u2EgE1tNxvR30YbUocEUFT10", "X-Proofpoint-ORIG-GUID": "xuVwfgM2u2EgE1tNxvR30YbUocEUFT10", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-02-07_02,2022-02-03_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support to enable aura tail drop via RQ specifically\nfor inline device RQ's pkt pool. This is better than RQ\nred drop as it can be applied to all RQ's that are not\nhaving security enabled but using same packet pool.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 4 ++++\n drivers/common/cnxk/roc_nix_inl.c | 39 ++++++++++++++++++++++++++++++----\n drivers/common/cnxk/roc_nix_inl.h | 2 ++\n drivers/common/cnxk/roc_nix_inl_dev.c | 9 ++++++++\n drivers/common/cnxk/roc_nix_inl_priv.h | 2 ++\n drivers/common/cnxk/roc_nix_queue.c | 6 +++++-\n drivers/common/cnxk/roc_npa.c | 33 ++++++++++++++++++++++++++--\n drivers/common/cnxk/roc_npa.h | 3 +++\n drivers/common/cnxk/version.map | 1 +\n 9 files changed, 92 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 250e1c0..0122b98 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -286,6 +286,10 @@ struct roc_nix_rq {\n \tuint8_t spb_red_drop;\n \t/* Average SPB aura level pass threshold for RED */\n \tuint8_t spb_red_pass;\n+\t/* LPB aura drop enable */\n+\tbool lpb_drop_ena;\n+\t/* SPB aura drop enable */\n+\tbool spb_drop_ena;\n \t/* End of Input parameters */\n \tstruct roc_nix *roc_nix;\n \tbool inl_dev_ref;\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex f57f1a4..ac17e95 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -528,23 +528,50 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)\n \tinl_rq->first_skip = rq->first_skip;\n \tinl_rq->later_skip = rq->later_skip;\n \tinl_rq->lpb_size = rq->lpb_size;\n+\tinl_rq->lpb_drop_ena = true;\n+\tinl_rq->spb_ena = rq->spb_ena;\n+\tinl_rq->spb_aura_handle = rq->spb_aura_handle;\n+\tinl_rq->spb_size = rq->spb_size;\n+\tinl_rq->spb_drop_ena = !!rq->spb_ena;\n \n \tif (!roc_model_is_cn9k()) {\n \t\tuint64_t aura_limit =\n \t\t\troc_npa_aura_op_limit_get(inl_rq->aura_handle);\n \t\tuint64_t aura_shift = plt_log2_u32(aura_limit);\n+\t\tuint64_t aura_drop, drop_pc;\n \n \t\tif (aura_shift < 8)\n \t\t\taura_shift = 0;\n \t\telse\n \t\t\taura_shift = aura_shift - 8;\n \n-\t\t/* Set first pass RQ to drop when half of the buffers are in\n+\t\t/* Set first pass RQ to drop after part of buffers are in\n \t\t * use to avoid metabuf alloc failure. This is needed as long\n-\t\t * as we cannot use different\n+\t\t * as we cannot use different aura.\n \t\t */\n-\t\tinl_rq->red_pass = (aura_limit / 2) >> aura_shift;\n-\t\tinl_rq->red_drop = ((aura_limit / 2) - 1) >> aura_shift;\n+\t\tdrop_pc = inl_dev->lpb_drop_pc;\n+\t\taura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;\n+\t\troc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true);\n+\t}\n+\n+\tif (inl_rq->spb_ena) {\n+\t\tuint64_t aura_limit =\n+\t\t\troc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);\n+\t\tuint64_t aura_shift = plt_log2_u32(aura_limit);\n+\t\tuint64_t aura_drop, drop_pc;\n+\n+\t\tif (aura_shift < 8)\n+\t\t\taura_shift = 0;\n+\t\telse\n+\t\t\taura_shift = aura_shift - 8;\n+\n+\t\t/* Set first pass RQ to drop after part of buffers are in\n+\t\t * use to avoid metabuf alloc failure. This is needed as long\n+\t\t * as we cannot use different aura.\n+\t\t */\n+\t\tdrop_pc = inl_dev->spb_drop_pc;\n+\t\taura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;\n+\t\troc_npa_aura_drop_set(inl_rq->spb_aura_handle, aura_drop, true);\n \t}\n \n \t/* Enable IPSec */\n@@ -613,6 +640,10 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)\n \tif (rc)\n \t\tplt_err(\"Failed to disable inline device rq, rc=%d\", rc);\n \n+\troc_npa_aura_drop_set(inl_rq->aura_handle, 0, false);\n+\tif (inl_rq->spb_ena)\n+\t\troc_npa_aura_drop_set(inl_rq->spb_aura_handle, 0, false);\n+\n \t/* Flush NIX LF for CN10K */\n \tnix_rq_vwqe_flush(rq, inl_dev->vwqe_interval);\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 224aaba..728225b 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -112,6 +112,8 @@ struct roc_nix_inl_dev {\n \tuint16_t chan_mask;\n \tbool attach_cptlf;\n \tbool wqe_skip;\n+\tuint8_t spb_drop_pc;\n+\tuint8_t lpb_drop_pc;\n \t/* End of input parameters */\n \n #define ROC_NIX_INL_MEM_SZ (1280)\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex 9dc0a62..4c1d85a 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -5,6 +5,8 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n+#define NIX_AURA_DROP_PC_DFLT 40\n+\n /* Default Rx Config for Inline NIX LF */\n #define NIX_INL_LF_RX_CFG \\\n \t(ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR | \\\n@@ -662,6 +664,13 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n \tinl_dev->chan_mask = roc_inl_dev->chan_mask;\n \tinl_dev->attach_cptlf = roc_inl_dev->attach_cptlf;\n \tinl_dev->wqe_skip = roc_inl_dev->wqe_skip;\n+\tinl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;\n+\tinl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;\n+\n+\tif (roc_inl_dev->spb_drop_pc)\n+\t\tinl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;\n+\tif (roc_inl_dev->lpb_drop_pc)\n+\t\tinl_dev->lpb_drop_pc = roc_inl_dev->lpb_drop_pc;\n \n \t/* Initialize base device */\n \trc = dev_init(&inl_dev->dev, pci_dev);\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex dcf752e..b6d8602 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -43,6 +43,8 @@ struct nix_inl_dev {\n \tstruct roc_nix_rq rq;\n \tuint16_t rq_refs;\n \tbool is_nix1;\n+\tuint8_t spb_drop_pc;\n+\tuint8_t lpb_drop_pc;\n \n \t/* NIX/CPT data */\n \tvoid *inb_sa_base;\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex a283d96..7d27185 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -299,7 +299,9 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \taq->rq.rq_int_ena = 0;\n \t/* Many to one reduction */\n \taq->rq.qint_idx = rq->qid % qints;\n-\taq->rq.xqe_drop_ena = 1;\n+\taq->rq.xqe_drop_ena = 0;\n+\taq->rq.lpb_drop_ena = rq->lpb_drop_ena;\n+\taq->rq.spb_drop_ena = rq->spb_drop_ena;\n \n \t/* If RED enabled, then fill enable for all cases */\n \tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n@@ -366,6 +368,8 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \t\taq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;\n \t\taq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;\n \t\taq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;\n+\t\taq->rq_mask.lpb_drop_ena = ~aq->rq_mask.lpb_drop_ena;\n+\t\taq->rq_mask.spb_drop_ena = ~aq->rq_mask.spb_drop_ena;\n \n \t\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n \t\t\taq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;\ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex 75fc224..1e60f44 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -193,6 +193,35 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle)\n \t}\n \treturn 0;\n }\n+\n+int\n+roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena)\n+{\n+\tstruct npa_aq_enq_req *aura_req;\n+\tstruct npa_lf *lf;\n+\tint rc;\n+\n+\tlf = idev_npa_obj_get();\n+\tif (lf == NULL)\n+\t\treturn NPA_ERR_DEVICE_NOT_BOUNDED;\n+\n+\taura_req = mbox_alloc_msg_npa_aq_enq(lf->mbox);\n+\tif (aura_req == NULL)\n+\t\treturn -ENOMEM;\n+\taura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n+\taura_req->ctype = NPA_AQ_CTYPE_AURA;\n+\taura_req->op = NPA_AQ_INSTOP_WRITE;\n+\n+\taura_req->aura.aura_drop_ena = ena;\n+\taura_req->aura.aura_drop = limit;\n+\taura_req->aura_mask.aura_drop_ena =\n+\t\t~(aura_req->aura_mask.aura_drop_ena);\n+\taura_req->aura_mask.aura_drop = ~(aura_req->aura_mask.aura_drop);\n+\trc = mbox_process(lf->mbox);\n+\n+\treturn rc;\n+}\n+\n static inline char *\n npa_stack_memzone_name(struct npa_lf *lf, int pool_id, char *name)\n {\n@@ -299,7 +328,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,\n \taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER);\n \taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER);\n \taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS);\n-\taura->avg_con = ROC_NPA_AVG_CONT;\n+\taura->avg_con = 0;\n \t/* Many to one reduction */\n \taura->err_qint_idx = aura_id % lf->qints;\n \n@@ -316,7 +345,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,\n \tpool->err_int_ena = BIT(NPA_POOL_ERR_INT_OVFLS);\n \tpool->err_int_ena |= BIT(NPA_POOL_ERR_INT_RANGE);\n \tpool->err_int_ena |= BIT(NPA_POOL_ERR_INT_PERR);\n-\tpool->avg_con = ROC_NPA_AVG_CONT;\n+\tpool->avg_con = 0;\n \n \t/* Many to one reduction */\n \tpool->err_qint_idx = pool_id % lf->qints;\ndiff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nindex 9f5fe5a..0339876bf 100644\n--- a/drivers/common/cnxk/roc_npa.h\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -731,4 +731,7 @@ int __roc_api roc_npa_dump(void);\n /* Reset operation performance counter. */\n int __roc_api roc_npa_pool_op_pc_reset(uint64_t aura_handle);\n \n+int __roc_api roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit,\n+\t\t\t\t bool ena);\n+\n #endif /* _ROC_NPA_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex a5ea244..7a8aff1 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -285,6 +285,7 @@ INTERNAL {\n \troc_nix_vlan_mcam_entry_write;\n \troc_nix_vlan_strip_vtag_ena_dis;\n \troc_nix_vlan_tpid_set;\n+\troc_npa_aura_drop_set;\n \troc_npa_aura_limit_modify;\n \troc_npa_aura_op_range_set;\n \troc_npa_ctx_dump;\n", "prefixes": [ "07/20" ] }