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{
    "id": 106638,
    "url": "http://patches.dpdk.org/api/patches/106638/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220127153950.812953-19-michaelba@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220127153950.812953-19-michaelba@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220127153950.812953-19-michaelba@nvidia.com",
    "date": "2022-01-27T15:39:48",
    "name": "[18/20] net/mlx5: separate per port configuration",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "caceb09aba0bc8aee863ead0d2d62667a0fad398",
    "submitter": {
        "id": 1949,
        "url": "http://patches.dpdk.org/api/people/1949/?format=api",
        "name": "Michael Baum",
        "email": "michaelba@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220127153950.812953-19-michaelba@nvidia.com/mbox/",
    "series": [
        {
            "id": 21402,
            "url": "http://patches.dpdk.org/api/series/21402/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21402",
            "date": "2022-01-27T15:39:30",
            "name": "mlx5: refactor devargs management",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/21402/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/106638/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/106638/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Michael Baum <michaelba@nvidia.com>",
        "To": "<dev@dpdk.org>",
        "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Subject": "[PATCH 18/20] net/mlx5: separate per port configuration",
        "Date": "Thu, 27 Jan 2022 17:39:48 +0200",
        "Message-ID": "<20220127153950.812953-19-michaelba@nvidia.com>",
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    },
    "content": "Add configuration structure for port (ethdev). This structure contains\nall configurations coming from devargs which oriented to port. It is a\nfield of mlx5_priv structure, and is updated in spawn function for each\nport.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c   | 121 ++------------------\n drivers/net/mlx5/mlx5.c            | 178 ++++++++++++++++++++++++-----\n drivers/net/mlx5/mlx5.h            |  21 ++--\n drivers/net/mlx5/mlx5_devx.c       |   3 +-\n drivers/net/mlx5/mlx5_ethdev.c     |   7 +-\n drivers/net/mlx5/mlx5_rxq.c        |   4 +-\n drivers/net/mlx5/mlx5_tx.c         |   2 +-\n drivers/net/mlx5/mlx5_txq.c        |   6 +-\n drivers/net/mlx5/windows/mlx5_os.c |  55 ++-------\n 9 files changed, 188 insertions(+), 209 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex c432cf0858..6979385782 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -999,8 +999,6 @@ mlx5_representor_match(struct mlx5_dev_spawn_data *spawn,\n  *   Backing DPDK device.\n  * @param spawn\n  *   Verbs device parameters (name, port, switch_info) to spawn.\n- * @param config\n- *   Device configuration parameters.\n  * @param eth_da\n  *   Device arguments.\n  *\n@@ -1014,12 +1012,10 @@ mlx5_representor_match(struct mlx5_dev_spawn_data *spawn,\n static struct rte_eth_dev *\n mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t       struct mlx5_dev_spawn_data *spawn,\n-\t       struct mlx5_dev_config *config,\n \t       struct rte_eth_devargs *eth_da)\n {\n \tconst struct mlx5_switch_info *switch_info = &spawn->info;\n \tstruct mlx5_dev_ctx_shared *sh = NULL;\n-\tstruct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr;\n \tstruct ibv_port_attr port_attr = { .state = IBV_PORT_NOP };\n \tstruct rte_eth_dev *eth_dev = NULL;\n \tstruct mlx5_priv *priv = NULL;\n@@ -1029,7 +1025,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tint own_domain_id = 0;\n \tuint16_t port_id;\n \tstruct mlx5_port_info vport_info = { .query_flags = 0 };\n-\tint nl_rdma = -1;\n+\tint nl_rdma;\n \tint i;\n \n \t/* Determine if this port representor is supposed to be spawned. */\n@@ -1107,13 +1103,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tmlx5_dev_close(eth_dev);\n \t\treturn NULL;\n \t}\n-\t/* Process parameters. */\n-\terr = mlx5_args(config, dpdk_dev->devargs);\n-\tif (err) {\n-\t\tDRV_LOG(ERR, \"failed to process device arguments: %s\",\n-\t\t\tstrerror(rte_errno));\n-\t\treturn NULL;\n-\t}\n \tsh = mlx5_alloc_shared_dev_ctx(spawn);\n \tif (!sh)\n \t\treturn NULL;\n@@ -1269,41 +1258,10 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tDRV_LOG(DEBUG, \"dev_port-%u new domain_id=%u\\n\",\n \t\t\tpriv->dev_port, priv->domain_id);\n \t}\n-\tif (config->hw_padding && !sh->dev_cap.hw_padding) {\n-\t\tDRV_LOG(DEBUG, \"Rx end alignment padding isn't supported\");\n-\t\tconfig->hw_padding = 0;\n-\t} else if (config->hw_padding) {\n-\t\tDRV_LOG(DEBUG, \"Rx end alignment padding is enabled\");\n-\t}\n-\t/*\n-\t * MPW is disabled by default, while the Enhanced MPW is enabled\n-\t * by default.\n-\t */\n-\tif (config->mps == MLX5_ARG_UNSET)\n-\t\tconfig->mps = (sh->dev_cap.mps == MLX5_MPW_ENHANCED) ?\n-\t\t\t      MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED;\n-\telse\n-\t\tconfig->mps = config->mps ? sh->dev_cap.mps : MLX5_MPW_DISABLED;\n-\tDRV_LOG(INFO, \"%sMPS is %s\",\n-\t\tconfig->mps == MLX5_MPW_ENHANCED ? \"enhanced \" :\n-\t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n-\t\tconfig->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n \tif (sh->cdev->config.devx) {\n+\t\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n+\n \t\tsh->steering_format_version = hca_attr->steering_format_version;\n-\t\t/* LRO is supported only when DV flow enabled. */\n-\t\tif (sh->dev_cap.lro_supported && sh->config.dv_flow_en)\n-\t\t\tsh->dev_cap.lro_supported = 0;\n-\t\tif (sh->dev_cap.lro_supported) {\n-\t\t\t/*\n-\t\t\t * If LRO timeout is not configured by application,\n-\t\t\t * use the minimal supported value.\n-\t\t\t */\n-\t\t\tif (!config->lro_timeout)\n-\t\t\t\tconfig->lro_timeout =\n-\t\t\t\t       hca_attr->lro_timer_supported_periods[0];\n-\t\t\tDRV_LOG(DEBUG, \"LRO session timeout set to %d usec\",\n-\t\t\t\tconfig->lro_timeout);\n-\t\t}\n #if defined(HAVE_MLX5DV_DR) && \\\n \t(defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \\\n \t defined(HAVE_MLX5_DR_CREATE_ACTION_ASO))\n@@ -1395,39 +1353,14 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t}\n #endif\n \t}\n-\tif (config->cqe_comp && !sh->dev_cap.cqe_comp) {\n-\t\tDRV_LOG(WARNING, \"Rx CQE 128B compression is not supported.\");\n-\t\tconfig->cqe_comp = 0;\n-\t}\n-\tif (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&\n-\t    (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_flow_tag)) {\n-\t\tDRV_LOG(WARNING, \"Flow Tag CQE compression\"\n-\t\t\t\t \" format isn't supported.\");\n-\t\tconfig->cqe_comp = 0;\n-\t}\n-\tif (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&\n-\t    (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) {\n-\t\tDRV_LOG(WARNING, \"L3/L4 Header CQE compression\"\n-\t\t\t\t \" format isn't supported.\");\n-\t\tconfig->cqe_comp = 0;\n-\t}\n-\tDRV_LOG(DEBUG, \"Rx CQE compression is %ssupported\",\n-\t\t\tconfig->cqe_comp ? \"\" : \"not \");\n-\tif (config->std_delay_drop || config->hp_delay_drop) {\n-\t\tif (!hca_attr->rq_delay_drop) {\n-\t\t\tconfig->std_delay_drop = 0;\n-\t\t\tconfig->hp_delay_drop = 0;\n-\t\t\tDRV_LOG(WARNING,\n-\t\t\t\t\"dev_port-%u: Rxq delay drop is not supported\",\n-\t\t\t\tpriv->dev_port);\n-\t\t}\n-\t}\n-\tif (config->mprq.enabled && !sh->dev_cap.mprq.enabled) {\n-\t\tDRV_LOG(WARNING, \"Multi-Packet RQ isn't supported.\");\n-\t\tconfig->mprq.enabled = 0;\n+\t/* Process parameters and store port configuration on priv structure. */\n+\terr = mlx5_port_args_config(priv, dpdk_dev->devargs, &priv->config);\n+\tif (err) {\n+\t\terr = rte_errno;\n+\t\tDRV_LOG(ERR, \"Failed to process port configure: %s\",\n+\t\t\tstrerror(rte_errno));\n+\t\tgoto error;\n \t}\n-\tif (config->max_dump_files_num == 0)\n-\t\tconfig->max_dump_files_num = 128;\n \teth_dev = rte_eth_dev_allocate(name);\n \tif (eth_dev == NULL) {\n \t\tDRV_LOG(ERR, \"can not allocate rte ethdev\");\n@@ -1528,10 +1461,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t * Verbs context returned by ibv_open_device().\n \t */\n \tmlx5_link_update(eth_dev, 0);\n-\t/* Detect minimal data bytes to inline. */\n-\tmlx5_set_min_inline(spawn, config);\n-\t/* Store device configuration on private structure. */\n-\tpriv->config = *config;\n \tfor (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {\n \t\ticfg[i].release_mem_en = !!sh->config.reclaim_mode;\n \t\tif (sh->config.reclaim_mode)\n@@ -1899,25 +1828,6 @@ mlx5_device_bond_pci_match(const char *ibdev_name,\n \treturn pf;\n }\n \n-static void\n-mlx5_os_config_default(struct mlx5_dev_config *config)\n-{\n-\tmemset(config, 0, sizeof(*config));\n-\tconfig->mps = MLX5_ARG_UNSET;\n-\tconfig->cqe_comp = 1;\n-\tconfig->rx_vec_en = 1;\n-\tconfig->txq_inline_max = MLX5_ARG_UNSET;\n-\tconfig->txq_inline_min = MLX5_ARG_UNSET;\n-\tconfig->txq_inline_mpw = MLX5_ARG_UNSET;\n-\tconfig->txqs_inline = MLX5_ARG_UNSET;\n-\tconfig->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;\n-\tconfig->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;\n-\tconfig->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;\n-\tconfig->log_hp_size = MLX5_ARG_UNSET;\n-\tconfig->std_delay_drop = 0;\n-\tconfig->hp_delay_drop = 0;\n-}\n-\n /**\n  * Register a PCI device within bonding.\n  *\n@@ -1966,7 +1876,6 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev,\n \tint bd = -1;\n \tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);\n \tstruct mlx5_dev_spawn_data *list = NULL;\n-\tstruct mlx5_dev_config dev_config;\n \tstruct rte_eth_devargs eth_da = *req_eth_da;\n \tstruct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */\n \tstruct mlx5_bond_info bond_info;\n@@ -2308,10 +2217,7 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev,\n \tfor (i = 0; i != ns; ++i) {\n \t\tuint32_t restore;\n \n-\t\t/* Default configuration. */\n-\t\tmlx5_os_config_default(&dev_config);\n-\t\tlist[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i],\n-\t\t\t\t\t\t &dev_config, &eth_da);\n+\t\tlist[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], &eth_da);\n \t\tif (!list[i].eth_dev) {\n \t\t\tif (rte_errno != EBUSY && rte_errno != EEXIST)\n \t\t\t\tbreak;\n@@ -2466,7 +2372,6 @@ static int\n mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev)\n {\n \tstruct rte_eth_devargs eth_da = { .nb_ports = 0 };\n-\tstruct mlx5_dev_config config;\n \tstruct mlx5_dev_spawn_data spawn = { .pf_bond = -1 };\n \tstruct rte_device *dev = cdev->dev;\n \tstruct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev);\n@@ -2477,8 +2382,6 @@ mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev)\n \tret = mlx5_os_parse_eth_devargs(dev, &eth_da);\n \tif (ret != 0)\n \t\treturn ret;\n-\t/* Set default config data. */\n-\tmlx5_os_config_default(&config);\n \t/* Init spawn data. */\n \tspawn.max_port = 1;\n \tspawn.phys_port = 1;\n@@ -2491,7 +2394,7 @@ mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev)\n \tspawn.ifindex = ret;\n \tspawn.cdev = cdev;\n \t/* Spawn device. */\n-\teth_dev = mlx5_dev_spawn(dev, &spawn, &config, &eth_da);\n+\teth_dev = mlx5_dev_spawn(dev, &spawn, &eth_da);\n \tif (eth_dev == NULL)\n \t\treturn -rte_errno;\n \t/* Post create. */\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 75ff11c357..b3601155d7 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -2101,9 +2101,9 @@ const struct eth_dev_ops mlx5_dev_ops_isolate = {\n  *   0 on success, a negative errno value otherwise and rte_errno is set.\n  */\n static int\n-mlx5_args_check(const char *key, const char *val, void *opaque)\n+mlx5_port_args_check_handler(const char *key, const char *val, void *opaque)\n {\n-\tstruct mlx5_dev_config *config = opaque;\n+\tstruct mlx5_port_config *config = opaque;\n \tsigned long tmp;\n \n \t/* No-op, port representors are processed in mlx5_dev_spawn(). */\n@@ -2197,38 +2197,156 @@ mlx5_args_check(const char *key, const char *val, void *opaque)\n }\n \n /**\n- * Parse device parameters.\n+ * Parse user port parameters and adjust them according to device capabilities.\n  *\n- * @param config\n- *   Pointer to device configuration structure.\n+ * @param priv\n+ *   Pointer to shared device context.\n  * @param devargs\n  *   Device arguments structure.\n+ * @param config\n+ *   Pointer to port configuration structure.\n  *\n  * @return\n  *   0 on success, a negative errno value otherwise and rte_errno is set.\n  */\n int\n-mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)\n+mlx5_port_args_config(struct mlx5_priv *priv, struct rte_devargs *devargs,\n+\t\t      struct mlx5_port_config *config)\n {\n \tstruct rte_kvargs *kvlist;\n+\tstruct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;\n+\tstruct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;\n+\tbool devx = priv->sh->cdev->config.devx;\n \tint ret = 0;\n \n-\tif (devargs == NULL)\n-\t\treturn 0;\n-\t/* Following UGLY cast is done to pass checkpatch. */\n-\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n-\tif (kvlist == NULL) {\n-\t\trte_errno = EINVAL;\n-\t\treturn -rte_errno;\n+\t/* Default configuration. */\n+\tmemset(config, 0, sizeof(*config));\n+\tconfig->mps = MLX5_ARG_UNSET;\n+\tconfig->cqe_comp = 1;\n+\tconfig->rx_vec_en = 1;\n+\tconfig->txq_inline_max = MLX5_ARG_UNSET;\n+\tconfig->txq_inline_min = MLX5_ARG_UNSET;\n+\tconfig->txq_inline_mpw = MLX5_ARG_UNSET;\n+\tconfig->txqs_inline = MLX5_ARG_UNSET;\n+\tconfig->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;\n+\tconfig->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;\n+\tconfig->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;\n+\tconfig->log_hp_size = MLX5_ARG_UNSET;\n+\tconfig->std_delay_drop = 0;\n+\tconfig->hp_delay_drop = 0;\n+\t/* Parse device parameters. */\n+\tif (devargs != NULL) {\n+\t\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\t\tif (kvlist == NULL) {\n+\t\t\tDRV_LOG(ERR,\n+\t\t\t\t\"Failed to parse device arguments.\");\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\t/* Process parameters. */\n+\t\tret = rte_kvargs_process(kvlist, NULL,\n+\t\t\t\t\t mlx5_port_args_check_handler, config);\n+\t\trte_kvargs_free(kvlist);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"Failed to process port arguments: %s\",\n+\t\t\t\tstrerror(rte_errno));\n+\t\t\treturn -rte_errno;\n+\t\t}\n \t}\n-\t/* Process parameters. */\n-\tret = rte_kvargs_process(kvlist, NULL, mlx5_args_check, config);\n-\tif (ret) {\n-\t\trte_errno = EINVAL;\n-\t\tret = -rte_errno;\n+\t/* Adjust parameters according to device capabilities. */\n+\tif (config->hw_padding && !dev_cap->hw_padding) {\n+\t\tDRV_LOG(DEBUG, \"Rx end alignment padding isn't supported.\");\n+\t\tconfig->hw_padding = 0;\n+\t} else if (config->hw_padding) {\n+\t\tDRV_LOG(DEBUG, \"Rx end alignment padding is enabled.\");\n \t}\n-\trte_kvargs_free(kvlist);\n-\treturn ret;\n+\t/*\n+\t * MPW is disabled by default, while the Enhanced MPW is enabled\n+\t * by default.\n+\t */\n+\tif (config->mps == MLX5_ARG_UNSET)\n+\t\tconfig->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ?\n+\t\t\t      MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED;\n+\telse\n+\t\tconfig->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED;\n+\tDRV_LOG(INFO, \"%sMPS is %s\",\n+\t\tconfig->mps == MLX5_MPW_ENHANCED ? \"enhanced \" :\n+\t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n+\t\tconfig->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n+\t/* LRO is supported only when DV flow enabled. */\n+\tif (dev_cap->lro_supported && !priv->sh->config.dv_flow_en)\n+\t\tdev_cap->lro_supported = 0;\n+\tif (dev_cap->lro_supported) {\n+\t\t/*\n+\t\t * If LRO timeout is not configured by application,\n+\t\t * use the minimal supported value.\n+\t\t */\n+\t\tif (!config->lro_timeout)\n+\t\t\tconfig->lro_timeout =\n+\t\t\t\t       hca_attr->lro_timer_supported_periods[0];\n+\t\tDRV_LOG(DEBUG, \"LRO session timeout set to %d usec.\",\n+\t\t\tconfig->lro_timeout);\n+\t}\n+\tif (config->cqe_comp && !dev_cap->cqe_comp) {\n+\t\tDRV_LOG(WARNING, \"Rx CQE 128B compression is not supported.\");\n+\t\tconfig->cqe_comp = 0;\n+\t}\n+\tif (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&\n+\t    (!devx || !hca_attr->mini_cqe_resp_flow_tag)) {\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"Flow Tag CQE compression format isn't supported.\");\n+\t\tconfig->cqe_comp = 0;\n+\t}\n+\tif (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&\n+\t    (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) {\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"L3/L4 Header CQE compression format isn't supported.\");\n+\t\tconfig->cqe_comp = 0;\n+\t}\n+\tDRV_LOG(DEBUG, \"Rx CQE compression is %ssupported.\",\n+\t\tconfig->cqe_comp ? \"\" : \"not \");\n+\tif ((config->std_delay_drop || config->hp_delay_drop) &&\n+\t    !dev_cap->rq_delay_drop_en) {\n+\t\tconfig->std_delay_drop = 0;\n+\t\tconfig->hp_delay_drop = 0;\n+\t\tDRV_LOG(WARNING, \"dev_port-%u: Rxq delay drop isn't supported.\",\n+\t\t\tpriv->dev_port);\n+\t}\n+\tif (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) {\n+\t\tDRV_LOG(WARNING, \"Multi-Packet RQ isn't supported.\");\n+\t\tconfig->mprq.enabled = 0;\n+\t}\n+\tif (config->max_dump_files_num == 0)\n+\t\tconfig->max_dump_files_num = 128;\n+\t/* Detect minimal data bytes to inline. */\n+\tmlx5_set_min_inline(priv);\n+\tDRV_LOG(DEBUG, \"VLAN insertion in WQE is %ssupported.\",\n+\t\tconfig->hw_vlan_insert ? \"\" : \"not \");\n+\tDRV_LOG(DEBUG, \"\\\"rxq_pkt_pad_en\\\" is %u.\", config->hw_padding);\n+\tDRV_LOG(DEBUG, \"\\\"rxq_cqe_comp_en\\\" is %u.\", config->cqe_comp);\n+\tDRV_LOG(DEBUG, \"\\\"cqe_comp_fmt\\\" is %u.\", config->cqe_comp_fmt);\n+\tDRV_LOG(DEBUG, \"\\\"rx_vec_en\\\" is %u.\", config->rx_vec_en);\n+\tDRV_LOG(DEBUG, \"Standard \\\"delay_drop\\\" is %u.\",\n+\t\tconfig->std_delay_drop);\n+\tDRV_LOG(DEBUG, \"Hairpin \\\"delay_drop\\\" is %u.\", config->hp_delay_drop);\n+\tDRV_LOG(DEBUG, \"\\\"max_dump_files_num\\\" is %u.\",\n+\t\tconfig->max_dump_files_num);\n+\tDRV_LOG(DEBUG, \"\\\"log_hp_size\\\" is %u.\", config->log_hp_size);\n+\tDRV_LOG(DEBUG, \"\\\"mprq_en\\\" is %u.\", config->mprq.enabled);\n+\tDRV_LOG(DEBUG, \"\\\"mprq_log_stride_num\\\" is %u.\",\n+\t\tconfig->mprq.log_stride_num);\n+\tDRV_LOG(DEBUG, \"\\\"mprq_log_stride_size\\\" is %u.\",\n+\t\tconfig->mprq.log_stride_size);\n+\tDRV_LOG(DEBUG, \"\\\"mprq_max_memcpy_len\\\" is %u.\",\n+\t\tconfig->mprq.max_memcpy_len);\n+\tDRV_LOG(DEBUG, \"\\\"rxqs_min_mprq\\\" is %u.\", config->mprq.min_rxqs_num);\n+\tDRV_LOG(DEBUG, \"\\\"lro_timeout_usec\\\" is %u.\", config->lro_timeout);\n+\tDRV_LOG(DEBUG, \"\\\"txq_mpw_en\\\" is %d.\", config->mps);\n+\tDRV_LOG(DEBUG, \"\\\"txqs_min_inline\\\" is %d.\", config->txqs_inline);\n+\tDRV_LOG(DEBUG, \"\\\"txq_inline_min\\\" is %d.\", config->txq_inline_min);\n+\tDRV_LOG(DEBUG, \"\\\"txq_inline_max\\\" is %d.\", config->txq_inline_max);\n+\tDRV_LOG(DEBUG, \"\\\"txq_inline_mpw\\\" is %d.\", config->txq_inline_mpw);\n+\treturn 0;\n }\n \n /**\n@@ -2366,21 +2484,19 @@ mlx5_probe_again_args_validate(struct mlx5_common_device *cdev)\n  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx\n  *   and none (0 bytes) for other NICs\n  *\n- * @param spawn\n- *   Verbs device parameters (name, port, switch_info) to spawn.\n- * @param config\n- *   Device configuration parameters.\n+ * @param priv\n+ *   Pointer to the private device data structure.\n  */\n void\n-mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,\n-\t\t    struct mlx5_dev_config *config)\n+mlx5_set_min_inline(struct mlx5_priv *priv)\n {\n-\tstruct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr;\n+\tstruct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;\n+\tstruct mlx5_port_config *config = &priv->config;\n \n \tif (config->txq_inline_min != MLX5_ARG_UNSET) {\n \t\t/* Application defines size of inlined data explicitly. */\n-\t\tif (spawn->pci_dev != NULL) {\n-\t\t\tswitch (spawn->pci_dev->id.device_id) {\n+\t\tif (priv->pci_dev != NULL) {\n+\t\t\tswitch (priv->pci_dev->id.device_id) {\n \t\t\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4:\n \t\t\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:\n \t\t\t\tif (config->txq_inline_min <\n@@ -2446,7 +2562,7 @@ mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,\n \t\t\t}\n \t\t}\n \t}\n-\tif (spawn->pci_dev == NULL) {\n+\tif (priv->pci_dev == NULL) {\n \t\tconfig->txq_inline_min = MLX5_INLINE_HSIZE_NONE;\n \t\tgoto exit;\n \t}\n@@ -2455,7 +2571,7 @@ mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,\n \t * inline data size with DevX. Try PCI ID\n \t * to determine old NICs.\n \t */\n-\tswitch (spawn->pci_dev->id.device_id) {\n+\tswitch (priv->pci_dev->id.device_id) {\n \tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4:\n \tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:\n \tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 46fa5131a7..95910aba1b 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -243,14 +243,13 @@ struct mlx5_stats_ctrl {\n #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)\n \n /*\n- * Device configuration structure.\n- *\n- * Merged configuration from:\n- *\n- *  - Device capabilities,\n- *  - User device parameters disabled features.\n+ * Port configuration structure.\n+ * User device parameters disabled features.\n+ * This structure contains all configurations coming from devargs which\n+ * oriented to port. When probing again, devargs doesn't have to be compatible\n+ * with primary devargs. It is updated for each port in spawn function.\n  */\n-struct mlx5_dev_config {\n+struct mlx5_port_config {\n \tunsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */\n \tunsigned int hw_padding:1; /* End alignment padding is supported. */\n \tunsigned int cqe_comp:1; /* CQE compression is enabled. */\n@@ -1450,7 +1449,7 @@ struct mlx5_priv {\n \tuint32_t link_speed_capa; /* Link speed capabilities. */\n \tstruct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */\n \tstruct mlx5_stats_ctrl stats_ctrl; /* Stats control. */\n-\tstruct mlx5_dev_config config; /* Device configuration. */\n+\tstruct mlx5_port_config config; /* Port configuration. */\n \t/* Context for Verbs allocator. */\n \tint nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */\n \tint nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */\n@@ -1539,7 +1538,6 @@ void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);\n \tfor (port_id = mlx5_eth_find_next(0, dev); \\\n \t     port_id < RTE_MAX_ETHPORTS; \\\n \t     port_id = mlx5_eth_find_next(port_id + 1, dev))\n-int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);\n void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,\n \t\t\t      struct mlx5_hca_attr *hca_attr);\n struct mlx5_dev_ctx_shared *\n@@ -1548,10 +1546,11 @@ void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);\n int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev);\n void mlx5_free_table_hash_list(struct mlx5_priv *priv);\n int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);\n-void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,\n-\t\t\t struct mlx5_dev_config *config);\n+void mlx5_set_min_inline(struct mlx5_priv *priv);\n void mlx5_set_metadata_mask(struct rte_eth_dev *dev);\n int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev);\n+int mlx5_port_args_config(struct mlx5_priv *priv, struct rte_devargs *devargs,\n+\t\t\t  struct mlx5_port_config *config);\n bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);\n int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);\n void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev);\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex de0f3672c1..e57787cfec 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -766,8 +766,7 @@ mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,\n \tmemcpy(tir_attr->rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN);\n \ttir_attr->indirect_table = ind_tbl->rqt->id;\n \tif (dev->data->dev_conf.lpbk_mode)\n-\t\ttir_attr->self_lb_block =\n-\t\t\t\t\tMLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;\n+\t\ttir_attr->self_lb_block = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;\n \tif (lro) {\n \t\ttir_attr->lro_timeout_period_usecs = priv->config.lro_timeout;\n \t\ttir_attr->lro_max_msg_sz = priv->max_lro_msg_size;\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex d637dee98d..72bf8ac914 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -266,7 +266,7 @@ static void\n mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_config *config = &priv->config;\n+\tstruct mlx5_port_config *config = &priv->config;\n \tunsigned int inlen;\n \tuint16_t nb_max;\n \n@@ -302,7 +302,6 @@ int\n mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_config *config = &priv->config;\n \tunsigned int max;\n \n \t/* FIXME: we should ask the device for these values. */\n@@ -321,8 +320,8 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n \tinfo->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES;\n \tinfo->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev);\n \tinfo->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG;\n-\tinfo->rx_seg_capa.multi_pools = !config->mprq.enabled;\n-\tinfo->rx_seg_capa.offset_allowed = !config->mprq.enabled;\n+\tinfo->rx_seg_capa.multi_pools = !priv->config.mprq.enabled;\n+\tinfo->rx_seg_capa.offset_allowed = !priv->config.mprq.enabled;\n \tinfo->rx_seg_capa.offset_align_log2 = 0;\n \tinfo->rx_offload_capa = (mlx5_get_rx_port_offloads() |\n \t\t\t\t info->rx_queue_offload_capa);\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 1d1f2556de..2625fa3308 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1562,7 +1562,7 @@ mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t  uint32_t *actual_log_stride_size)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_config *config = &priv->config;\n+\tstruct mlx5_port_config *config = &priv->config;\n \tstruct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;\n \tuint32_t log_min_stride_num = dev_cap->mprq.log_min_stride_num;\n \tuint32_t log_max_stride_num = dev_cap->mprq.log_max_stride_num;\n@@ -1681,7 +1681,7 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_rxq_ctrl *tmpl;\n \tunsigned int mb_len = rte_pktmbuf_data_room_size(rx_seg[0].mp);\n-\tstruct mlx5_dev_config *config = &priv->config;\n+\tstruct mlx5_port_config *config = &priv->config;\n \tuint64_t offloads = conf->offloads |\n \t\t\t   dev->data->dev_conf.rxmode.offloads;\n \tunsigned int lro_on_queue = !!(offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO);\ndiff --git a/drivers/net/mlx5/mlx5_tx.c b/drivers/net/mlx5/mlx5_tx.c\nindex fd2cf20967..fecec7dad7 100644\n--- a/drivers/net/mlx5/mlx5_tx.c\n+++ b/drivers/net/mlx5/mlx5_tx.c\n@@ -517,7 +517,7 @@ eth_tx_burst_t\n mlx5_select_tx_function(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_config *config = &priv->config;\n+\tstruct mlx5_port_config *config = &priv->config;\n \tuint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;\n \tunsigned int diff = 0, olx = 0, i, m;\n \ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 3373ee66b4..edbaa50692 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -100,7 +100,7 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tuint64_t offloads = (RTE_ETH_TX_OFFLOAD_MULTI_SEGS |\n \t\t\t     RTE_ETH_TX_OFFLOAD_VLAN_INSERT);\n-\tstruct mlx5_dev_config *config = &priv->config;\n+\tstruct mlx5_port_config *config = &priv->config;\n \tstruct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;\n \n \tif (dev_cap->hw_csum)\n@@ -741,7 +741,7 @@ static void\n txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)\n {\n \tstruct mlx5_priv *priv = txq_ctrl->priv;\n-\tstruct mlx5_dev_config *config = &priv->config;\n+\tstruct mlx5_port_config *config = &priv->config;\n \tstruct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;\n \tunsigned int inlen_send; /* Inline data for ordinary SEND.*/\n \tunsigned int inlen_empw; /* Inline data for enhanced MPW. */\n@@ -960,7 +960,7 @@ static int\n txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)\n {\n \tstruct mlx5_priv *priv = txq_ctrl->priv;\n-\tstruct mlx5_dev_config *config = &priv->config;\n+\tstruct mlx5_port_config *config = &priv->config;\n \tunsigned int max_inline;\n \n \tmax_inline = txq_calc_inline_max(txq_ctrl);\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 04f9590096..f511f97494 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -284,8 +284,6 @@ mlx5_os_set_nonblock_channel_fd(int fd)\n  *   Backing DPDK device.\n  * @param spawn\n  *   Verbs device parameters (name, port, switch_info) to spawn.\n- * @param config\n- *   Device configuration parameters.\n  *\n  * @return\n  *   A valid Ethernet device object on success, NULL otherwise and rte_errno\n@@ -295,8 +293,7 @@ mlx5_os_set_nonblock_channel_fd(int fd)\n  */\n static struct rte_eth_dev *\n mlx5_dev_spawn(struct rte_device *dpdk_dev,\n-\t       struct mlx5_dev_spawn_data *spawn,\n-\t       struct mlx5_dev_config *config)\n+\t       struct mlx5_dev_spawn_data *spawn)\n {\n \tconst struct mlx5_switch_info *switch_info = &spawn->info;\n \tstruct mlx5_dev_ctx_shared *sh = NULL;\n@@ -317,14 +314,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\treturn NULL;\n \t}\n \tDRV_LOG(DEBUG, \"naming Ethernet device \\\"%s\\\"\", name);\n-\t/* Process parameters. */\n-\terr = mlx5_args(config, dpdk_dev->devargs);\n-\tif (err) {\n-\t\terr = rte_errno;\n-\t\tDRV_LOG(ERR, \"failed to process device arguments: %s\",\n-\t\t\tstrerror(rte_errno));\n-\t\tgoto error;\n-\t}\n \tsh = mlx5_alloc_shared_dev_ctx(spawn);\n \tif (!sh)\n \t\treturn NULL;\n@@ -396,24 +385,14 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t}\n \t\town_domain_id = 1;\n \t}\n-\tif (config->hw_padding) {\n-\t\tDRV_LOG(DEBUG, \"Rx end alignment padding isn't supported\");\n-\t\tconfig->hw_padding = 0;\n-\t}\n-\tDRV_LOG(DEBUG, \"%sMPS is %s.\",\n-\t\tconfig->mps == MLX5_MPW_ENHANCED ? \"enhanced \" :\n-\t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n-\t\tconfig->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n-\tif (config->cqe_comp) {\n-\t\tDRV_LOG(WARNING, \"Rx CQE compression isn't supported.\");\n-\t\tconfig->cqe_comp = 0;\n-\t}\n-\tif (config->mprq.enabled) {\n-\t\tDRV_LOG(WARNING, \"Multi-Packet RQ isn't supported\");\n-\t\tconfig->mprq.enabled = 0;\n+\t/* Process parameters and store port configuration on priv structure. */\n+\terr = mlx5_port_args_config(priv, dpdk_dev->devargs, &priv->config);\n+\tif (err) {\n+\t\terr = rte_errno;\n+\t\tDRV_LOG(ERR, \"Failed to process port configure: %s\",\n+\t\t\tstrerror(rte_errno));\n+\t\tgoto error;\n \t}\n-\tif (config->max_dump_files_num == 0)\n-\t\tconfig->max_dump_files_num = 128;\n \teth_dev = rte_eth_dev_allocate(name);\n \tif (eth_dev == NULL) {\n \t\tDRV_LOG(ERR, \"can not allocate rte ethdev\");\n@@ -508,10 +487,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t * Verbs context returned by ibv_open_device().\n \t */\n \tmlx5_link_update(eth_dev, 0);\n-\t/* Detect minimal data bytes to inline. */\n-\tmlx5_set_min_inline(spawn, config);\n-\t/* Store device configuration on private structure. */\n-\tpriv->config = *config;\n \tfor (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {\n \t\ticfg[i].release_mem_en = !!sh->config.reclaim_mode;\n \t\tif (sh->config.reclaim_mode)\n@@ -817,18 +792,6 @@ mlx5_os_net_probe(struct mlx5_common_device *cdev)\n \t\t\t.name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,\n \t\t},\n \t};\n-\tstruct mlx5_dev_config dev_config = {\n-\t\t.rx_vec_en = 1,\n-\t\t.txq_inline_max = MLX5_ARG_UNSET,\n-\t\t.txq_inline_min = MLX5_ARG_UNSET,\n-\t\t.txq_inline_mpw = MLX5_ARG_UNSET,\n-\t\t.txqs_inline = MLX5_ARG_UNSET,\n-\t\t.mprq = {\n-\t\t\t.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,\n-\t\t\t.min_rxqs_num = MLX5_MPRQ_MIN_RXQS,\n-\t\t},\n-\t\t.log_hp_size = MLX5_ARG_UNSET,\n-\t};\n \tint ret;\n \tuint32_t restore;\n \n@@ -842,7 +805,7 @@ mlx5_os_net_probe(struct mlx5_common_device *cdev)\n \t\t\tstrerror(rte_errno));\n \t\treturn -rte_errno;\n \t}\n-\tspawn.eth_dev = mlx5_dev_spawn(cdev->dev, &spawn, &dev_config);\n+\tspawn.eth_dev = mlx5_dev_spawn(cdev->dev, &spawn);\n \tif (!spawn.eth_dev)\n \t\treturn -rte_errno;\n \trestore = spawn.eth_dev->data->dev_flags;\n",
    "prefixes": [
        "18/20"
    ]
}