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GET /api/patches/106632/?format=api
{ "id": 106632, "url": "http://patches.dpdk.org/api/patches/106632/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220127153950.812953-15-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220127153950.812953-15-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220127153950.812953-15-michaelba@nvidia.com", "date": "2022-01-27T15:39:44", "name": "[14/20] net/mlx5: rearrange device attribute structure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cf3d3d0d8938bbd8f2b26092fc8fabcbcdcc1dc3", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220127153950.812953-15-michaelba@nvidia.com/mbox/", "series": [ { "id": 21402, "url": "http://patches.dpdk.org/api/series/21402/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21402", "date": "2022-01-27T15:39:30", "name": "mlx5: refactor devargs management", "version": 1, "mbox": "http://patches.dpdk.org/series/21402/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/106632/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/106632/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E125CA04A6;\n\tThu, 27 Jan 2022 16:41:48 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 79538428DE;\n\tThu, 27 Jan 2022 16:40:27 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2067.outbound.protection.outlook.com [40.107.236.67])\n by mails.dpdk.org (Postfix) with ESMTP id 68691428DB\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH 14/20] net/mlx5: rearrange device attribute structure", "Date": "Thu, 27 Jan 2022 17:39:44 +0200", "Message-ID": "<20220127153950.812953-15-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220127153950.812953-1-michaelba@nvidia.com>", "References": "<20220127153950.812953-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "bb98ec12-13d2-4e17-e2fb-08d9e1ab5557", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB4799:EE_", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB4799A472625FD9B1D7C2A3DFCC219@MN2PR12MB4799.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:82;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n qRtSpJsNZTwTn2NITWV6CccH6Dwni8v0vg9qz+kpJcWLte8Kv0UtXZTSV3couzv2RDfMJNTKCztNlEC/WqSSl8/DfQKtvnDTBk34/BqMnjE9VSGSjZ2vRi+F6LQjhirRG1BhuvBCtMCd8Tngj/MhBIRBdQQsD6AzyEzLUKq65Kq/F7u1HLuMeFpUNnC8tiisuv0Th2+8DwujSPXM9WtsTQC0qtXpspy+baCQ5ikLI5urZNPrejNYh9H1QGFmi72R9VF+tr9rZJPpEr5LkcJ7g1LR/Ur1xZnvy6gyVLhrIzmcaUzQCvswHYs3qKYt6aPTEENPil1Z5o1ys2J5YHOZrTnOg1rmurqnst9S+9zavn29r8Owl5DdXa5fIoKjPT55eI2PnDjzeAprhr6TG/d5R6YzW1Z0BT1oDsESgaWCfVvVEiiNfca3Qgqd9KtdUbkPUuW2acWNXdStNTIJy5No5Q/TwGOzNMI8PJi8R6gZEQMMbo9JfL8g0eYYZIdVaa+6+Tvsh6HURsG1KBK82ViU+1sZBqDchZV5/dvlyoJeQsImXEliVtpbUdSEQjP8wNhzX/Ez10LZdjbTS2pzUVhkeeF6Vfag6/npUCuHozBGnJSJS5zMpiH4TnHiFRMAZuTK2MMIiwjOW6bMo/I7OOOf3SXQjFrW7jsyJdAJpvt4IAevEvGukcu+6+ueaMb12iUpbpiPUJgMolOy7Sdp0Dg/uDoiTSjNXiO65e9ivMjAueQa5vzYp1ZsFAmSsPVy070NXik3FVVPz5Fyrz9X3p9XfU01Uoz5207Q5nVJhsTgzJNr92aY8O+iT82eUAHhCBO4iFi3Toe+1dMW2tpYXX2u7Q==", "X-Forefront-Antispam-Report": "CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(4636009)(46966006)(40470700004)(36840700001)(36756003)(81166007)(6666004)(1076003)(83380400001)(36860700001)(55016003)(356005)(5660300002)(86362001)(336012)(30864003)(2906002)(70206006)(26005)(82310400004)(8936002)(47076005)(6286002)(4326008)(7696005)(40460700003)(316002)(107886003)(426003)(6916009)(2616005)(8676002)(508600001)(70586007)(54906003)(186003)(36900700001)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Jan 2022 15:40:23.5397 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bb98ec12-13d2-4e17-e2fb-08d9e1ab5557", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT024.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4799", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Rearrange the mlx5_os_get_dev_attr() function in such a way that it\nfirst executes the queries and only then updates the fields.\nIn addition, it changed its name in preparation for expanding its\noperations to configure the capabilities inside it.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 122 +++++++++++++---------------\n drivers/net/mlx5/linux/mlx5_verbs.c | 5 +-\n drivers/net/mlx5/mlx5.c | 4 +-\n drivers/net/mlx5/mlx5.h | 56 ++++++-------\n drivers/net/mlx5/mlx5_devx.c | 2 +-\n drivers/net/mlx5/mlx5_ethdev.c | 5 +-\n drivers/net/mlx5/mlx5_trigger.c | 8 +-\n drivers/net/mlx5/mlx5_txq.c | 18 ++--\n drivers/net/mlx5/windows/mlx5_os.c | 67 ++++++---------\n 9 files changed, 127 insertions(+), 160 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 47b088db83..b6848fc34c 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -131,46 +131,25 @@ mlx5_os_set_nonblock_channel_fd(int fd)\n * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5\n * device attributes from the glue out parameter.\n *\n- * @param cdev\n- * Pointer to mlx5 device.\n- *\n- * @param device_attr\n- * Pointer to mlx5 device attributes.\n+ * @param sh\n+ * Pointer to shared device context.\n *\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n int\n-mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,\n-\t\t struct mlx5_dev_attr *device_attr)\n+mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)\n {\n \tint err;\n-\tstruct ibv_context *ctx = cdev->ctx;\n+\tstruct ibv_context *ctx = sh->cdev->ctx;\n \tstruct ibv_device_attr_ex attr_ex;\n+\tstruct mlx5dv_context dv_attr = { .comp_mask = 0 };\n \n-\tmemset(device_attr, 0, sizeof(*device_attr));\n \terr = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex);\n \tif (err) {\n \t\trte_errno = errno;\n \t\treturn -rte_errno;\n \t}\n-\tdevice_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex;\n-\tdevice_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr;\n-\tdevice_attr->max_sge = attr_ex.orig_attr.max_sge;\n-\tdevice_attr->max_cq = attr_ex.orig_attr.max_cq;\n-\tdevice_attr->max_cqe = attr_ex.orig_attr.max_cqe;\n-\tdevice_attr->max_mr = attr_ex.orig_attr.max_mr;\n-\tdevice_attr->max_pd = attr_ex.orig_attr.max_pd;\n-\tdevice_attr->max_qp = attr_ex.orig_attr.max_qp;\n-\tdevice_attr->max_srq = attr_ex.orig_attr.max_srq;\n-\tdevice_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr;\n-\tdevice_attr->raw_packet_caps = attr_ex.raw_packet_caps;\n-\tdevice_attr->max_rwq_indirection_table_size =\n-\t\tattr_ex.rss_caps.max_rwq_indirection_table_size;\n-\tdevice_attr->max_tso = attr_ex.tso_caps.max_tso;\n-\tdevice_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts;\n-\n-\tstruct mlx5dv_context dv_attr = { .comp_mask = 0 };\n #ifdef HAVE_IBV_MLX5_MOD_SWP\n \tdv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;\n #endif\n@@ -185,31 +164,40 @@ mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,\n \t\trte_errno = errno;\n \t\treturn -rte_errno;\n \t}\n-\n-\tdevice_attr->flags = dv_attr.flags;\n-\tdevice_attr->comp_mask = dv_attr.comp_mask;\n+\tmemset(&sh->dev_cap, 0, sizeof(struct mlx5_dev_cap));\n+\tsh->dev_cap.device_cap_flags_ex = attr_ex.device_cap_flags_ex;\n+\tsh->dev_cap.max_qp_wr = attr_ex.orig_attr.max_qp_wr;\n+\tsh->dev_cap.max_sge = attr_ex.orig_attr.max_sge;\n+\tsh->dev_cap.max_cq = attr_ex.orig_attr.max_cq;\n+\tsh->dev_cap.max_qp = attr_ex.orig_attr.max_qp;\n+\tsh->dev_cap.raw_packet_caps = attr_ex.raw_packet_caps;\n+\tsh->dev_cap.max_rwq_indirection_table_size =\n+\t\tattr_ex.rss_caps.max_rwq_indirection_table_size;\n+\tsh->dev_cap.max_tso = attr_ex.tso_caps.max_tso;\n+\tsh->dev_cap.tso_supported_qpts = attr_ex.tso_caps.supported_qpts;\n+\tstrlcpy(sh->dev_cap.fw_ver, attr_ex.orig_attr.fw_ver,\n+\t\tsizeof(sh->dev_cap.fw_ver));\n+\tsh->dev_cap.flags = dv_attr.flags;\n+\tsh->dev_cap.comp_mask = dv_attr.comp_mask;\n #ifdef HAVE_IBV_MLX5_MOD_SWP\n-\tdevice_attr->sw_parsing_offloads =\n+\tsh->dev_cap.sw_parsing_offloads =\n \t\tdv_attr.sw_parsing_caps.sw_parsing_offloads;\n #endif\n #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n-\tdevice_attr->min_single_stride_log_num_of_bytes =\n+\tsh->dev_cap.min_single_stride_log_num_of_bytes =\n \t\tdv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes;\n-\tdevice_attr->max_single_stride_log_num_of_bytes =\n+\tsh->dev_cap.max_single_stride_log_num_of_bytes =\n \t\tdv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes;\n-\tdevice_attr->min_single_wqe_log_num_of_strides =\n+\tsh->dev_cap.min_single_wqe_log_num_of_strides =\n \t\tdv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides;\n-\tdevice_attr->max_single_wqe_log_num_of_strides =\n+\tsh->dev_cap.max_single_wqe_log_num_of_strides =\n \t\tdv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides;\n-\tdevice_attr->stride_supported_qpts =\n+\tsh->dev_cap.stride_supported_qpts =\n \t\tdv_attr.striding_rq_caps.supported_qpts;\n #endif\n #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n-\tdevice_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps;\n+\tsh->dev_cap.tunnel_offloads_caps = dv_attr.tunnel_offloads_caps;\n #endif\n-\tstrlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver,\n-\t\tsizeof(device_attr->fw_ver));\n-\n \treturn 0;\n }\n \n@@ -983,8 +971,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t * Multi-packet send is supported by ConnectX-4 Lx PF as well\n \t * as all ConnectX-5 devices.\n \t */\n-\tif (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {\n-\t\tif (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {\n+\tif (sh->dev_cap.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {\n+\t\tif (sh->dev_cap.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {\n \t\t\tDRV_LOG(DEBUG, \"enhanced MPW is supported\");\n \t\t\tmps = MLX5_MPW_ENHANCED;\n \t\t} else {\n@@ -996,41 +984,41 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tmps = MLX5_MPW_DISABLED;\n \t}\n #ifdef HAVE_IBV_MLX5_MOD_SWP\n-\tif (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)\n-\t\tswp = sh->device_attr.sw_parsing_offloads;\n+\tif (sh->dev_cap.comp_mask & MLX5DV_CONTEXT_MASK_SWP)\n+\t\tswp = sh->dev_cap.sw_parsing_offloads;\n \tDRV_LOG(DEBUG, \"SWP support: %u\", swp);\n #endif\n \tconfig->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |\n \t\tMLX5_SW_PARSING_TSO_CAP);\n #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n-\tif (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {\n+\tif (sh->dev_cap.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {\n \t\tDRV_LOG(DEBUG, \"\\tmin_single_stride_log_num_of_bytes: %d\",\n-\t\t\tsh->device_attr.min_single_stride_log_num_of_bytes);\n+\t\t\tsh->dev_cap.min_single_stride_log_num_of_bytes);\n \t\tDRV_LOG(DEBUG, \"\\tmax_single_stride_log_num_of_bytes: %d\",\n-\t\t\tsh->device_attr.max_single_stride_log_num_of_bytes);\n+\t\t\tsh->dev_cap.max_single_stride_log_num_of_bytes);\n \t\tDRV_LOG(DEBUG, \"\\tmin_single_wqe_log_num_of_strides: %d\",\n-\t\t\tsh->device_attr.min_single_wqe_log_num_of_strides);\n+\t\t\tsh->dev_cap.min_single_wqe_log_num_of_strides);\n \t\tDRV_LOG(DEBUG, \"\\tmax_single_wqe_log_num_of_strides: %d\",\n-\t\t\tsh->device_attr.max_single_wqe_log_num_of_strides);\n+\t\t\tsh->dev_cap.max_single_wqe_log_num_of_strides);\n \t\tDRV_LOG(DEBUG, \"\\tsupported_qpts: %d\",\n-\t\t\tsh->device_attr.stride_supported_qpts);\n+\t\t\tsh->dev_cap.stride_supported_qpts);\n \t\tDRV_LOG(DEBUG, \"\\tmin_stride_wqe_log_size: %d\",\n \t\t\tconfig->mprq.log_min_stride_wqe_size);\n \t\tDRV_LOG(DEBUG, \"device supports Multi-Packet RQ\");\n \t\tmprq = 1;\n \t\tconfig->mprq.log_min_stride_size =\n-\t\t\tsh->device_attr.min_single_stride_log_num_of_bytes;\n+\t\t\tsh->dev_cap.min_single_stride_log_num_of_bytes;\n \t\tconfig->mprq.log_max_stride_size =\n-\t\t\tsh->device_attr.max_single_stride_log_num_of_bytes;\n+\t\t\tsh->dev_cap.max_single_stride_log_num_of_bytes;\n \t\tconfig->mprq.log_min_stride_num =\n-\t\t\tsh->device_attr.min_single_wqe_log_num_of_strides;\n+\t\t\tsh->dev_cap.min_single_wqe_log_num_of_strides;\n \t\tconfig->mprq.log_max_stride_num =\n-\t\t\tsh->device_attr.max_single_wqe_log_num_of_strides;\n+\t\t\tsh->dev_cap.max_single_wqe_log_num_of_strides;\n \t}\n #endif\n #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n-\tif (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {\n-\t\tconfig->tunnel_en = sh->device_attr.tunnel_offloads_caps &\n+\tif (sh->dev_cap.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {\n+\t\tconfig->tunnel_en = sh->dev_cap.tunnel_offloads_caps &\n \t\t\t (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN |\n \t\t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE |\n \t\t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE);\n@@ -1052,9 +1040,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\"tunnel offloading disabled due to old OFED/rdma-core version\");\n #endif\n #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT\n-\tmpls_en = ((sh->device_attr.tunnel_offloads_caps &\n+\tmpls_en = ((sh->dev_cap.tunnel_offloads_caps &\n \t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&\n-\t\t (sh->device_attr.tunnel_offloads_caps &\n+\t\t (sh->dev_cap.tunnel_offloads_caps &\n \t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));\n \tDRV_LOG(DEBUG, \"MPLS over GRE/UDP tunnel offloading is %ssupported\",\n \t\tmpls_en ? \"\" : \"not \");\n@@ -1215,7 +1203,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tDRV_LOG(DEBUG, \"dev_port-%u new domain_id=%u\\n\",\n \t\t\tpriv->dev_port, priv->domain_id);\n \t}\n-\tconfig->hw_csum = !!(sh->device_attr.device_cap_flags_ex &\n+\tconfig->hw_csum = !!(sh->dev_cap.device_cap_flags_ex &\n \t\t\t IBV_DEVICE_RAW_IP_CSUM);\n \tDRV_LOG(DEBUG, \"checksum offloading is %ssupported\",\n \t\t(config->hw_csum ? \"\" : \"not \"));\n@@ -1224,7 +1212,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tDRV_LOG(DEBUG, \"counters are not supported\");\n #endif\n \tconfig->ind_table_max_size =\n-\t\tsh->device_attr.max_rwq_indirection_table_size;\n+\t\tsh->dev_cap.max_rwq_indirection_table_size;\n \t/*\n \t * Remove this check once DPDK supports larger/variable\n \t * indirection tables.\n@@ -1233,16 +1221,16 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512;\n \tDRV_LOG(DEBUG, \"maximum Rx indirection table size is %u\",\n \t\tconfig->ind_table_max_size);\n-\tconfig->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &\n+\tconfig->hw_vlan_strip = !!(sh->dev_cap.raw_packet_caps &\n \t\t\t\t IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);\n \tDRV_LOG(DEBUG, \"VLAN stripping is %ssupported\",\n \t\t(config->hw_vlan_strip ? \"\" : \"not \"));\n-\tconfig->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &\n+\tconfig->hw_fcs_strip = !!(sh->dev_cap.raw_packet_caps &\n \t\t\t\t IBV_RAW_PACKET_CAP_SCATTER_FCS);\n #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)\n-\thw_padding = !!sh->device_attr.rx_pad_end_addr_align;\n+\thw_padding = !!sh->dev_cap.rx_pad_end_addr_align;\n #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)\n-\thw_padding = !!(sh->device_attr.device_cap_flags_ex &\n+\thw_padding = !!(sh->dev_cap.device_cap_flags_ex &\n \t\t\tIBV_DEVICE_PCI_WRITE_END_PADDING);\n #endif\n \tif (config->hw_padding && !hw_padding) {\n@@ -1251,11 +1239,11 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t} else if (config->hw_padding) {\n \t\tDRV_LOG(DEBUG, \"Rx end alignment padding is enabled\");\n \t}\n-\tconfig->tso = (sh->device_attr.max_tso > 0 &&\n-\t\t (sh->device_attr.tso_supported_qpts &\n+\tconfig->tso = (sh->dev_cap.max_tso > 0 &&\n+\t\t (sh->dev_cap.tso_supported_qpts &\n \t\t (1 << IBV_QPT_RAW_PACKET)));\n \tif (config->tso)\n-\t\tconfig->tso_max_payload_sz = sh->device_attr.max_tso;\n+\t\tconfig->tso_max_payload_sz = sh->dev_cap.max_tso;\n \t/*\n \t * MPW is disabled by default, while the Enhanced MPW is enabled\n \t * by default.\n@@ -1382,7 +1370,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n #endif\n \t}\n \tif (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 &&\n-\t !(sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) {\n+\t !(sh->dev_cap.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) {\n \t\tDRV_LOG(WARNING, \"Rx CQE 128B compression is not supported\");\n \t\tconfig->cqe_comp = 0;\n \t}\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex 722017efa4..73c44138de 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -872,13 +872,12 @@ mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx)\n \t/* CQ to be associated with the receive queue. */\n \tqp_attr.recv_cq = txq_ctrl->obj->cq;\n \t/* Max number of outstanding WRs. */\n-\tqp_attr.cap.max_send_wr = ((priv->sh->device_attr.max_qp_wr < desc) ?\n-\t\t\t\t priv->sh->device_attr.max_qp_wr : desc);\n+\tqp_attr.cap.max_send_wr = RTE_MIN(priv->sh->dev_cap.max_qp_wr, desc);\n \t/*\n \t * Max number of scatter/gather elements in a WR, must be 1 to prevent\n \t * libmlx5 from trying to affect must be 1 to prevent libmlx5 from\n \t * trying to affect too much memory. TX gather is not impacted by the\n-\t * device_attr.max_sge limit and will still work properly.\n+\t * dev_cap.max_sge limit and will still work properly.\n \t */\n \tqp_attr.cap.max_send_sge = 1;\n \tqp_attr.qp_type = IBV_QPT_RAW_PACKET,\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex e1fe8f9375..b33dc0e7b4 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1262,9 +1262,9 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \tsh->esw_mode = !!(spawn->info.master || spawn->info.representor);\n \tif (spawn->bond_info)\n \t\tsh->bond = *spawn->bond_info;\n-\terr = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);\n+\terr = mlx5_os_capabilities_prepare(sh);\n \tif (err) {\n-\t\tDRV_LOG(DEBUG, \"mlx5_os_get_dev_attr() failed\");\n+\t\tDRV_LOG(ERR, \"Fail to configure device capabilities.\");\n \t\tgoto error;\n \t}\n \tsh->refcnt = 1;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex a713e61572..fd6350eee7 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -114,32 +114,31 @@ struct mlx5_flow_cb_ctx {\n \tvoid *data2;\n };\n \n-/* Device attributes used in mlx5 PMD */\n-struct mlx5_dev_attr {\n-\tuint64_t\tdevice_cap_flags_ex;\n-\tint\t\tmax_qp_wr;\n-\tint\t\tmax_sge;\n-\tint\t\tmax_cq;\n-\tint\t\tmax_qp;\n-\tint\t\tmax_cqe;\n-\tuint32_t\tmax_pd;\n-\tuint32_t\tmax_mr;\n-\tuint32_t\tmax_srq;\n-\tuint32_t\tmax_srq_wr;\n-\tuint32_t\traw_packet_caps;\n-\tuint32_t\tmax_rwq_indirection_table_size;\n-\tuint32_t\tmax_tso;\n-\tuint32_t\ttso_supported_qpts;\n-\tuint64_t\tflags;\n-\tuint64_t\tcomp_mask;\n-\tuint32_t\tsw_parsing_offloads;\n-\tuint32_t\tmin_single_stride_log_num_of_bytes;\n-\tuint32_t\tmax_single_stride_log_num_of_bytes;\n-\tuint32_t\tmin_single_wqe_log_num_of_strides;\n-\tuint32_t\tmax_single_wqe_log_num_of_strides;\n-\tuint32_t\tstride_supported_qpts;\n-\tuint32_t\ttunnel_offloads_caps;\n-\tchar\t\tfw_ver[64];\n+/* Device capabilities structure which isn't changed in any stage. */\n+struct mlx5_dev_cap {\n+\tuint64_t device_cap_flags_ex;\n+\tint max_cq; /* Maximum number of supported CQs */\n+\tint max_qp; /* Maximum number of supported QPs. */\n+\tint max_qp_wr; /* Maximum number of outstanding WR on any WQ. */\n+\tint max_sge;\n+\t/* Maximum number of s/g per WR for SQ & RQ of QP for non RDMA Read\n+\t * operations.\n+\t */\n+\tuint32_t raw_packet_caps;\n+\tuint32_t max_rwq_indirection_table_size;\n+\t/* Maximum receive WQ indirection table size. */\n+\tuint32_t max_tso; /* Maximum TCP payload for TSO. */\n+\tuint32_t tso_supported_qpts;\n+\tuint64_t flags;\n+\tuint64_t comp_mask;\n+\tuint32_t sw_parsing_offloads;\n+\tuint32_t min_single_stride_log_num_of_bytes;\n+\tuint32_t max_single_stride_log_num_of_bytes;\n+\tuint32_t min_single_wqe_log_num_of_strides;\n+\tuint32_t max_single_wqe_log_num_of_strides;\n+\tuint32_t stride_supported_qpts;\n+\tuint32_t tunnel_offloads_caps;\n+\tchar fw_ver[64]; /* Firmware version of this device. */\n };\n \n /** Data associated with devices to spawn. */\n@@ -1165,7 +1164,7 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t tdn; /* Transport Domain number. */\n \tchar ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */\n \tchar ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */\n-\tstruct mlx5_dev_attr device_attr; /* Device properties. */\n+\tstruct mlx5_dev_cap dev_cap; /* Device capabilities. */\n \tint numa_node; /* Numa node of backing physical device. */\n \t/* Packet pacing related structure. */\n \tstruct mlx5_dev_txpp txpp;\n@@ -1792,8 +1791,7 @@ void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev);\n /* mlx5_os.c */\n \n struct rte_pci_driver;\n-int mlx5_os_get_dev_attr(struct mlx5_common_device *dev,\n-\t\t\t struct mlx5_dev_attr *dev_attr);\n+int mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh);\n void mlx5_os_free_shared_dr(struct mlx5_priv *priv);\n int mlx5_os_net_probe(struct mlx5_common_device *cdev);\n void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 97c8925044..553df6424d 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -1305,7 +1305,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \twqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE;\n \t/* Create Send Queue object with DevX. */\n \twqe_n = RTE_MIN((1UL << txq_data->elts_n) * wqe_size,\n-\t\t\t(uint32_t)priv->sh->device_attr.max_qp_wr);\n+\t\t\t(uint32_t)priv->sh->dev_cap.max_qp_wr);\n \tlog_desc_n = log2above(wqe_n);\n \tret = mlx5_txq_create_devx_sq_resources(dev, idx, log_desc_n);\n \tif (ret) {\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 06d5acb75f..d970eb6904 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -313,8 +313,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n \t * Since we need one CQ per QP, the limit is the minimum number\n \t * between the two values.\n \t */\n-\tmax = RTE_MIN(priv->sh->device_attr.max_cq,\n-\t\t priv->sh->device_attr.max_qp);\n+\tmax = RTE_MIN(priv->sh->dev_cap.max_cq, priv->sh->dev_cap.max_qp);\n \t/* max_rx_queues is uint16_t. */\n \tmax = RTE_MIN(max, (unsigned int)UINT16_MAX);\n \tinfo->max_rx_queues = max;\n@@ -516,7 +515,7 @@ int\n mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_attr *attr = &priv->sh->device_attr;\n+\tstruct mlx5_dev_cap *attr = &priv->sh->dev_cap;\n \tsize_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1;\n \n \tif (fw_size < size)\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex d128b3e978..cd8c451286 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -215,10 +215,10 @@ mlx5_rxq_start(struct rte_eth_dev *dev)\n \t\t/* Should not release Rx queues but return immediately. */\n \t\treturn -rte_errno;\n \t}\n-\tDRV_LOG(DEBUG, \"Port %u device_attr.max_qp_wr is %d.\",\n-\t\tdev->data->port_id, priv->sh->device_attr.max_qp_wr);\n-\tDRV_LOG(DEBUG, \"Port %u device_attr.max_sge is %d.\",\n-\t\tdev->data->port_id, priv->sh->device_attr.max_sge);\n+\tDRV_LOG(DEBUG, \"Port %u dev_cap.max_qp_wr is %d.\",\n+\t\tdev->data->port_id, priv->sh->dev_cap.max_qp_wr);\n+\tDRV_LOG(DEBUG, \"Port %u dev_cap.max_sge is %d.\",\n+\t\tdev->data->port_id, priv->sh->dev_cap.max_sge);\n \tfor (i = 0; i != priv->rxqs_n; ++i) {\n \t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_ref(dev, i);\n \t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 4e0bf7af9c..56e0937ca3 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -714,7 +714,7 @@ txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)\n \tstruct mlx5_priv *priv = txq_ctrl->priv;\n \tunsigned int wqe_size;\n \n-\twqe_size = priv->sh->device_attr.max_qp_wr / desc;\n+\twqe_size = priv->sh->dev_cap.max_qp_wr / desc;\n \tif (!wqe_size)\n \t\treturn 0;\n \t/*\n@@ -982,8 +982,7 @@ txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)\n \t\t\t\" satisfied (%u) on port %u, try the smaller\"\n \t\t\t\" Tx queue size (%d)\",\n \t\t\ttxq_ctrl->txq.inlen_mode, max_inline,\n-\t\t\tpriv->dev_data->port_id,\n-\t\t\tpriv->sh->device_attr.max_qp_wr);\n+\t\t\tpriv->dev_data->port_id, priv->sh->dev_cap.max_qp_wr);\n \t\tgoto error;\n \t}\n \tif (txq_ctrl->txq.inlen_send > max_inline &&\n@@ -994,8 +993,7 @@ txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)\n \t\t\t\" satisfied (%u) on port %u, try the smaller\"\n \t\t\t\" Tx queue size (%d)\",\n \t\t\ttxq_ctrl->txq.inlen_send, max_inline,\n-\t\t\tpriv->dev_data->port_id,\n-\t\t\tpriv->sh->device_attr.max_qp_wr);\n+\t\t\tpriv->dev_data->port_id, priv->sh->dev_cap.max_qp_wr);\n \t\tgoto error;\n \t}\n \tif (txq_ctrl->txq.inlen_empw > max_inline &&\n@@ -1006,8 +1004,7 @@ txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)\n \t\t\t\" satisfied (%u) on port %u, try the smaller\"\n \t\t\t\" Tx queue size (%d)\",\n \t\t\ttxq_ctrl->txq.inlen_empw, max_inline,\n-\t\t\tpriv->dev_data->port_id,\n-\t\t\tpriv->sh->device_attr.max_qp_wr);\n+\t\t\tpriv->dev_data->port_id, priv->sh->dev_cap.max_qp_wr);\n \t\tgoto error;\n \t}\n \tif (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {\n@@ -1016,8 +1013,7 @@ txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)\n \t\t\t\" satisfied (%u) on port %u, try the smaller\"\n \t\t\t\" Tx queue size (%d)\",\n \t\t\tMLX5_MAX_TSO_HEADER, max_inline,\n-\t\t\tpriv->dev_data->port_id,\n-\t\t\tpriv->sh->device_attr.max_qp_wr);\n+\t\t\tpriv->dev_data->port_id, priv->sh->dev_cap.max_qp_wr);\n \t\tgoto error;\n \t}\n \tif (txq_ctrl->txq.inlen_send > max_inline) {\n@@ -1098,12 +1094,12 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \tif (txq_adjust_params(tmpl))\n \t\tgoto error;\n \tif (txq_calc_wqebb_cnt(tmpl) >\n-\t priv->sh->device_attr.max_qp_wr) {\n+\t priv->sh->dev_cap.max_qp_wr) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"port %u Tx WQEBB count (%d) exceeds the limit (%d),\"\n \t\t\t\" try smaller queue size\",\n \t\t\tdev->data->port_id, txq_calc_wqebb_cnt(tmpl),\n-\t\t\tpriv->sh->device_attr.max_qp_wr);\n+\t\t\tpriv->sh->dev_cap.max_qp_wr);\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex eaa63ad50f..16fd54091e 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -143,55 +143,42 @@ mlx5_init_once(void)\n }\n \n /**\n- * Get mlx5 device attributes.\n+ * Get mlx5 device capabilities.\n *\n- * @param cdev\n- * Pointer to mlx5 device.\n- *\n- * @param device_attr\n- * Pointer to mlx5 device attributes.\n+ * @param sh\n+ * Pointer to shared device context.\n *\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n int\n-mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,\n-\t\t struct mlx5_dev_attr *device_attr)\n+mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)\n {\n-\tstruct mlx5_context *mlx5_ctx;\n+\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n+\tstruct mlx5_context *mlx5_ctx = sh->cdev->ctx;\n \tvoid *pv_iseg = NULL;\n \tu32 cb_iseg = 0;\n \n-\tif (!cdev || !cdev->ctx) {\n-\t\trte_errno = EINVAL;\n-\t\treturn -rte_errno;\n-\t}\n-\tmlx5_ctx = (struct mlx5_context *)cdev->ctx;\n-\tmemset(device_attr, 0, sizeof(*device_attr));\n-\tdevice_attr->max_cq = 1 << cdev->config.hca_attr.log_max_cq;\n-\tdevice_attr->max_qp = 1 << cdev->config.hca_attr.log_max_qp;\n-\tdevice_attr->max_qp_wr = 1 << cdev->config.hca_attr.log_max_qp_sz;\n-\tdevice_attr->max_cqe = 1 << cdev->config.hca_attr.log_max_cq_sz;\n-\tdevice_attr->max_mr = 1 << cdev->config.hca_attr.log_max_mrw_sz;\n-\tdevice_attr->max_pd = 1 << cdev->config.hca_attr.log_max_pd;\n-\tdevice_attr->max_srq = 1 << cdev->config.hca_attr.log_max_srq;\n-\tdevice_attr->max_srq_wr = 1 << cdev->config.hca_attr.log_max_srq_sz;\n-\tdevice_attr->max_tso = 1 << cdev->config.hca_attr.max_lso_cap;\n-\tif (cdev->config.hca_attr.rss_ind_tbl_cap) {\n-\t\tdevice_attr->max_rwq_indirection_table_size =\n-\t\t\t1 << cdev->config.hca_attr.rss_ind_tbl_cap;\n-\t}\n-\tdevice_attr->sw_parsing_offloads =\n-\t\tmlx5_get_supported_sw_parsing_offloads(&cdev->config.hca_attr);\n-\tdevice_attr->tunnel_offloads_caps =\n-\t\tmlx5_get_supported_tunneling_offloads(&cdev->config.hca_attr);\n \tpv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);\n \tif (pv_iseg == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to get device hca_iseg\");\n+\t\tDRV_LOG(ERR, \"Failed to get device hca_iseg.\");\n \t\trte_errno = errno;\n \t\treturn -rte_errno;\n \t}\n-\tsnprintf(device_attr->fw_ver, 64, \"%x.%x.%04x\",\n+\tmemset(&sh->dev_cap, 0, sizeof(struct mlx5_dev_cap));\n+\tsh->dev_cap.max_cq = 1 << hca_attr->log_max_cq;\n+\tsh->dev_cap.max_qp = 1 << hca_attr->log_max_qp;\n+\tsh->dev_cap.max_qp_wr = 1 << hca_attr->log_max_qp_sz;\n+\tsh->dev_cap.max_tso = 1 << hca_attr->max_lso_cap;\n+\tif (hca_attr->rss_ind_tbl_cap) {\n+\t\tsh->dev_cap.max_rwq_indirection_table_size =\n+\t\t\t1 << hca_attr->rss_ind_tbl_cap;\n+\t}\n+\tsh->dev_cap.sw_parsing_offloads =\n+\t\tmlx5_get_supported_sw_parsing_offloads(hca_attr);\n+\tsh->dev_cap.tunnel_offloads_caps =\n+\t\tmlx5_get_supported_tunneling_offloads(hca_attr);\n+\tsnprintf(sh->dev_cap.fw_ver, 64, \"%x.%x.%04x\",\n \t\t MLX5_GET(initial_seg, pv_iseg, fw_rev_major),\n \t\t MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),\n \t\t MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));\n@@ -335,12 +322,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tgoto error;\n \t}\n \tDRV_LOG(DEBUG, \"MPW isn't supported\");\n-\tconfig->swp = sh->device_attr.sw_parsing_offloads &\n+\tconfig->swp = sh->dev_cap.sw_parsing_offloads &\n \t\t(MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |\n \t\t MLX5_SW_PARSING_TSO_CAP);\n \tconfig->ind_table_max_size =\n-\t\tsh->device_attr.max_rwq_indirection_table_size;\n-\tconfig->tunnel_en = sh->device_attr.tunnel_offloads_caps &\n+\t\tsh->dev_cap.max_rwq_indirection_table_size;\n+\tconfig->tunnel_en = sh->dev_cap.tunnel_offloads_caps &\n \t\t(MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |\n \t\t MLX5_TUNNELED_OFFLOADS_GRE_CAP |\n \t\t MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);\n@@ -410,7 +397,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t}\n \tDRV_LOG(DEBUG, \"counters are not supported\");\n \tconfig->ind_table_max_size =\n-\t\tsh->device_attr.max_rwq_indirection_table_size;\n+\t\tsh->dev_cap.max_rwq_indirection_table_size;\n \t/*\n \t * Remove this check once DPDK supports larger/variable\n \t * indirection tables.\n@@ -423,9 +410,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tDRV_LOG(DEBUG, \"Rx end alignment padding isn't supported\");\n \t\tconfig->hw_padding = 0;\n \t}\n-\tconfig->tso = (sh->device_attr.max_tso > 0);\n+\tconfig->tso = (sh->dev_cap.max_tso > 0);\n \tif (config->tso)\n-\t\tconfig->tso_max_payload_sz = sh->device_attr.max_tso;\n+\t\tconfig->tso_max_payload_sz = sh->dev_cap.max_tso;\n \tDRV_LOG(DEBUG, \"%sMPS is %s.\",\n \t\tconfig->mps == MLX5_MPW_ENHANCED ? \"enhanced \" :\n \t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n", "prefixes": [ "14/20" ] }