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GET /api/patches/106627/?format=api
{ "id": 106627, "url": "http://patches.dpdk.org/api/patches/106627/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220127153950.812953-8-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220127153950.812953-8-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220127153950.812953-8-michaelba@nvidia.com", "date": "2022-01-27T15:39:37", "name": "[07/20] net/mlx5: remove HCA attr structure duplication", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c11427fc63535f997b4c17789408a3541cd0ee04", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220127153950.812953-8-michaelba@nvidia.com/mbox/", "series": [ { "id": 21402, "url": "http://patches.dpdk.org/api/series/21402/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21402", "date": "2022-01-27T15:39:30", "name": "mlx5: refactor devargs management", "version": 1, "mbox": "http://patches.dpdk.org/series/21402/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/106627/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/106627/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CFF79A04A6;\n\tThu, 27 Jan 2022 16:41:10 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3BFBA42897;\n\tThu, 27 Jan 2022 16:40:18 +0100 (CET)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam08on2083.outbound.protection.outlook.com [40.107.100.83])\n by mails.dpdk.org (Postfix) with ESMTP id E67EB4067C\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH 07/20] net/mlx5: remove HCA attr structure duplication", "Date": "Thu, 27 Jan 2022 17:39:37 +0200", "Message-ID": "<20220127153950.812953-8-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220127153950.812953-1-michaelba@nvidia.com>", "References": "<20220127153950.812953-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "829a78e0-27b0-41f8-a195-08d9e1ab4e2e", "X-MS-TrafficTypeDiagnostic": "BY5PR12MB5000:EE_", "X-Microsoft-Antispam-PRVS": "\n <BY5PR12MB500070D6E7CCEE4FFB6B8205CC219@BY5PR12MB5000.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:9508;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n pggCLt5RuxVTK5FmutJbJKmdbbH1qk8/1/qeGFQp6fPNsDZ6w7ev3Hv3/k7HWzR1I2+NDZBZCDS6smXiLM6IUop1+EcRNQuSFku34uZgAZtYhEnndIrfQH+qFJHnLynp1ESyQBJzj9AMMdN/e9kk7z5Yw3Olyqxh6O5NfTBUiYrz+VJHfpKRhBwc6OptG6V6JD3tYPcyKn6j6Xz7LftBE8EWIa6gBZvWQPSGa4Ojql86QIZNWTUQ5KsVVcqOqVkt5913zcT21xO+w6lZvo7QjLDOxpXA34V+SENH/T5zX1VBUAl2Ms4ISo3V5JVJ10iFxMMx6rAeXDwjPtBOwyvmFeEtLiTmN7owoP2B2xm9D3LsTcvLr20ZIJIziI3NUhpsKCpXfP4Ko0vf+agKsnt7V6YORvbhwG3c/YQbEkg8ZIRYu4bbn462DjJlMoSAuWdbVuN83mlXgbk/QOLweccwO2bt8mMgVyBX/2rEgo/Lm3i8buD7OMj1EvCsczHOYQIQYaUtVTagP1XVAXtnRwj8/5XF6ipaqnn8VJFNoaTamSIidBLda0t0A1H3qsto7nDjt+Mn2bkVZN+8DKL63b2bENBzTiklFKnAhK8PY05du6RU7uA9uJpKYjrkv1PyG9FB5WsiwfEvHXRM9dtIBYTOC+QDMc3hwK4/aIcJJbs7daPx0aqlJqh4x9BphyUH0rg4fMCKygZRnUbDC/YsbBRTs3Y7HUhiakm+VTdWguForz9K/sxGf2cFk+XKD4fpPOjt", "X-Forefront-Antispam-Report": "CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(83380400001)(36860700001)(66574015)(47076005)(40460700003)(508600001)(316002)(1076003)(6286002)(26005)(2616005)(36756003)(54906003)(6916009)(336012)(186003)(426003)(5660300002)(70586007)(70206006)(4326008)(8676002)(30864003)(6666004)(81166007)(7696005)(8936002)(356005)(55016003)(107886003)(82310400004)(86362001)(2906002)(36900700001)(309714004)(20210929001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Jan 2022 15:40:11.4472 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 829a78e0-27b0-41f8-a195-08d9e1ab4e2e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT046.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB5000", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The HCA attribute structure is field of net configure structure.\nIt is also field of common configure structure.\n\nThere is no need for this duplication, because there is a reference to\nthe common structure from within the net structures.\n\nThis patch removes it from net configure structure and uses the common\nconfig structure instead.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 95 ++++++++++++++----------------\n drivers/net/mlx5/mlx5.c | 14 +++--\n drivers/net/mlx5/mlx5.h | 1 -\n drivers/net/mlx5/mlx5_devx.c | 8 ++-\n drivers/net/mlx5/mlx5_ethdev.c | 2 +-\n drivers/net/mlx5/mlx5_flow.c | 16 ++---\n drivers/net/mlx5/mlx5_flow_dv.c | 13 ++--\n drivers/net/mlx5/mlx5_flow_flex.c | 4 +-\n drivers/net/mlx5/mlx5_flow_meter.c | 4 +-\n drivers/net/mlx5/mlx5_rxq.c | 4 +-\n drivers/net/mlx5/mlx5_trigger.c | 12 ++--\n drivers/net/mlx5/mlx5_txpp.c | 2 +-\n drivers/net/mlx5/windows/mlx5_os.c | 25 ++++----\n 13 files changed, 100 insertions(+), 100 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 11d15d0aef..39ca145e4a 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -675,6 +675,7 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n \tbool fallback;\n \n #ifndef HAVE_IBV_DEVX_ASYNC\n@@ -682,16 +683,16 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n #else\n \tfallback = false;\n \tif (!sh->devx || !priv->config.dv_flow_en ||\n-\t !priv->config.hca_attr.flow_counters_dump ||\n-\t !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||\n+\t !hca_attr->flow_counters_dump ||\n+\t !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||\n \t (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))\n \t\tfallback = true;\n #endif\n \tif (fallback)\n \t\tDRV_LOG(INFO, \"Use fall-back DV counter management. Flow \"\n \t\t\t\"counter dump:%d, bulk_alloc_bitmap:0x%hhx.\",\n-\t\t\tpriv->config.hca_attr.flow_counters_dump,\n-\t\t\tpriv->config.hca_attr.flow_counter_bulk_alloc_bitmap);\n+\t\t\thca_attr->flow_counters_dump,\n+\t\t\thca_attr->flow_counter_bulk_alloc_bitmap);\n \t/* Initialize fallback mode only on the port initializes sh. */\n \tif (sh->refcnt == 1)\n \t\tsh->cmng.counter_fallback = fallback;\n@@ -875,6 +876,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n {\n \tconst struct mlx5_switch_info *switch_info = &spawn->info;\n \tstruct mlx5_dev_ctx_shared *sh = NULL;\n+\tstruct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr;\n \tstruct ibv_port_attr port_attr = { .state = IBV_PORT_NOP };\n \tstruct mlx5dv_context dv_attr = { .comp_mask = 0 };\n \tstruct rte_eth_dev *eth_dev = NULL;\n@@ -990,7 +992,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t}\n #endif\n #ifdef HAVE_MLX5DV_DR_ESWITCH\n-\tif (!(sh->cdev->config.hca_attr.eswitch_manager && config->dv_flow_en &&\n+\tif (!(hca_attr->eswitch_manager && config->dv_flow_en &&\n \t (switch_info->representor || switch_info->master)))\n \t\tconfig->dv_esw_en = 0;\n #else\n@@ -1315,14 +1317,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n \t\tconfig->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n \tif (sh->devx) {\n-\t\tconfig->hca_attr = sh->cdev->config.hca_attr;\n-\t\tsh->steering_format_version =\n-\t\t\tconfig->hca_attr.steering_format_version;\n+\t\tsh->steering_format_version = hca_attr->steering_format_version;\n \t\t/* Check for LRO support. */\n-\t\tif (config->dest_tir && config->hca_attr.lro_cap &&\n+\t\tif (config->dest_tir && hca_attr->lro_cap &&\n \t\t config->dv_flow_en) {\n \t\t\t/* TBD check tunnel lro caps. */\n-\t\t\tconfig->lro.supported = config->hca_attr.lro_cap;\n+\t\t\tconfig->lro.supported = hca_attr->lro_cap;\n \t\t\tDRV_LOG(DEBUG, \"Device supports LRO\");\n \t\t\t/*\n \t\t\t * If LRO timeout is not configured by application,\n@@ -1330,21 +1330,19 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t */\n \t\t\tif (!config->lro.timeout)\n \t\t\t\tconfig->lro.timeout =\n-\t\t\t\tconfig->hca_attr.lro_timer_supported_periods[0];\n+\t\t\t\t hca_attr->lro_timer_supported_periods[0];\n \t\t\tDRV_LOG(DEBUG, \"LRO session timeout set to %d usec\",\n \t\t\t\tconfig->lro.timeout);\n \t\t\tDRV_LOG(DEBUG, \"LRO minimal size of TCP segment \"\n \t\t\t\t\"required for coalescing is %d bytes\",\n-\t\t\t\tconfig->hca_attr.lro_min_mss_size);\n+\t\t\t\thca_attr->lro_min_mss_size);\n \t\t}\n #if defined(HAVE_MLX5DV_DR) && \\\n \t(defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \\\n \t defined(HAVE_MLX5_DR_CREATE_ACTION_ASO))\n-\t\tif (config->hca_attr.qos.sup &&\n-\t\t config->hca_attr.qos.flow_meter_old &&\n+\t\tif (hca_attr->qos.sup && hca_attr->qos.flow_meter_old &&\n \t\t config->dv_flow_en) {\n-\t\t\tuint8_t reg_c_mask =\n-\t\t\t\tconfig->hca_attr.qos.flow_meter_reg_c_ids;\n+\t\t\tuint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids;\n \t\t\t/*\n \t\t\t * Meter needs two REG_C's for color match and pre-sfx\n \t\t\t * flow match. Here get the REG_C for color match.\n@@ -1368,20 +1366,18 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\t\tpriv->mtr_color_reg = ffs(reg_c_mask)\n \t\t\t\t\t\t\t - 1 + REG_C_0;\n \t\t\t\tpriv->mtr_en = 1;\n-\t\t\t\tpriv->mtr_reg_share =\n-\t\t\t\t config->hca_attr.qos.flow_meter;\n+\t\t\t\tpriv->mtr_reg_share = hca_attr->qos.flow_meter;\n \t\t\t\tDRV_LOG(DEBUG, \"The REG_C meter uses is %d\",\n \t\t\t\t\tpriv->mtr_color_reg);\n \t\t\t}\n \t\t}\n-\t\tif (config->hca_attr.qos.sup &&\n-\t\t\tconfig->hca_attr.qos.flow_meter_aso_sup) {\n+\t\tif (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) {\n \t\t\tuint32_t log_obj_size =\n \t\t\t\trte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);\n \t\t\tif (log_obj_size >=\n-\t\t\tconfig->hca_attr.qos.log_meter_aso_granularity &&\n-\t\t\tlog_obj_size <=\n-\t\t\tconfig->hca_attr.qos.log_meter_aso_max_alloc)\n+\t\t\t hca_attr->qos.log_meter_aso_granularity &&\n+\t\t\t log_obj_size <=\n+\t\t\t hca_attr->qos.log_meter_aso_max_alloc)\n \t\t\t\tsh->meter_aso_en = 1;\n \t\t}\n \t\tif (priv->mtr_en) {\n@@ -1391,12 +1387,11 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\tgoto error;\n \t\t\t}\n \t\t}\n-\t\tif (config->hca_attr.flow.tunnel_header_0_1)\n+\t\tif (hca_attr->flow.tunnel_header_0_1)\n \t\t\tsh->tunnel_header_0_1 = 1;\n #endif\n #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO\n-\t\tif (config->hca_attr.flow_hit_aso &&\n-\t\t priv->mtr_color_reg == REG_C_3) {\n+\t\tif (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) {\n \t\t\tsh->flow_hit_aso_en = 1;\n \t\t\terr = mlx5_flow_aso_age_mng_init(sh);\n \t\t\tif (err) {\n@@ -1408,8 +1403,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */\n #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \\\n \tdefined(HAVE_MLX5_DR_ACTION_ASO_CT)\n-\t\tif (config->hca_attr.ct_offload &&\n-\t\t priv->mtr_color_reg == REG_C_3) {\n+\t\tif (hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) {\n \t\t\terr = mlx5_flow_aso_ct_mng_init(sh);\n \t\t\tif (err) {\n \t\t\t\terr = -err;\n@@ -1420,13 +1414,13 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t}\n #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */\n #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE)\n-\t\tif (config->hca_attr.log_max_ft_sampler_num > 0 &&\n+\t\tif (hca_attr->log_max_ft_sampler_num > 0 &&\n \t\t config->dv_flow_en) {\n \t\t\tpriv->sampler_en = 1;\n \t\t\tDRV_LOG(DEBUG, \"Sampler enabled!\");\n \t\t} else {\n \t\t\tpriv->sampler_en = 0;\n-\t\t\tif (!config->hca_attr.log_max_ft_sampler_num)\n+\t\t\tif (!hca_attr->log_max_ft_sampler_num)\n \t\t\t\tDRV_LOG(WARNING,\n \t\t\t\t\t\"No available register for sampler.\");\n \t\t\telse\n@@ -1440,13 +1434,13 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->cqe_comp = 0;\n \t}\n \tif (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&\n-\t (!sh->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) {\n+\t (!sh->devx || !hca_attr->mini_cqe_resp_flow_tag)) {\n \t\tDRV_LOG(WARNING, \"Flow Tag CQE compression\"\n \t\t\t\t \" format isn't supported.\");\n \t\tconfig->cqe_comp = 0;\n \t}\n \tif (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&\n-\t (!sh->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) {\n+\t (!sh->devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) {\n \t\tDRV_LOG(WARNING, \"L3/L4 Header CQE compression\"\n \t\t\t\t \" format isn't supported.\");\n \t\tconfig->cqe_comp = 0;\n@@ -1455,55 +1449,55 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tconfig->cqe_comp ? \"\" : \"not \");\n \tif (config->tx_pp) {\n \t\tDRV_LOG(DEBUG, \"Timestamp counter frequency %u kHz\",\n-\t\t\tconfig->hca_attr.dev_freq_khz);\n+\t\t\thca_attr->dev_freq_khz);\n \t\tDRV_LOG(DEBUG, \"Packet pacing is %ssupported\",\n-\t\t\tconfig->hca_attr.qos.packet_pacing ? \"\" : \"not \");\n+\t\t\thca_attr->qos.packet_pacing ? \"\" : \"not \");\n \t\tDRV_LOG(DEBUG, \"Cross channel ops are %ssupported\",\n-\t\t\tconfig->hca_attr.cross_channel ? \"\" : \"not \");\n+\t\t\thca_attr->cross_channel ? \"\" : \"not \");\n \t\tDRV_LOG(DEBUG, \"WQE index ignore is %ssupported\",\n-\t\t\tconfig->hca_attr.wqe_index_ignore ? \"\" : \"not \");\n+\t\t\thca_attr->wqe_index_ignore ? \"\" : \"not \");\n \t\tDRV_LOG(DEBUG, \"Non-wire SQ feature is %ssupported\",\n-\t\t\tconfig->hca_attr.non_wire_sq ? \"\" : \"not \");\n+\t\t\thca_attr->non_wire_sq ? \"\" : \"not \");\n \t\tDRV_LOG(DEBUG, \"Static WQE SQ feature is %ssupported (%d)\",\n-\t\t\tconfig->hca_attr.log_max_static_sq_wq ? \"\" : \"not \",\n-\t\t\tconfig->hca_attr.log_max_static_sq_wq);\n+\t\t\thca_attr->log_max_static_sq_wq ? \"\" : \"not \",\n+\t\t\thca_attr->log_max_static_sq_wq);\n \t\tDRV_LOG(DEBUG, \"WQE rate PP mode is %ssupported\",\n-\t\t\tconfig->hca_attr.qos.wqe_rate_pp ? \"\" : \"not \");\n+\t\t\thca_attr->qos.wqe_rate_pp ? \"\" : \"not \");\n \t\tif (!sh->devx) {\n \t\t\tDRV_LOG(ERR, \"DevX is required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config->hca_attr.qos.packet_pacing) {\n+\t\tif (!hca_attr->qos.packet_pacing) {\n \t\t\tDRV_LOG(ERR, \"Packet pacing is not supported\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config->hca_attr.cross_channel) {\n+\t\tif (!hca_attr->cross_channel) {\n \t\t\tDRV_LOG(ERR, \"Cross channel operations are\"\n \t\t\t\t \" required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config->hca_attr.wqe_index_ignore) {\n+\t\tif (!hca_attr->wqe_index_ignore) {\n \t\t\tDRV_LOG(ERR, \"WQE index ignore feature is\"\n \t\t\t\t \" required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config->hca_attr.non_wire_sq) {\n+\t\tif (!hca_attr->non_wire_sq) {\n \t\t\tDRV_LOG(ERR, \"Non-wire SQ feature is\"\n \t\t\t\t \" required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config->hca_attr.log_max_static_sq_wq) {\n+\t\tif (!hca_attr->log_max_static_sq_wq) {\n \t\t\tDRV_LOG(ERR, \"Static WQE SQ feature is\"\n \t\t\t\t \" required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config->hca_attr.qos.wqe_rate_pp) {\n+\t\tif (!hca_attr->qos.wqe_rate_pp) {\n \t\t\tDRV_LOG(ERR, \"WQE rate mode is required\"\n \t\t\t\t \" for packet pacing\");\n \t\t\terr = ENODEV;\n@@ -1517,7 +1511,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n #endif\n \t}\n \tif (config->std_delay_drop || config->hp_delay_drop) {\n-\t\tif (!config->hca_attr.rq_delay_drop) {\n+\t\tif (!hca_attr->rq_delay_drop) {\n \t\t\tconfig->std_delay_drop = 0;\n \t\t\tconfig->hp_delay_drop = 0;\n \t\t\tDRV_LOG(WARNING,\n@@ -1528,7 +1522,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tif (sh->devx) {\n \t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n \n-\t\terr = config->hca_attr.access_register_user ?\n+\t\terr = hca_attr->access_register_user ?\n \t\t\tmlx5_devx_cmd_register_read\n \t\t\t\t(sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n \t\t\t\treg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;\n@@ -1542,8 +1536,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\tconfig->rt_timestamp = 1;\n \t\t} else {\n \t\t\t/* Kernel does not support register reading. */\n-\t\t\tif (config->hca_attr.dev_freq_khz ==\n-\t\t\t\t\t\t (NS_PER_S / MS_PER_S))\n+\t\t\tif (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))\n \t\t\t\tconfig->rt_timestamp = 1;\n \t\t}\n \t}\n@@ -1552,7 +1545,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip\n \t * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore.\n \t */\n-\tif (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en)\n+\tif (hca_attr->scatter_fcs_w_decap_disable && config->decap_en)\n \t\tconfig->hw_fcs_strip = 0;\n \tDRV_LOG(DEBUG, \"FCS stripping configuration is %ssupported\",\n \t\t(config->hw_fcs_strip ? \"\" : \"not \"));\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 60167450e4..920b174b96 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -889,7 +889,7 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)\n \tuint32_t ids[8];\n \tint ret;\n \n-\tif (!priv->config.hca_attr.parse_graph_flex_node) {\n+\tif (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) {\n \t\tDRV_LOG(ERR, \"Dynamic flex parser is not supported \"\n \t\t\t\"for device %s.\", priv->dev_data->name);\n \t\treturn -ENOTSUP;\n@@ -2035,6 +2035,8 @@ void\n mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,\n \t\t struct mlx5_dev_config *config)\n {\n+\tstruct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr;\n+\n \tif (config->txq_inline_min != MLX5_ARG_UNSET) {\n \t\t/* Application defines size of inlined data explicitly. */\n \t\tif (spawn->pci_dev != NULL) {\n@@ -2054,9 +2056,9 @@ mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,\n \t\t}\n \t\tgoto exit;\n \t}\n-\tif (config->hca_attr.eth_net_offloads) {\n+\tif (hca_attr->eth_net_offloads) {\n \t\t/* We have DevX enabled, inline mode queried successfully. */\n-\t\tswitch (config->hca_attr.wqe_inline_mode) {\n+\t\tswitch (hca_attr->wqe_inline_mode) {\n \t\tcase MLX5_CAP_INLINE_MODE_L2:\n \t\t\t/* outer L2 header must be inlined. */\n \t\t\tconfig->txq_inline_min = MLX5_INLINE_HSIZE_L2;\n@@ -2065,14 +2067,14 @@ mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,\n \t\t\t/* No inline data are required by NIC. */\n \t\t\tconfig->txq_inline_min = MLX5_INLINE_HSIZE_NONE;\n \t\t\tconfig->hw_vlan_insert =\n-\t\t\t\tconfig->hca_attr.wqe_vlan_insert;\n+\t\t\t\thca_attr->wqe_vlan_insert;\n \t\t\tDRV_LOG(DEBUG, \"Tx VLAN insertion is supported\");\n \t\t\tgoto exit;\n \t\tcase MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:\n \t\t\t/* inline mode is defined by NIC vport context. */\n-\t\t\tif (!config->hca_attr.eth_virt)\n+\t\t\tif (!hca_attr->eth_virt)\n \t\t\t\tbreak;\n-\t\t\tswitch (config->hca_attr.vport_inline_mode) {\n+\t\t\tswitch (hca_attr->vport_inline_mode) {\n \t\t\tcase MLX5_INLINE_MODE_NONE:\n \t\t\t\tconfig->txq_inline_min =\n \t\t\t\t\tMLX5_INLINE_HSIZE_NONE;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex e4b2523eb0..ee485343ff 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -299,7 +299,6 @@ struct mlx5_dev_config {\n \tint txq_inline_mpw; /* Max packet size for inlining with eMPW. */\n \tint tx_pp; /* Timestamp scheduling granularity in nanoseconds. */\n \tint tx_skew; /* Tx scheduling skew between WQE and data on wire. */\n-\tstruct mlx5_hca_attr hca_attr; /* HCA attributes. */\n \tstruct mlx5_lro_config lro; /* LRO configuration. */\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 91243f684f..97c8925044 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -419,7 +419,8 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq)\n \tMLX5_ASSERT(rxq != NULL && rxq->ctrl != NULL && tmpl != NULL);\n \ttmpl->rxq_ctrl = rxq_ctrl;\n \tattr.hairpin = 1;\n-\tmax_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;\n+\tmax_wq_data =\n+\t\tpriv->sh->cdev->config.hca_attr.log_max_hairpin_wq_data_sz;\n \t/* Jumbo frames > 9KB should be supported, and more packets. */\n \tif (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {\n \t\tif (priv->config.log_hp_size > max_wq_data) {\n@@ -1117,7 +1118,8 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n \ttmpl->txq_ctrl = txq_ctrl;\n \tattr.hairpin = 1;\n \tattr.tis_lst_sz = 1;\n-\tmax_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;\n+\tmax_wq_data =\n+\t\tpriv->sh->cdev->config.hca_attr.log_max_hairpin_wq_data_sz;\n \t/* Jumbo frames > 9KB should be supported, and more packets. */\n \tif (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {\n \t\tif (priv->config.log_hp_size > max_wq_data) {\n@@ -1193,7 +1195,7 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,\n \tstruct mlx5_devx_create_sq_attr sq_attr = {\n \t\t.flush_in_error_en = 1,\n \t\t.allow_multi_pkt_send_wqe = !!priv->config.mps,\n-\t\t.min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode,\n+\t\t.min_wqe_inline_mode = cdev->config.hca_attr.vport_inline_mode,\n \t\t.allow_swp = !!priv->config.swp,\n \t\t.cqn = txq_obj->cq_obj.cq->id,\n \t\t.tis_lst_sz = 1,\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex dc647d5580..5b0eee3321 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -337,7 +337,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n \tinfo->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;\n \tmlx5_set_default_params(dev, info);\n \tmlx5_set_txlimit_params(dev, info);\n-\tif (priv->config.hca_attr.mem_rq_rmp &&\n+\tif (priv->sh->cdev->config.hca_attr.mem_rq_rmp &&\n \t priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new)\n \t\tinfo->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE;\n \tinfo->switch_info.name = dev->data->name;\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex d7cb1eb89b..5a21803e18 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -2906,7 +2906,7 @@ mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,\n \tconst struct rte_flow_item_geneve *mask = item->mask;\n \tint ret;\n \tuint16_t gbhdr;\n-\tuint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ?\n+\tuint8_t opt_len = priv->sh->cdev->config.hca_attr.geneve_max_opt_len ?\n \t\t\t MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0;\n \tconst struct rte_flow_item_geneve nic_mask = {\n \t\t.ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80),\n@@ -2914,7 +2914,7 @@ mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,\n \t\t.protocol = RTE_BE16(UINT16_MAX),\n \t};\n \n-\tif (!priv->config.hca_attr.tunnel_stateless_geneve_rx)\n+\tif (!priv->sh->cdev->config.hca_attr.tunnel_stateless_geneve_rx)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n \t\t\t\t\t \"L3 Geneve is not enabled by device\"\n@@ -2994,10 +2994,9 @@ mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n \tstruct mlx5_geneve_tlv_option_resource *geneve_opt_resource;\n-\tstruct mlx5_hca_attr *hca_attr = &priv->config.hca_attr;\n+\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n \tuint8_t data_max_supported =\n \t\t\thca_attr->max_geneve_tlv_option_data_len * 4;\n-\tstruct mlx5_dev_config *config = &priv->config;\n \tconst struct rte_flow_item_geneve *geneve_spec;\n \tconst struct rte_flow_item_geneve *geneve_mask;\n \tconst struct rte_flow_item_geneve_opt *spec = item->spec;\n@@ -3031,11 +3030,11 @@ mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,\n \t\t\t\"Geneve TLV opt class/type/length masks must be full\");\n \t/* Check if length is supported */\n \tif ((uint32_t)spec->option_len >\n-\t\t\tconfig->hca_attr.max_geneve_tlv_option_data_len)\n+\t\t\thca_attr->max_geneve_tlv_option_data_len)\n \t\treturn rte_flow_error_set\n \t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n \t\t\t\"Geneve TLV opt length not supported\");\n-\tif (config->hca_attr.max_geneve_tlv_options > 1)\n+\tif (hca_attr->max_geneve_tlv_options > 1)\n \t\tDRV_LOG(DEBUG,\n \t\t\t\"max_geneve_tlv_options supports more than 1 option\");\n \t/* Check GENEVE item preceding. */\n@@ -3090,7 +3089,7 @@ mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,\n \t\t\t\t\t\"Data mask is of unsupported size\");\n \t}\n \t/* Check GENEVE option is supported in NIC. */\n-\tif (!config->hca_attr.geneve_tlv_opt)\n+\tif (!hca_attr->geneve_tlv_opt)\n \t\treturn rte_flow_error_set\n \t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n \t\t\t\"Geneve TLV opt not supported\");\n@@ -6249,7 +6248,8 @@ flow_create_split_sample(struct rte_eth_dev *dev,\n \t\t * When reg_c_preserve is set, metadata registers Cx preserve\n \t\t * their value even through packet duplication.\n \t\t */\n-\t\tadd_tag = (!fdb_tx || priv->config.hca_attr.reg_c_preserve);\n+\t\tadd_tag = (!fdb_tx ||\n+\t\t\t priv->sh->cdev->config.hca_attr.reg_c_preserve);\n \t\tif (add_tag)\n \t\t\tsfx_items = (struct rte_flow_item *)((char *)sfx_actions\n \t\t\t\t\t+ act_size);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex ef9c66eddf..b0ed9f93a0 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -2317,7 +2317,7 @@ flow_dv_validate_item_gtp(struct rte_eth_dev *dev,\n \t\t.teid = RTE_BE32(0xffffffff),\n \t};\n \n-\tif (!priv->config.hca_attr.tunnel_stateless_gtp)\n+\tif (!priv->sh->cdev->config.hca_attr.tunnel_stateless_gtp)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n \t\t\t\t\t \"GTP support is not enabled\");\n@@ -2426,6 +2426,7 @@ flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,\n {\n \tint ret;\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;\n \tconst struct rte_flow_item_ipv4 *spec = item->spec;\n \tconst struct rte_flow_item_ipv4 *last = item->last;\n \tconst struct rte_flow_item_ipv4 *mask = item->mask;\n@@ -2444,8 +2445,8 @@ flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,\n \n \tif (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {\n \t\tint tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);\n-\t\tbool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :\n-\t\t\t priv->config.hca_attr.inner_ipv4_ihl;\n+\t\tbool ihl_cap = !tunnel ?\n+\t\t\t attr->outer_ipv4_ihl : attr->inner_ipv4_ihl;\n \t\tif (!ihl_cap)\n \t\t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n@@ -3384,7 +3385,7 @@ flow_dv_validate_action_decap(struct rte_eth_dev *dev,\n {\n \tconst struct mlx5_priv *priv = dev->data->dev_private;\n \n-\tif (priv->config.hca_attr.scatter_fcs_w_decap_disable &&\n+\tif (priv->sh->cdev->config.hca_attr.scatter_fcs_w_decap_disable &&\n \t !priv->config.decap_en)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n@@ -5753,7 +5754,7 @@ flow_dv_validate_action_sample(uint64_t *action_flags,\n \t\t\t\t\t\t NULL,\n \t\t\t\t\t\t \"E-Switch must has a dest \"\n \t\t\t\t\t\t \"port for mirroring\");\n-\t\tif (!priv->config.hca_attr.reg_c_preserve &&\n+\t\tif (!priv->sh->cdev->config.hca_attr.reg_c_preserve &&\n \t\t priv->representor_id != UINT16_MAX)\n \t\t\t*fdb_mirror_limit = 1;\n \t}\n@@ -6686,7 +6687,7 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev,\n \tconst struct rte_flow_item_integrity *spec = (typeof(spec))\n \t\t\t\t\t\t integrity_item->spec;\n \n-\tif (!priv->config.hca_attr.pkt_integrity_match)\n+\tif (!priv->sh->cdev->config.hca_attr.pkt_integrity_match)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t integrity_item,\ndiff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c\nindex 9413d4d817..26f0dfa36f 100644\n--- a/drivers/net/mlx5/mlx5_flow_flex.c\n+++ b/drivers/net/mlx5/mlx5_flow_flex.c\n@@ -910,7 +910,7 @@ mlx5_flex_translate_sample(struct mlx5_hca_flex_attr *attr,\n \t * offsets in any order.\n \t *\n \t * Gather all similar fields together, build array of bit intervals\n-\t * in asсending order and try to cover with the smallest set of sample\n+\t * in ascending order and try to cover with the smallest set of sample\n \t * registers.\n \t */\n \tmemset(&cover, 0, sizeof(cover));\n@@ -1153,7 +1153,7 @@ mlx5_flex_translate_conf(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_hca_flex_attr *attr = &priv->config.hca_attr.flex;\n+\tstruct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex;\n \tint ret;\n \n \tret = mlx5_flex_translate_length(attr, conf, devx, error);\ndiff --git a/drivers/net/mlx5/mlx5_flow_meter.c b/drivers/net/mlx5/mlx5_flow_meter.c\nindex 0dc7fbfb32..77ae326bb7 100644\n--- a/drivers/net/mlx5/mlx5_flow_meter.c\n+++ b/drivers/net/mlx5/mlx5_flow_meter.c\n@@ -155,7 +155,7 @@ mlx5_flow_meter_profile_validate(struct rte_eth_dev *dev,\n \t\t\t\t\t \"Meter profile already exists.\");\n \tif (!priv->sh->meter_aso_en) {\n \t\t/* Old version is even not supported. */\n-\t\tif (!priv->config.hca_attr.qos.flow_meter_old)\n+\t\tif (!priv->sh->cdev->config.hca_attr.qos.flow_meter_old)\n \t\t\treturn -rte_mtr_error_set(error, ENOTSUP,\n \t\t\t\tRTE_MTR_ERROR_TYPE_METER_PROFILE,\n \t\t\t\tNULL, \"Metering is not supported.\");\n@@ -426,7 +426,7 @@ mlx5_flow_mtr_cap_get(struct rte_eth_dev *dev,\n \t\t struct rte_mtr_error *error __rte_unused)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_hca_qos_attr *qattr = &priv->config.hca_attr.qos;\n+\tstruct mlx5_hca_qos_attr *qattr = &priv->sh->cdev->config.hca_attr.qos;\n \n \tif (!priv->mtr_en)\n \t\treturn -rte_mtr_error_set(error, ENOTSUP,\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 580d7ae868..0ede46aa43 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -863,7 +863,7 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\tMLX5_ASSERT(n_seg < MLX5_MAX_RXQ_NSEG);\n \t}\n \tif (conf->share_group > 0) {\n-\t\tif (!priv->config.hca_attr.mem_rq_rmp) {\n+\t\tif (!priv->sh->cdev->config.hca_attr.mem_rq_rmp) {\n \t\t\tDRV_LOG(ERR, \"port %u queue index %u shared Rx queue not supported by fw\",\n \t\t\t\t dev->data->port_id, idx);\n \t\t\trte_errno = EINVAL;\n@@ -1517,7 +1517,7 @@ mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \n-\tif (priv->config.hca_attr.lro_max_msg_sz_mode ==\n+\tif (priv->sh->cdev->config.hca_attr.lro_max_msg_sz_mode ==\n \t MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >\n \t MLX5_MAX_TCP_HDR_OFFSET)\n \t\tmax_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 74c9c0a4ff..4bb0331464 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -341,14 +341,16 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)\n \t\tsq_attr.state = MLX5_SQC_STATE_RDY;\n \t\tsq_attr.sq_state = MLX5_SQC_STATE_RST;\n \t\tsq_attr.hairpin_peer_rq = rq->id;\n-\t\tsq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id;\n+\t\tsq_attr.hairpin_peer_vhca =\n+\t\t\t\tpriv->sh->cdev->config.hca_attr.vhca_id;\n \t\tret = mlx5_devx_cmd_modify_sq(sq, &sq_attr);\n \t\tif (ret)\n \t\t\tgoto error;\n \t\trq_attr.state = MLX5_SQC_STATE_RDY;\n \t\trq_attr.rq_state = MLX5_SQC_STATE_RST;\n \t\trq_attr.hairpin_peer_sq = sq->id;\n-\t\trq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id;\n+\t\trq_attr.hairpin_peer_vhca =\n+\t\t\t\tpriv->sh->cdev->config.hca_attr.vhca_id;\n \t\tret = mlx5_devx_cmd_modify_rq(rq, &rq_attr);\n \t\tif (ret)\n \t\t\tgoto error;\n@@ -425,7 +427,7 @@ mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tpeer_info->qp_id = txq_ctrl->obj->sq->id;\n-\t\tpeer_info->vhca_id = priv->config.hca_attr.vhca_id;\n+\t\tpeer_info->vhca_id = priv->sh->cdev->config.hca_attr.vhca_id;\n \t\t/* 1-to-1 mapping, only the first one is used. */\n \t\tpeer_info->peer_q = txq_ctrl->hairpin_conf.peers[0].queue;\n \t\tpeer_info->tx_explicit = txq_ctrl->hairpin_conf.tx_explicit;\n@@ -455,7 +457,7 @@ mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tpeer_info->qp_id = rxq_ctrl->obj->rq->id;\n-\t\tpeer_info->vhca_id = priv->config.hca_attr.vhca_id;\n+\t\tpeer_info->vhca_id = priv->sh->cdev->config.hca_attr.vhca_id;\n \t\tpeer_info->peer_q = rxq->hairpin_conf.peers[0].queue;\n \t\tpeer_info->tx_explicit = rxq->hairpin_conf.tx_explicit;\n \t\tpeer_info->manual_bind = rxq->hairpin_conf.manual_bind;\n@@ -817,7 +819,7 @@ mlx5_hairpin_bind_single_port(struct rte_eth_dev *dev, uint16_t rx_port)\n \t\t/* Pass TxQ's information to peer RxQ and try binding. */\n \t\tcur.peer_q = rx_queue;\n \t\tcur.qp_id = txq_ctrl->obj->sq->id;\n-\t\tcur.vhca_id = priv->config.hca_attr.vhca_id;\n+\t\tcur.vhca_id = priv->sh->cdev->config.hca_attr.vhca_id;\n \t\tcur.tx_explicit = txq_ctrl->hairpin_conf.tx_explicit;\n \t\tcur.manual_bind = txq_ctrl->hairpin_conf.manual_bind;\n \t\t/*\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex af77e91e4c..1d16ebcb41 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -825,7 +825,7 @@ mlx5_txpp_create(struct mlx5_dev_ctx_shared *sh, struct mlx5_priv *priv)\n \tsh->txpp.tick = tx_pp >= 0 ? tx_pp : -tx_pp;\n \tsh->txpp.test = !!(tx_pp < 0);\n \tsh->txpp.skew = priv->config.tx_skew;\n-\tsh->txpp.freq = priv->config.hca_attr.dev_freq_khz;\n+\tsh->txpp.freq = sh->cdev->config.hca_attr.dev_freq_khz;\n \tret = mlx5_txpp_create_event_channel(sh);\n \tif (ret)\n \t\tgoto exit;\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex c1f8bc9ee3..3d8bd2e100 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -268,6 +268,7 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n \tbool fallback;\n \n #ifndef HAVE_IBV_DEVX_ASYNC\n@@ -275,16 +276,16 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n #else\n \tfallback = false;\n \tif (!sh->devx || !priv->config.dv_flow_en ||\n-\t !priv->config.hca_attr.flow_counters_dump ||\n-\t !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||\n+\t !hca_attr->flow_counters_dump ||\n+\t !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||\n \t (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))\n \t\tfallback = true;\n #endif\n \tif (fallback)\n \t\tDRV_LOG(INFO, \"Use fall-back DV counter management. Flow \"\n \t\t\t\"counter dump:%d, bulk_alloc_bitmap:0x%hhx.\",\n-\t\t\tpriv->config.hca_attr.flow_counters_dump,\n-\t\t\tpriv->config.hca_attr.flow_counter_bulk_alloc_bitmap);\n+\t\t\thca_attr->flow_counters_dump,\n+\t\t\thca_attr->flow_counter_bulk_alloc_bitmap);\n \t/* Initialize fallback mode only on the port initializes sh. */\n \tif (sh->refcnt == 1)\n \t\tsh->cmng.counter_fallback = fallback;\n@@ -318,6 +319,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tconst struct mlx5_switch_info *switch_info = &spawn->info;\n \tstruct mlx5_dev_ctx_shared *sh = NULL;\n \tstruct mlx5_dev_attr device_attr;\n+\tstruct mlx5_hca_attr *hca_attr;\n \tstruct rte_eth_dev *eth_dev = NULL;\n \tstruct mlx5_priv *priv = NULL;\n \tint err = 0;\n@@ -475,19 +477,19 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->cqe_comp = 0;\n \t}\n \tif (sh->devx) {\n-\t\tconfig->hca_attr = sh->cdev->config.hca_attr;\n-\t\tconfig->hw_csum = config->hca_attr.csum_cap;\n+\t\thca_attr = &sh->cdev->config.hca_attr;\n+\t\tconfig->hw_csum = hca_attr->csum_cap;\n \t\tDRV_LOG(DEBUG, \"checksum offloading is %ssupported\",\n-\t\t (config->hw_csum ? \"\" : \"not \"));\n-\t\tconfig->hw_vlan_strip = config->hca_attr.vlan_cap;\n+\t\t\t(config->hw_csum ? \"\" : \"not \"));\n+\t\tconfig->hw_vlan_strip = hca_attr->vlan_cap;\n \t\tDRV_LOG(DEBUG, \"VLAN stripping is %ssupported\",\n \t\t\t(config->hw_vlan_strip ? \"\" : \"not \"));\n-\t\tconfig->hw_fcs_strip = config->hca_attr.scatter_fcs;\n+\t\tconfig->hw_fcs_strip = hca_attr->scatter_fcs;\n \t}\n \tif (sh->devx) {\n \t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n \n-\t\terr = config->hca_attr.access_register_user ?\n+\t\terr = hca_attr->access_register_user ?\n \t\t\tmlx5_devx_cmd_register_read\n \t\t\t\t(sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n \t\t\t\treg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;\n@@ -501,8 +503,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\tconfig->rt_timestamp = 1;\n \t\t} else {\n \t\t\t/* Kernel does not support register reading. */\n-\t\t\tif (config->hca_attr.dev_freq_khz ==\n-\t\t\t\t\t\t (NS_PER_S / MS_PER_S))\n+\t\t\tif (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))\n \t\t\t\tconfig->rt_timestamp = 1;\n \t\t}\n \t}\n", "prefixes": [ "07/20" ] }