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GET /api/patches/106626/?format=api
{ "id": 106626, "url": "http://patches.dpdk.org/api/patches/106626/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220127153950.812953-9-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220127153950.812953-9-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220127153950.812953-9-michaelba@nvidia.com", "date": "2022-01-27T15:39:38", "name": "[08/20] net/mlx5: remove DevX flag duplication", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6fcc882082ab2b74cd9c196f9f0a35e83ae74fb6", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220127153950.812953-9-michaelba@nvidia.com/mbox/", "series": [ { "id": 21402, "url": "http://patches.dpdk.org/api/series/21402/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21402", "date": "2022-01-27T15:39:30", "name": "mlx5: refactor devargs management", "version": 1, "mbox": "http://patches.dpdk.org/series/21402/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/106626/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/106626/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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duplication", "Date": "Thu, 27 Jan 2022 17:39:38 +0200", "Message-ID": "<20220127153950.812953-9-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220127153950.812953-1-michaelba@nvidia.com>", "References": "<20220127153950.812953-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "c019f24c-e138-4997-34f2-08d9e1ab4ec3", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1567:EE_", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB1567FFF2D6258C7F148D06A6CC219@MWHPR12MB1567.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7691;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ZC66k4NmuxJrk5BWzOPL0JbxjUgDHBKDxSMqPbC6CK/N+9n62skXkC8fv2J/Z+s6a8wTOSqelQIPCFf6rJK/X9Qd9KQINbvhv5b1rccQ/bLe94iDtBQNpuN0PoV9Fr+l1lGIbviYvH/2yni8uVdrfs3J7k5pkmRnbahxlBf/glBZY24XWKZkdk15I/FUouZS0BYDltedTxSM5OfqcJ9VdvXPBltxGRYC1s/SmbrqEei/o14YfKGoftyW+a1cAuXdxRJIbpz6/Fwscx0LIqDTPuYeVwrl4tJa44Z5fWFHuTADYS0sCaJNgmSmQZv4k/aA9nWmo39MFmuupxOeVnceDEuKt8vBJ76EFg/e6mQtSayAr2Y1auWuLoemg23Yey5Wu8bJtNWMAqhZfOM1c1UepryGDb6UDaKi78XaW6amVU8XRkHrWLEk1qYXu8PLCoUaPK6cpcYMr+ZJCb/wm2IWsUsIYJf/k8qeHQIgzAv0gpvvX6o33Pdy30ixQzM1yfn22crfGxqC4Uq7ksguGN1Ide+Ga61yHzCLdW/qo85QI1v1T1RKNjjlJSj49gyzM1BGFdUdgdxNnp1YQbDqhDManeW4o2FmdQmIzdE+XATFfQ9UAa3XTMLIaoK5OpTuyvXWvbZhEc/rZhRQj6kGsQDJbIukrGK4hQhLSeh96LzSPE+TCtbnBFTycVCSfJJXczqyx5lrR/z/ROm+pK0jmjLJyw==", "X-Forefront-Antispam-Report": "CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(86362001)(2906002)(83380400001)(336012)(55016003)(54906003)(6666004)(40460700003)(6916009)(426003)(7696005)(47076005)(5660300002)(36756003)(4326008)(70586007)(2616005)(6286002)(508600001)(8936002)(36860700001)(8676002)(186003)(356005)(70206006)(81166007)(82310400004)(30864003)(26005)(107886003)(316002)(1076003)(36900700001)(20210929001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Jan 2022 15:40:12.4209 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c019f24c-e138-4997-34f2-08d9e1ab4ec3", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT059.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1567", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The sharing device context structure has a field named \"devx\" which\nindicates if DevX is supported.\nThe common configure stracture has also field named \"devx\" with the same\nmeaning.\n\nThere is no need for this duplication, because there is a reference to\nthe common structure from within the sharing device context structure.\n\nThis patch removes it from sharing device context structure and uses the\ncommon config structure instead.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 16 ++++++++--------\n drivers/net/mlx5/linux/mlx5_verbs.c | 4 ++--\n drivers/net/mlx5/mlx5.c | 3 +--\n drivers/net/mlx5/mlx5.h | 1 -\n drivers/net/mlx5/mlx5_ethdev.c | 3 ++-\n drivers/net/mlx5/mlx5_flow.c | 2 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 23 ++++++++++++-----------\n drivers/net/mlx5/mlx5_trigger.c | 2 +-\n drivers/net/mlx5/windows/mlx5_os.c | 6 +++---\n 9 files changed, 30 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 39ca145e4a..b579be25cb 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -682,7 +682,7 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n \tfallback = true;\n #else\n \tfallback = false;\n-\tif (!sh->devx || !priv->config.dv_flow_en ||\n+\tif (!sh->cdev->config.devx || !priv->config.dv_flow_en ||\n \t !hca_attr->flow_counters_dump ||\n \t !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||\n \t (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))\n@@ -1316,7 +1316,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->mps == MLX5_MPW_ENHANCED ? \"enhanced \" :\n \t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n \t\tconfig->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n-\tif (sh->devx) {\n+\tif (sh->cdev->config.devx) {\n \t\tsh->steering_format_version = hca_attr->steering_format_version;\n \t\t/* Check for LRO support. */\n \t\tif (config->dest_tir && hca_attr->lro_cap &&\n@@ -1434,13 +1434,13 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->cqe_comp = 0;\n \t}\n \tif (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&\n-\t (!sh->devx || !hca_attr->mini_cqe_resp_flow_tag)) {\n+\t (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_flow_tag)) {\n \t\tDRV_LOG(WARNING, \"Flow Tag CQE compression\"\n \t\t\t\t \" format isn't supported.\");\n \t\tconfig->cqe_comp = 0;\n \t}\n \tif (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&\n-\t (!sh->devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) {\n+\t (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) {\n \t\tDRV_LOG(WARNING, \"L3/L4 Header CQE compression\"\n \t\t\t\t \" format isn't supported.\");\n \t\tconfig->cqe_comp = 0;\n@@ -1463,7 +1463,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\thca_attr->log_max_static_sq_wq);\n \t\tDRV_LOG(DEBUG, \"WQE rate PP mode is %ssupported\",\n \t\t\thca_attr->qos.wqe_rate_pp ? \"\" : \"not \");\n-\t\tif (!sh->devx) {\n+\t\tif (!sh->cdev->config.devx) {\n \t\t\tDRV_LOG(ERR, \"DevX is required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n@@ -1519,7 +1519,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\tpriv->dev_port);\n \t\t}\n \t}\n-\tif (sh->devx) {\n+\tif (sh->cdev->config.devx) {\n \t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n \n \t\terr = hca_attr->access_register_user ?\n@@ -1676,7 +1676,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tif (mlx5_flex_item_port_init(eth_dev) < 0)\n \t\t\tgoto error;\n \t}\n-\tif (sh->devx && config->dv_flow_en && config->dest_tir) {\n+\tif (sh->cdev->config.devx && config->dv_flow_en && config->dest_tir) {\n \t\tpriv->obj_ops = devx_obj_ops;\n \t\tmlx5_queue_counter_id_prepare(eth_dev);\n \t\tpriv->obj_ops.lb_dummy_queue_create =\n@@ -2735,7 +2735,7 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)\n \t\t\trte_intr_fd_set(sh->intr_handle, -1);\n \t\t}\n \t}\n-\tif (sh->devx) {\n+\tif (sh->cdev->config.devx) {\n #ifdef HAVE_IBV_DEVX_ASYNC\n \t\tsh->intr_handle_devx =\n \t\t\trte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex 2b6eef44a7..722017efa4 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -998,7 +998,7 @@ mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \tqp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET;\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t/* If using DevX, need additional mask to read tisn value. */\n-\tif (priv->sh->devx && !priv->sh->tdn)\n+\tif (priv->sh->cdev->config.devx && !priv->sh->tdn)\n \t\tqp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;\n #endif\n \tobj.cq.in = txq_obj->cq;\n@@ -1042,7 +1042,7 @@ mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \t * This is done once per port.\n \t * Will use this value on Rx, when creating matching TIR.\n \t */\n-\tif (priv->sh->devx && !priv->sh->tdn) {\n+\tif (priv->sh->cdev->config.devx && !priv->sh->tdn) {\n \t\tret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn,\n \t\t\t\t\t\t &priv->sh->tdn);\n \t\tif (ret) {\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 920b174b96..b371a87355 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1182,7 +1182,6 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \tpthread_mutex_init(&sh->txpp.mutex, NULL);\n \tsh->numa_node = spawn->cdev->dev->numa_node;\n \tsh->cdev = spawn->cdev;\n-\tsh->devx = sh->cdev->config.devx;\n \tif (spawn->bond_info)\n \t\tsh->bond = *spawn->bond_info;\n \terr = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);\n@@ -1205,7 +1204,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\tsh->port[i].ih_port_id = RTE_MAX_ETHPORTS;\n \t\tsh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;\n \t}\n-\tif (sh->devx) {\n+\tif (sh->cdev->config.devx) {\n \t\tsh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);\n \t\tif (!sh->td) {\n \t\t\tDRV_LOG(ERR, \"TD allocation failure\");\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex ee485343ff..6bc7a34f60 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1146,7 +1146,6 @@ struct mlx5_flex_item {\n struct mlx5_dev_ctx_shared {\n \tLIST_ENTRY(mlx5_dev_ctx_shared) next;\n \tuint32_t refcnt;\n-\tuint32_t devx:1; /* Opened with DV. */\n \tuint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */\n \tuint32_t steering_format_version:4;\n \t/* Indicates the device steering logic format. */\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 5b0eee3321..801c467bba 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -723,7 +723,8 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_dev_config *config = &priv->config;\n \n-\tif (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) {\n+\tif (!priv->sh->cdev->config.devx || !config->dest_tir ||\n+\t !config->dv_flow_en) {\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 5a21803e18..907f3fd75a 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -9966,7 +9966,7 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev)\n \ttype = mlx5_flow_os_get_type();\n \tif (type == MLX5_FLOW_TYPE_MAX) {\n \t\ttype = MLX5_FLOW_TYPE_VERBS;\n-\t\tif (priv->sh->devx && priv->config.dv_flow_en)\n+\t\tif (priv->sh->cdev->config.devx && priv->config.dv_flow_en)\n \t\t\ttype = MLX5_FLOW_TYPE_DV;\n \t}\n \tfops = flow_get_drv_ops(type);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex b0ed9f93a0..4e60a54df3 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -3291,7 +3291,7 @@ flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \n-\tif (!priv->sh->devx)\n+\tif (!priv->sh->cdev->config.devx)\n \t\tgoto notsup_err;\n \tif (action_flags & MLX5_FLOW_ACTION_COUNT)\n \t\treturn rte_flow_error_set(error, EINVAL,\n@@ -5302,8 +5302,8 @@ flow_dv_validate_action_age(uint64_t action_flags,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tconst struct rte_flow_action_age *age = action->conf;\n \n-\tif (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&\n-\t !priv->sh->aso_age_mng))\n+\tif (!priv->sh->cdev->config.devx ||\n+\t (priv->sh->cmng.counter_fallback && !priv->sh->aso_age_mng))\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL,\n@@ -5587,7 +5587,8 @@ flow_dv_validate_action_sample(uint64_t *action_flags,\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\t \"ratio value starts from 1\");\n-\tif (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))\n+\tif (!priv->sh->cdev->config.devx ||\n+\t (sample->ratio > 0 && !priv->sampler_en))\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL,\n@@ -6175,7 +6176,7 @@ flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)\n \t\t\tage ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;\n \tuint32_t cnt_idx;\n \n-\tif (!priv->sh->devx) {\n+\tif (!priv->sh->cdev->config.devx) {\n \t\trte_errno = ENOTSUP;\n \t\treturn 0;\n \t}\n@@ -6498,7 +6499,7 @@ flow_dv_mtr_alloc(struct rte_eth_dev *dev)\n \tstruct mlx5_aso_mtr_pool *pool;\n \tuint32_t mtr_idx = 0;\n \n-\tif (!priv->sh->devx) {\n+\tif (!priv->sh->cdev->config.devx) {\n \t\trte_errno = ENOTSUP;\n \t\treturn 0;\n \t}\n@@ -12515,7 +12516,7 @@ flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)\n \tuint32_t ct_idx;\n \n \tMLX5_ASSERT(mng);\n-\tif (!priv->sh->devx) {\n+\tif (!priv->sh->cdev->config.devx) {\n \t\trte_errno = ENOTSUP;\n \t\treturn 0;\n \t}\n@@ -12953,7 +12954,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t}\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n-\t\t\tif (!priv->sh->devx) {\n+\t\t\tif (!priv->sh->cdev->config.devx) {\n \t\t\t\treturn rte_flow_error_set\n \t\t\t\t\t (error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -15834,7 +15835,7 @@ flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct rte_flow_query_count *qc = data;\n \n-\tif (!priv->sh->devx)\n+\tif (!priv->sh->cdev->config.devx)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL,\n@@ -15887,7 +15888,7 @@ flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \n-\tif (!priv->sh->devx || !action_ptr)\n+\tif (!priv->sh->cdev->config.devx || !action_ptr)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL,\n@@ -17491,7 +17492,7 @@ flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,\n \tuint64_t inn_pkts, inn_bytes;\n \tint ret;\n \n-\tif (!priv->sh->devx)\n+\tif (!priv->sh->cdev->config.devx)\n \t\treturn -1;\n \n \tret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 4bb0331464..1dfe7da435 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1104,7 +1104,7 @@ mlx5_dev_start(struct rte_eth_dev *dev)\n \t\t\tdev->data->port_id, strerror(rte_errno));\n \t\tgoto error;\n \t}\n-\tif ((priv->sh->devx && priv->config.dv_flow_en &&\n+\tif ((priv->sh->cdev->config.devx && priv->config.dv_flow_en &&\n \t priv->config.dest_tir) && priv->obj_ops.lb_dummy_queue_create) {\n \t\tret = priv->obj_ops.lb_dummy_queue_create(dev);\n \t\tif (ret)\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 3d8bd2e100..5396365ec9 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -275,7 +275,7 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n \tfallback = true;\n #else\n \tfallback = false;\n-\tif (!sh->devx || !priv->config.dv_flow_en ||\n+\tif (!sh->cdev->config.devx || !priv->config.dv_flow_en ||\n \t !hca_attr->flow_counters_dump ||\n \t !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||\n \t (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))\n@@ -476,7 +476,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tDRV_LOG(WARNING, \"Rx CQE compression isn't supported.\");\n \t\tconfig->cqe_comp = 0;\n \t}\n-\tif (sh->devx) {\n+\tif (sh->cdev->config.devx) {\n \t\thca_attr = &sh->cdev->config.hca_attr;\n \t\tconfig->hw_csum = hca_attr->csum_cap;\n \t\tDRV_LOG(DEBUG, \"checksum offloading is %ssupported\",\n@@ -661,7 +661,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tgoto error;\n \t\t}\n \t}\n-\tif (sh->devx) {\n+\tif (sh->cdev->config.devx) {\n \t\tpriv->obj_ops = devx_obj_ops;\n \t} else {\n \t\tDRV_LOG(ERR, \"Windows flow must be DevX.\");\n", "prefixes": [ "08/20" ] }