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{
    "id": 10654,
    "url": "http://patches.dpdk.org/api/patches/10654/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1455806076-18497-23-git-send-email-helin.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1455806076-18497-23-git-send-email-helin.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1455806076-18497-23-git-send-email-helin.zhang@intel.com",
    "date": "2016-02-18T14:34:28",
    "name": "[dpdk-dev,v3,22/30] i40e/base: use FW to read/write rx control registers",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8da3cf6be3bbd0674e7483c42ff33524d013994e",
    "submitter": {
        "id": 14,
        "url": "http://patches.dpdk.org/api/people/14/?format=api",
        "name": "Zhang, Helin",
        "email": "helin.zhang@intel.com"
    },
    "delegate": {
        "id": 10,
        "url": "http://patches.dpdk.org/api/users/10/?format=api",
        "username": "bruce",
        "first_name": "Bruce",
        "last_name": "Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1455806076-18497-23-git-send-email-helin.zhang@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/10654/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/10654/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 24BA7C444;\n\tThu, 18 Feb 2016 15:35:33 +0100 (CET)",
            "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id 3B932C3B8\n\tfor <dev@dpdk.org>; Thu, 18 Feb 2016 15:35:31 +0100 (CET)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga104.fm.intel.com with ESMTP; 18 Feb 2016 06:35:30 -0800",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga002.fm.intel.com with ESMTP; 18 Feb 2016 06:35:30 -0800",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id u1IEZSDj019338;\n\tThu, 18 Feb 2016 22:35:28 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid u1IEZPgh018693; Thu, 18 Feb 2016 22:35:27 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u1IEZPgI018689; \n\tThu, 18 Feb 2016 22:35:25 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.22,465,1449561600\"; d=\"scan'208\";a=\"918505428\"",
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Thu, 18 Feb 2016 22:34:28 +0800",
        "Message-Id": "<1455806076-18497-23-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1455806076-18497-1-git-send-email-helin.zhang@intel.com>",
        "References": "<1455776683-11790-1-git-send-email-helin.zhang@intel.com>\n\t<1455806076-18497-1-git-send-email-helin.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 22/30] i40e/base: use FW to read/write rx\n\tcontrol registers",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "RX control register read/write functions are added, as directly\nread/write may fail when under stress small traffic. After the\nadminq is ready, all rx control registers should be read/written\nby dedicated functions.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n drivers/net/i40e/base/i40e_adminq_cmd.h |  16 ++++\n drivers/net/i40e/base/i40e_common.c     | 126 +++++++++++++++++++++++++++++++-\n drivers/net/i40e/base/i40e_osdep.h      |  36 +++++++++\n drivers/net/i40e/base/i40e_prototype.h  |   8 ++\n 4 files changed, 184 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h\nindex 165df9b..12ebd35 100644\n--- a/drivers/net/i40e/base/i40e_adminq_cmd.h\n+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h\n@@ -165,6 +165,8 @@ enum i40e_admin_queue_opc {\n \ti40e_aqc_opc_set_port_parameters\t= 0x0203,\n \ti40e_aqc_opc_get_switch_resource_alloc\t= 0x0204,\n \ti40e_aqc_opc_set_switch_config\t\t= 0x0205,\n+\ti40e_aqc_opc_rx_ctl_reg_read\t\t= 0x0206,\n+\ti40e_aqc_opc_rx_ctl_reg_write\t\t= 0x0207,\n \n \ti40e_aqc_opc_add_vsi\t\t\t= 0x0210,\n \ti40e_aqc_opc_update_vsi_parameters\t= 0x0211,\n@@ -752,6 +754,20 @@ struct i40e_aqc_set_switch_config {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);\n \n+/* Read Receive control registers  (direct 0x0206)\n+ * Write Receive control registers (direct 0x0207)\n+ *     used for accessing Rx control registers that can be\n+ *     slow and need special handling when under high Rx load\n+ */\n+struct i40e_aqc_rx_ctl_reg_read_write {\n+\t__le32 reserved1;\n+\t__le32 address;\n+\t__le32 reserved2;\n+\t__le32 value;\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);\n+\n /* Add VSI (indirect 0x0210)\n  *    this indirect command uses struct i40e_aqc_vsi_properties_data\n  *    as the indirect buffer (128 bytes)\ndiff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c\nindex e94f726..ef3425e 100644\n--- a/drivers/net/i40e/base/i40e_common.c\n+++ b/drivers/net/i40e/base/i40e_common.c\n@@ -5356,7 +5356,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,\n \t\treturn ret;\n \n \t/* Read the PF Queue Filter control register */\n-\tval = rd32(hw, I40E_PFQF_CTL_0);\n+\tval = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);\n \n \t/* Program required PE hash buckets for the PF */\n \tval &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;\n@@ -5393,7 +5393,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,\n \tif (settings->enable_macvlan)\n \t\tval |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;\n \n-\twr32(hw, I40E_PFQF_CTL_0, val);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);\n \n \treturn I40E_SUCCESS;\n }\n@@ -6317,6 +6317,128 @@ restore_config:\n \treturn status;\n }\n #endif /* PF_DRIVER */\n+\n+/**\n+ * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: ptr to register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Use the firmware to read the Rx control register,\n+ * especially useful if the Rx unit is under heavy pressure\n+ **/\n+enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 *reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =\n+\t\t(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n+\tenum i40e_status_code status;\n+\n+\tif (reg_val == NULL)\n+\t\treturn I40E_ERR_PARAM;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);\n+\n+\tcmd_resp->address = CPU_TO_LE32(reg_addr);\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\n+\tif (status == I40E_SUCCESS)\n+\t\t*reg_val = LE32_TO_CPU(cmd_resp->value);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_read_rx_ctl - read from an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ **/\n+u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)\n+{\n+\tenum i40e_status_code status = I40E_SUCCESS;\n+\tbool use_register;\n+\tint retry = 5;\n+\tu32 val = 0;\n+\n+\tuse_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);\n+\tif (!use_register) {\n+do_retry:\n+\t\tstatus = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);\n+\t\tif (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {\n+\t\t\ti40e_msec_delay(1);\n+\t\t\tretry--;\n+\t\t\tgoto do_retry;\n+\t\t}\n+\t}\n+\n+\t/* if the AQ access failed, try the old-fashioned way */\n+\tif (status || use_register)\n+\t\tval = rd32(hw, reg_addr);\n+\n+\treturn val;\n+}\n+\n+/**\n+ * i40e_aq_rx_ctl_write_register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Use the firmware to write to an Rx control register,\n+ * especially useful if the Rx unit is under heavy pressure\n+ **/\n+enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_rx_ctl_reg_read_write *cmd =\n+\t\t(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n+\tenum i40e_status_code status;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);\n+\n+\tcmd->address = CPU_TO_LE32(reg_addr);\n+\tcmd->value = CPU_TO_LE32(reg_val);\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_write_rx_ctl - write to an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: register value\n+ **/\n+void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)\n+{\n+\tenum i40e_status_code status = I40E_SUCCESS;\n+\tbool use_register;\n+\tint retry = 5;\n+\n+\tuse_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);\n+\tif (!use_register) {\n+do_retry:\n+\t\tstatus = i40e_aq_rx_ctl_write_register(hw, reg_addr,\n+\t\t\t\t\t\t       reg_val, NULL);\n+\t\tif (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {\n+\t\t\ti40e_msec_delay(1);\n+\t\t\tretry--;\n+\t\t\tgoto do_retry;\n+\t\t}\n+\t}\n+\n+\t/* if the AQ access failed, try the old-fashioned way */\n+\tif (status || use_register)\n+\t\twr32(hw, reg_addr, reg_val);\n+}\n #ifdef VF_DRIVER\n \n /**\ndiff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h\nindex 71077f0..8c84ed8 100644\n--- a/drivers/net/i40e/base/i40e_osdep.h\n+++ b/drivers/net/i40e/base/i40e_osdep.h\n@@ -117,6 +117,42 @@ do {                                                            \\\n \t\t\t\t\t##__VA_ARGS__);         \\\n } while (0)\n \n+/* AQ commands based interfaces of i40e_read_rx_ctl() and i40e_write_rx_ctl()\n+ * are required for reading/writing below registers, as reading/writing it\n+ * directly may not function correctly if the device is under heavy small\n+ * packet traffic. Note that those interfaces are available from FVL5 and not\n+ * suitable before the AdminQ is ready during initialization.\n+ *\n+ * I40E_PFQF_CTL_0\n+ * I40E_PFQF_HENA\n+ * I40E_PFQF_FDALLOC\n+ * I40E_PFQF_HREGION\n+ * I40E_PFLAN_QALLOC\n+ * I40E_VPQF_CTL\n+ * I40E_VFQF_HENA\n+ * I40E_VFQF_HREGION\n+ * I40E_VSIQF_CTL\n+ * I40E_VSILAN_QBASE\n+ * I40E_VSILAN_QTABLE\n+ * I40E_VSIQF_TCREGION\n+ * I40E_PFQF_HKEY\n+ * I40E_VFQF_HKEY\n+ * I40E_PRTQF_CTL_0\n+ * I40E_GLFCOE_RCTL\n+ * I40E_GLFCOE_RSOF\n+ * I40E_GLQF_CTL\n+ * I40E_GLQF_SWAP\n+ * I40E_GLQF_HASH_MSK\n+ * I40E_GLQF_HASH_INSET\n+ * I40E_GLQF_HSYM\n+ * I40E_GLQF_FC_MSK\n+ * I40E_GLQF_FC_INSET\n+ * I40E_GLQF_FD_MSK\n+ * I40E_PRTQF_FD_INSET\n+ * I40E_PRTQF_FD_FLXINSET\n+ * I40E_PRTQF_FD_MSK\n+ */\n+\n #define I40E_PCI_REG(reg)         (*((volatile uint32_t *)(reg)))\n #define I40E_PCI_REG_ADDR(a, reg) \\\n \t((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))\ndiff --git a/drivers/net/i40e/base/i40e_prototype.h b/drivers/net/i40e/base/i40e_prototype.h\nindex e0a409f..674430d 100644\n--- a/drivers/net/i40e/base/i40e_prototype.h\n+++ b/drivers/net/i40e/base/i40e_prototype.h\n@@ -516,6 +516,14 @@ enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,\n \t\t\t\t\t\t    u16 vsi_seid);\n+enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 *reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);\n+enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);\n #ifdef X722_SUPPORT\n enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,\n \t\t\tstruct i40e_aqc_arp_proxy_data *proxy_config,\n",
    "prefixes": [
        "dpdk-dev",
        "v3",
        "22/30"
    ]
}