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GET /api/patches/105800/?format=api
{ "id": 105800, "url": "http://patches.dpdk.org/api/patches/105800/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220114031036.19052-4-johndale@cisco.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220114031036.19052-4-johndale@cisco.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220114031036.19052-4-johndale@cisco.com", "date": "2022-01-14T03:10:36", "name": "[3/3] net/enic: support max descriptors allowed by adapter", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "695ce5836ddb1e9de6375a73d69f1ed546fd1e69", "submitter": { "id": 359, "url": "http://patches.dpdk.org/api/people/359/?format=api", "name": "John Daley (johndale)", "email": "johndale@cisco.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220114031036.19052-4-johndale@cisco.com/mbox/", "series": [ { "id": 21162, "url": "http://patches.dpdk.org/api/series/21162/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21162", "date": "2022-01-14T03:10:33", "name": "enic PMD patches", "version": 1, "mbox": "http://patches.dpdk.org/series/21162/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105800/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105800/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B4B25A00C3;\n\tFri, 14 Jan 2022 04:11:32 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A640D42758;\n\tFri, 14 Jan 2022 04:11:32 +0100 (CET)", "from alln-iport-1.cisco.com (alln-iport-1.cisco.com [173.37.142.88])\n by mails.dpdk.org (Postfix) with ESMTP id 47B0B40DDD\n for <dev@dpdk.org>; Fri, 14 Jan 2022 04:11:31 +0100 (CET)", "from alln-core-9.cisco.com ([173.36.13.129])\n by alln-iport-1.cisco.com with ESMTP/TLS/DHE-RSA-SEED-SHA;\n 14 Jan 2022 03:11:30 +0000", "from cisco.com (savbu-usnic-a.cisco.com [10.193.184.48])\n by alln-core-9.cisco.com (8.15.2/8.15.2) with ESMTP id 20E3BUTa010646;\n Fri, 14 Jan 2022 03:11:30 GMT", "by cisco.com (Postfix, from userid 392789)\n id 10FDE20F2003; Thu, 13 Jan 2022 19:11:30 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=cisco.com; i=@cisco.com; l=7001; q=dns/txt; s=iport;\n t=1642129891; x=1643339491;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=JEPfsyqXvchHQpF7g4QCUYN+LQk8HwGMeizV2GZWcFs=;\n b=CzN0r5rHXuRqCmQDFX+0CO/latv/ymL3tv5hPCIpUZJ1nDYBK0CMFaO7\n TcnSGPnyYbrKkoHo9/BkLug6As4gg7HkpysdBl0jKeBFcXQdnYz0D/4Jf\n qWxb3DoUpiBd/LJLEDnXNnpwWhOiWPahyVgr3a35BZRgbq3kecV9fGZFE k=;", "X-IronPort-AV": "E=Sophos;i=\"5.88,287,1635206400\"; d=\"scan'208\";a=\"798076125\"", "From": "John Daley <johndale@cisco.com>", "To": "ferruh.yigit@intel.com, arybchenko@solarflare.com", "Cc": "dev@dpdk.org, John Daley <johndale@cisco.com>,\n Hyong Youb Kim <hyonkim@cisco.com>", "Subject": "[PATCH 3/3] net/enic: support max descriptors allowed by adapter", "Date": "Thu, 13 Jan 2022 19:10:36 -0800", "Message-Id": "<20220114031036.19052-4-johndale@cisco.com>", "X-Mailer": "git-send-email 2.33.1", "In-Reply-To": "<20220114031036.19052-1-johndale@cisco.com>", "References": "<20220114031036.19052-1-johndale@cisco.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Outbound-SMTP-Client": "10.193.184.48, savbu-usnic-a.cisco.com", "X-Outbound-Node": "alln-core-9.cisco.com", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Newer VIC adapters have the max number of supported RX and TX\ndescriptors in their configuration. Use these values as the\nmaximums.\n\nSigned-off-by: John Daley <johndale@cisco.com>\nReviewed-by: Hyong Youb Kim <hyonkim@cisco.com>\n---\n drivers/net/enic/base/cq_enet_desc.h | 6 ++++-\n drivers/net/enic/enic_res.c | 20 +++++++++++++----\n drivers/net/enic/enic_res.h | 6 +++--\n drivers/net/enic/enic_rxtx.c | 33 +++++++++++++++++++---------\n 4 files changed, 48 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/enic/base/cq_enet_desc.h b/drivers/net/enic/base/cq_enet_desc.h\nindex a34a4f5400..02db85b9a0 100644\n--- a/drivers/net/enic/base/cq_enet_desc.h\n+++ b/drivers/net/enic/base/cq_enet_desc.h\n@@ -67,7 +67,8 @@ struct cq_enet_rq_desc_64 {\n \tuint16_t vlan;\n \tuint16_t checksum_fcoe;\n \tuint8_t flags;\n-\tuint8_t unused[48];\n+\tuint8_t fetch_idx_flags;\n+\tuint8_t unused[47];\n \tuint8_t type_color;\n };\n \n@@ -92,6 +93,9 @@ struct cq_enet_rq_desc_64 {\n #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS 14\n #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \\\n \t((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1)\n+#define CQ_ENET_RQ_DESC_FETCH_IDX_BITS 2\n+#define CQ_ENET_RQ_DESC_FETCH_IDX_MASK \\\n+\t((1 << CQ_ENET_RQ_DESC_FETCH_IDX_BITS) - 1)\n #define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED (0x1 << 14)\n #define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED (0x1 << 15)\n \ndiff --git a/drivers/net/enic/enic_res.c b/drivers/net/enic/enic_res.c\nindex 9cfb857939..caf773bab2 100644\n--- a/drivers/net/enic/enic_res.c\n+++ b/drivers/net/enic/enic_res.c\n@@ -26,6 +26,7 @@ int enic_get_vnic_config(struct enic *enic)\n \tstruct vnic_enet_config *c = &enic->config;\n \tint err;\n \tuint64_t sizes;\n+\tuint32_t max_rq_descs, max_wq_descs;\n \n \terr = vnic_dev_get_mac_addr(enic->vdev, enic->mac_addr);\n \tif (err) {\n@@ -57,6 +58,8 @@ int enic_get_vnic_config(struct enic *enic)\n \tGET_CONFIG(loop_tag);\n \tGET_CONFIG(num_arfs);\n \tGET_CONFIG(max_pkt_size);\n+\tGET_CONFIG(max_rq_ring);\n+\tGET_CONFIG(max_wq_ring);\n \n \t/* max packet size is only defined in newer VIC firmware\n \t * and will be 0 for legacy firmware and VICs\n@@ -101,20 +104,29 @@ int enic_get_vnic_config(struct enic *enic)\n \t\t((enic->filter_actions & FILTER_ACTION_COUNTER_FLAG) ?\n \t\t \"count \" : \"\"));\n \n-\tc->wq_desc_count = RTE_MIN((uint32_t)ENIC_MAX_WQ_DESCS,\n+\t/* The max size of RQ and WQ rings are specified in 1500 series VICs and\n+\t * beyond. If they are not specified by the VIC or if 64B CQ descriptors\n+\t * are not being used, the max number of descriptors is 4096.\n+\t */\n+\tmax_wq_descs = (enic->cq64_request && c->max_wq_ring) ? c->max_wq_ring :\n+\t\t ENIC_LEGACY_MAX_WQ_DESCS;\n+\tc->wq_desc_count = RTE_MIN(max_wq_descs,\n \t\t\tRTE_MAX((uint32_t)ENIC_MIN_WQ_DESCS, c->wq_desc_count));\n \tc->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */\n-\n-\tc->rq_desc_count = RTE_MIN((uint32_t)ENIC_MAX_RQ_DESCS,\n+\tmax_rq_descs = (enic->cq64_request && c->max_rq_ring) ? c->max_rq_ring\n+\t\t : ENIC_LEGACY_MAX_WQ_DESCS;\n+\tc->rq_desc_count = RTE_MIN(max_rq_descs,\n \t\t\tRTE_MAX((uint32_t)ENIC_MIN_RQ_DESCS, c->rq_desc_count));\n \tc->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */\n+\tdev_debug(NULL, \"Max supported VIC descriptors: WQ:%u, RQ:%u\\n\",\n+\t\t max_wq_descs, max_rq_descs);\n \n \tc->intr_timer_usec = RTE_MIN(c->intr_timer_usec,\n \t\t\t\t vnic_dev_get_intr_coal_timer_max(enic->vdev));\n \n \tdev_info(enic_get_dev(enic),\n \t\t\"vNIC MAC addr \" RTE_ETHER_ADDR_PRT_FMT\n-\t\t\"wq/rq %d/%d mtu %d, max mtu:%d\\n\",\n+\t\t\" wq/rq %d/%d mtu %d, max mtu:%d\\n\",\n \t\tenic->mac_addr[0], enic->mac_addr[1], enic->mac_addr[2],\n \t\tenic->mac_addr[3], enic->mac_addr[4], enic->mac_addr[5],\n \t\tc->wq_desc_count, c->rq_desc_count,\ndiff --git a/drivers/net/enic/enic_res.h b/drivers/net/enic/enic_res.h\nindex 34f15d5a42..ae979d52be 100644\n--- a/drivers/net/enic/enic_res.h\n+++ b/drivers/net/enic/enic_res.h\n@@ -12,9 +12,11 @@\n #include \"vnic_rq.h\"\n \n #define ENIC_MIN_WQ_DESCS\t\t64\n-#define ENIC_MAX_WQ_DESCS\t\t4096\n #define ENIC_MIN_RQ_DESCS\t\t64\n-#define ENIC_MAX_RQ_DESCS\t\t4096\n+\n+/* 1400 series VICs and prior all have 4K max, after that it's in the config */\n+#define ENIC_LEGACY_MAX_WQ_DESCS 4096\n+#define ENIC_LEGACY_MAX_RQ_DESCS 4096\n \n /* A descriptor ring has a multiple of 32 descriptors */\n #define ENIC_ALIGN_DESCS\t\t32\ndiff --git a/drivers/net/enic/enic_rxtx.c b/drivers/net/enic/enic_rxtx.c\nindex c44715bfd0..4681ef6eca 100644\n--- a/drivers/net/enic/enic_rxtx.c\n+++ b/drivers/net/enic/enic_rxtx.c\n@@ -84,6 +84,7 @@ enic_recv_pkts_common(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tuint8_t packet_error;\n \t\tuint16_t ciflags;\n \t\tuint8_t tc;\n+\t\tuint16_t rq_idx_msbs = 0;\n \n \t\tmax_rx--;\n \n@@ -94,17 +95,24 @@ enic_recv_pkts_common(void *rx_queue, struct rte_mbuf **rx_pkts,\n \n \t\t/* Get the cq descriptor and extract rq info from it */\n \t\tcqd = *cqd_ptr;\n+\n \t\t/*\n-\t\t * The first 16B of 64B descriptor is identical to the\n-\t\t * 16B descriptor, except type_color. Copy type_color\n-\t\t * from the 64B descriptor into the 16B descriptor's\n-\t\t * field, so the code below can assume the 16B\n-\t\t * descriptor format.\n+\t\t * The first 16B of a 64B descriptor is identical to a 16B\n+\t\t * descriptor except for the type_color and fetch index. Extract\n+\t\t * fetch index and copy the type_color from the 64B to where it\n+\t\t * would be in a 16B descriptor so sebwequent code can run\n+\t\t * without further conditionals.\n \t\t */\n-\t\tif (use_64b_desc)\n+\t\tif (use_64b_desc) {\n+\t\t\trq_idx_msbs = (((volatile struct cq_enet_rq_desc_64 *)\n+\t\t\t\t cqd_ptr)->fetch_idx_flags\n+\t\t\t\t & CQ_ENET_RQ_DESC_FETCH_IDX_MASK)\n+\t\t\t\t << CQ_DESC_COMP_NDX_BITS;\n \t\t\tcqd.type_color = tc;\n+\t\t}\n \t\trq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;\n-\t\trq_idx = cqd.completed_index & CQ_DESC_COMP_NDX_MASK;\n+\t\trq_idx = rq_idx_msbs +\n+\t\t\t (cqd.completed_index & CQ_DESC_COMP_NDX_MASK);\n \n \t\trq = &enic->rq[rq_num];\n \t\trqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;\n@@ -362,14 +370,19 @@ static inline void enic_free_wq_bufs(struct vnic_wq *wq,\n \t\t\t\t uint16_t completed_index)\n {\n \tstruct rte_mbuf *buf;\n-\tstruct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];\n+\tstruct rte_mbuf *m, *free[ENIC_LEGACY_MAX_WQ_DESCS];\n \tunsigned int nb_to_free, nb_free = 0, i;\n \tstruct rte_mempool *pool;\n \tunsigned int tail_idx;\n \tunsigned int desc_count = wq->ring.desc_count;\n \n-\tnb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)\n-\t\t\t\t + 1;\n+\t/*\n+\t * On 1500 Series VIC and beyond, greater than ENIC_LEGACY_MAX_WQ_DESCS\n+\t * may be attempted to be freed. Cap it at ENIC_LEGACY_MAX_WQ_DESCS.\n+\t */\n+\tnb_to_free = RTE_MIN(enic_ring_sub(desc_count, wq->tail_idx,\n+\t\t\t completed_index) + 1,\n+\t\t\t (uint32_t)ENIC_LEGACY_MAX_WQ_DESCS);\n \ttail_idx = wq->tail_idx;\n \tpool = wq->bufs[tail_idx]->pool;\n \tfor (i = 0; i < nb_to_free; i++) {\n", "prefixes": [ "3/3" ] }