Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/105701/?format=api
{ "id": 105701, "url": "http://patches.dpdk.org/api/patches/105701/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220109111130.751933-2-skori@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220109111130.751933-2-skori@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220109111130.751933-2-skori@marvell.com", "date": "2022-01-09T11:11:30", "name": "[v1,2/2] net/cnxk: support priority flow control", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9ecec45ac0beccad0e238c0bb98fc2d223120a1a", "submitter": { "id": 1318, "url": "http://patches.dpdk.org/api/people/1318/?format=api", "name": "Sunil Kumar Kori", "email": "skori@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220109111130.751933-2-skori@marvell.com/mbox/", "series": [ { "id": 21102, "url": "http://patches.dpdk.org/api/series/21102/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21102", "date": "2022-01-09T11:11:29", "name": "[v1,1/2] common/cnxk: support priority flow ctrl config API", "version": 1, "mbox": "http://patches.dpdk.org/series/21102/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105701/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/105701/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A2AE2A0351;\n\tSun, 9 Jan 2022 12:11:47 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9595141155;\n\tSun, 9 Jan 2022 12:11:42 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 2D411410F5\n for <dev@dpdk.org>; Sun, 9 Jan 2022 12:11:40 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 209AGEsw011795\n for <dev@dpdk.org>; Sun, 9 Jan 2022 03:11:39 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3dfb0p9y6b-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 09 Jan 2022 03:11:39 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sun, 9 Jan 2022 03:11:37 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 9 Jan 2022 03:11:37 -0800", "from localhost.localdomain (unknown [10.28.34.25])\n by maili.marvell.com (Postfix) with ESMTP id CCB343F70A8;\n Sun, 9 Jan 2022 03:11:35 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=QB3By0vSMesO6T2y2EQhFBoGcvOBxgL/yCzoRwp/ZTQ=;\n b=CEhwszcmIkgiaC5PQWtpiu98eZ1pzWDNtgoBi/tI+xhPc1YUoAS8R3JPpCvz3LP9sEDc\n OyFaxWpO/vKVHyqEncaLCmUYEyEtHcwuoFjJkm5XWXMMO5OVpfM8uW2uL+7FF1wDg1KO\n TFNNLxVpj/GV0cHBkRdtbuoi+dQ0n0JjBMOl/TenGmHKraYWh4kGDjDdjx2gJRRXqWG0\n TD2PxQ3ZlkUtOXh/CjpKeknP61qOIRub8l9Phs5J2DfzPpyBZUSLhaKfFovOVY9IJJsf\n 6FWYEDOws2EqhO27T6WjColkF43JQ5ulHeMNkilCX5UoTURrjbXMbJgc9CirBgqECc/d Ow==", "From": "<skori@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v1 2/2] net/cnxk: support priority flow control", "Date": "Sun, 9 Jan 2022 16:41:30 +0530", "Message-ID": "<20220109111130.751933-2-skori@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220109111130.751933-1-skori@marvell.com>", "References": "<20220109111130.751933-1-skori@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "vDg05wge16LSbty4rrPKOPqu_QQ8bvHM", "X-Proofpoint-GUID": "vDg05wge16LSbty4rrPKOPqu_QQ8bvHM", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-01-09_04,2022-01-07_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nPatch implements priority flow control support for CNXK platforms.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/net/cnxk/cnxk_ethdev.c | 19 ++++\n drivers/net/cnxk/cnxk_ethdev.h | 16 +++\n drivers/net/cnxk/cnxk_ethdev_ops.c | 177 +++++++++++++++++++++++++++--\n 3 files changed, 203 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 74f625553d..382d88bbf3 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -1260,6 +1260,8 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto cq_fini;\n \t}\n \n+\t/* Initialize TC to SQ mapping as invalid */\n+\tmemset(dev->pfc_tc_sq_map, 0xFF, sizeof(dev->pfc_tc_sq_map));\n \t/*\n \t * Restore queue config when reconfigure followed by\n \t * reconfigure and no queue configure invoked from application case.\n@@ -1548,6 +1550,7 @@ struct eth_dev_ops cnxk_eth_dev_ops = {\n \t.tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,\n \t.flow_ctrl_get = cnxk_nix_flow_ctrl_get,\n \t.flow_ctrl_set = cnxk_nix_flow_ctrl_set,\n+\t.priority_flow_ctrl_queue_set = cnxk_nix_priority_flow_ctrl_queue_set,\n \t.dev_set_link_up = cnxk_nix_set_link_up,\n \t.dev_set_link_down = cnxk_nix_set_link_down,\n \t.get_module_info = cnxk_nix_get_module_info,\n@@ -1721,6 +1724,8 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n \tconst struct eth_dev_ops *dev_ops = eth_dev->dev_ops;\n+\tstruct rte_eth_pfc_queue_conf pfc_conf = {0};\n+\tstruct rte_eth_fc_conf fc_conf = {0};\n \tstruct roc_nix *nix = &dev->nix;\n \tint rc, i;\n \n@@ -1736,6 +1741,20 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)\n \n \troc_nix_npc_rx_ena_dis(nix, false);\n \n+\t/* Restore 802.3 Flow control configuration */\n+\tfc_conf.mode = RTE_ETH_FC_NONE;\n+\trc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);\n+\n+\tpfc_conf.mode = RTE_ETH_FC_NONE;\n+\tpfc_conf.rx_pause.tc = roc_nix_chan_count_get(nix) - 1;\n+\tpfc_conf.tx_pause.tc = roc_nix_chan_count_get(nix) - 1;\n+\trc = cnxk_nix_priority_flow_ctrl_queue_set(eth_dev, &pfc_conf);\n+\tif (rc)\n+\t\tplt_err(\"Failed to reset PFC. error code(%d)\", rc);\n+\n+\tfc_conf.mode = RTE_ETH_FC_FULL;\n+\trc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);\n+\n \t/* Disable and free rte_meter entries */\n \tnix_meter_fini(dev);\n \ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 5bfda3d815..28fb19307a 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -143,6 +143,16 @@ struct cnxk_fc_cfg {\n \tuint8_t tx_pause;\n };\n \n+struct cnxk_pfc_cfg {\n+\tstruct cnxk_fc_cfg fc_cfg;\n+\tuint16_t class_en;\n+\tuint16_t pause_time;\n+\tuint8_t rx_tc;\n+\tuint8_t rx_qid;\n+\tuint8_t tx_tc;\n+\tuint8_t tx_qid;\n+};\n+\n struct cnxk_eth_qconf {\n \tunion {\n \t\tstruct rte_eth_txconf tx;\n@@ -366,6 +376,8 @@ struct cnxk_eth_dev {\n \tstruct cnxk_eth_qconf *rx_qconf;\n \n \t/* Flow control configuration */\n+\tuint16_t pfc_tc_sq_map[16];\n+\tstruct cnxk_pfc_cfg pfc_cfg;\n \tstruct cnxk_fc_cfg fc_cfg;\n \n \t/* PTP Counters */\n@@ -467,6 +479,8 @@ int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \t\t\t struct rte_eth_fc_conf *fc_conf);\n int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n \t\t\t struct rte_eth_fc_conf *fc_conf);\n+int cnxk_nix_priority_flow_ctrl_queue_set(struct rte_eth_dev *eth_dev,\n+\t\t\t\t\t struct rte_eth_pfc_queue_conf *pfc_conf);\n int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);\n int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);\n int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,\n@@ -606,6 +620,8 @@ int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,\n \t\t\t\t uint32_t *prev_id, uint32_t *next_id,\n \t\t\t\t struct cnxk_mtr_policy_node *policy,\n \t\t\t\t int *tree_level);\n+int nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,\n+\t\t\t\t struct cnxk_pfc_cfg *conf);\n \n /* Inlines */\n static __rte_always_inline uint64_t\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c\nindex ce5f1f7240..27fa2da36d 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_ops.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c\n@@ -69,6 +69,8 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)\n \tdevinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |\n \t\t\t RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;\n \tdevinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;\n+\n+\tdevinfo->pfc_queue_tc_max = roc_nix_chan_count_get(&dev->nix);\n \treturn 0;\n }\n \n@@ -230,6 +232,8 @@ nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable)\n \tcq = &dev->cqs[qid];\n \tfc_cfg.type = ROC_NIX_FC_CQ_CFG;\n \tfc_cfg.cq_cfg.enable = enable;\n+\t/* Map all CQs to last channel */\n+\tfc_cfg.cq_cfg.tc = roc_nix_chan_count_get(nix) - 1;\n \tfc_cfg.cq_cfg.rq = qid;\n \tfc_cfg.cq_cfg.cq_drop = cq->drop_thresh;\n \n@@ -248,6 +252,8 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \tstruct rte_eth_dev_data *data = eth_dev->data;\n \tstruct cnxk_fc_cfg *fc = &dev->fc_cfg;\n \tstruct roc_nix *nix = &dev->nix;\n+\tstruct cnxk_eth_rxq_sp *rxq;\n+\tstruct cnxk_eth_txq_sp *txq;\n \tuint8_t rx_pause, tx_pause;\n \tint rc, i;\n \n@@ -282,7 +288,12 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \t\t}\n \n \t\tfor (i = 0; i < data->nb_rx_queues; i++) {\n-\t\t\trc = nix_fc_cq_config_set(dev, i, tx_pause);\n+\t\t\tstruct roc_nix_fc_cfg fc_cfg;\n+\n+\t\t\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\t\t\trxq = ((struct cnxk_eth_rxq_sp *)\n+\t\t\t\tdata->rx_queues[i]) - 1;\n+\t\t\trc = nix_fc_cq_config_set(dev, rxq->qid, !!tx_pause);\n \t\t\tif (rc)\n \t\t\t\treturn rc;\n \t\t}\n@@ -290,14 +301,19 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \n \t/* Check if RX pause frame is enabled or not */\n \tif (fc->rx_pause ^ rx_pause) {\n-\t\tstruct roc_nix_fc_cfg fc_cfg;\n-\n-\t\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n-\t\tfc_cfg.type = ROC_NIX_FC_TM_CFG;\n-\t\tfc_cfg.tm_cfg.enable = !!rx_pause;\n-\t\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n-\t\tif (rc)\n-\t\t\treturn rc;\n+\t\tfor (i = 0; i < data->nb_tx_queues; i++) {\n+\t\t\tstruct roc_nix_fc_cfg fc_cfg;\n+\n+\t\t\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\t\t\ttxq = ((struct cnxk_eth_txq_sp *)\n+\t\t\t\tdata->tx_queues[i]) - 1;\n+\t\t\tfc_cfg.type = ROC_NIX_FC_TM_CFG;\n+\t\t\tfc_cfg.tm_cfg.sq = txq->qid;\n+\t\t\tfc_cfg.tm_cfg.enable = !!rx_pause;\n+\t\t\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n \t}\n \n \trc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]);\n@@ -311,6 +327,29 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \treturn rc;\n }\n \n+int\n+cnxk_nix_priority_flow_ctrl_queue_set(struct rte_eth_dev *eth_dev,\n+\t\t\t\t struct rte_eth_pfc_queue_conf *pfc_conf)\n+{\n+\tstruct cnxk_pfc_cfg conf = {0};\n+\tint rc;\n+\n+\tconf.fc_cfg.mode = pfc_conf->mode;\n+\n+\tconf.pause_time = pfc_conf->tx_pause.pause_time;\n+\tconf.rx_tc = pfc_conf->tx_pause.tc;\n+\tconf.rx_qid = pfc_conf->tx_pause.rx_qid;\n+\n+\tconf.tx_tc = pfc_conf->rx_pause.tc;\n+\tconf.tx_qid = pfc_conf->rx_pause.tx_qid;\n+\n+\trc = nix_priority_flow_ctrl_configure(eth_dev, &conf);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn rc;\n+}\n+\n int\n cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev,\n \t\t const struct rte_flow_ops **ops)\n@@ -911,3 +950,123 @@ cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,\n \n \treturn 0;\n }\n+\n+int\n+nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,\n+\t\t\t\t struct cnxk_pfc_cfg *conf)\n+{\n+\tenum roc_nix_fc_mode mode_map[] = {ROC_NIX_FC_NONE, ROC_NIX_FC_RX,\n+\t\t\t\t\t ROC_NIX_FC_TX, ROC_NIX_FC_FULL};\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct cnxk_pfc_cfg *pfc = &dev->pfc_cfg;\n+\tstruct roc_nix *nix = &dev->nix;\n+\tstruct roc_nix_pfc_cfg pfc_cfg;\n+\tstruct roc_nix_fc_cfg fc_cfg;\n+\tstruct cnxk_eth_rxq_sp *rxq;\n+\tstruct cnxk_eth_txq_sp *txq;\n+\tuint8_t rx_pause, tx_pause;\n+\tenum rte_eth_fc_mode mode;\n+\tstruct roc_nix_cq *cq;\n+\tstruct roc_nix_sq *sq;\n+\tint rc;\n+\n+\tif (roc_nix_is_vf_or_sdp(nix)) {\n+\t\tplt_err(\"Prio flow ctrl config is not allowed on VF and SDP\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (roc_model_is_cn96_ax() && data->dev_started) {\n+\t\t/* On Ax, CQ should be in disabled state\n+\t\t * while setting flow control configuration.\n+\t\t */\n+\t\tplt_info(\"Stop the port=%d for setting flow control\",\n+\t\t\t data->port_id);\n+\t\treturn 0;\n+\t}\n+\n+\tif (dev->pfc_tc_sq_map[conf->tx_tc] != 0xFFFF &&\n+\t dev->pfc_tc_sq_map[conf->tx_tc] != conf->tx_qid) {\n+\t\tplt_err(\"Same TC can not be configured on multiple SQs\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tmode = conf->fc_cfg.mode;\n+\trx_pause = (mode == RTE_FC_FULL) || (mode == RTE_FC_RX_PAUSE);\n+\ttx_pause = (mode == RTE_FC_FULL) || (mode == RTE_FC_TX_PAUSE);\n+\n+\t/* Configure CQs */\n+\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\trxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[conf->rx_qid]) - 1;\n+\tcq = &dev->cqs[rxq->qid];\n+\tfc_cfg.type = ROC_NIX_FC_CQ_CFG;\n+\tfc_cfg.cq_cfg.tc = conf->rx_tc;\n+\tfc_cfg.cq_cfg.enable = !!tx_pause;\n+\tfc_cfg.cq_cfg.rq = cq->qid;\n+\tfc_cfg.cq_cfg.cq_drop = cq->drop_thresh;\n+\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\t/* Check if RX pause frame is enabled or not */\n+\tif (pfc->fc_cfg.rx_pause ^ rx_pause) {\n+\t\tif (conf->tx_qid >= eth_dev->data->nb_tx_queues)\n+\t\t\tgoto exit;\n+\n+\t\tif ((roc_nix_tm_tree_type_get(nix) != ROC_NIX_TM_PFC) &&\n+\t\t eth_dev->data->nb_tx_queues > 1) {\n+\t\t\t/*\n+\t\t\t * Disabled xmit will be enabled when\n+\t\t\t * new topology is available.\n+\t\t\t */\n+\t\t\trc = roc_nix_tm_hierarchy_disable(nix);\n+\t\t\tif (rc)\n+\t\t\t\tgoto exit;\n+\n+\t\t\trc = roc_nix_tm_prepare_pfc_tree(nix);\n+\t\t\tif (rc)\n+\t\t\t\tgoto exit;\n+\n+\t\t\trc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_PFC,\n+\t\t\t\t\t\t\t true);\n+\t\t\tif (rc)\n+\t\t\t\tgoto exit;\n+\t\t}\n+\t}\n+\n+\ttxq = ((struct cnxk_eth_txq_sp *)data->rx_queues[conf->tx_qid]) - 1;\n+\tsq = &dev->sqs[txq->qid];\n+\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\tfc_cfg.type = ROC_NIX_FC_TM_CFG;\n+\tfc_cfg.tm_cfg.sq = sq->qid;\n+\tfc_cfg.tm_cfg.tc = conf->tx_tc;\n+\tfc_cfg.tm_cfg.enable = !!rx_pause;\n+\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tdev->pfc_tc_sq_map[conf->tx_tc] = sq->qid;\n+\n+\t/* Configure MAC block */\n+\tif (tx_pause)\n+\t\tpfc->class_en |= BIT(conf->rx_tc);\n+\telse\n+\t\tpfc->class_en &= ~BIT(conf->rx_tc);\n+\n+\tif (pfc->class_en)\n+\t\tmode = RTE_ETH_FC_FULL;\n+\n+\tmemset(&pfc_cfg, 0, sizeof(struct roc_nix_pfc_cfg));\n+\tpfc_cfg.mode = mode_map[mode];\n+\tpfc_cfg.tc = conf->rx_tc;\n+\trc = roc_nix_pfc_mode_set(nix, &pfc_cfg);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tpfc->fc_cfg.rx_pause = rx_pause;\n+\tpfc->fc_cfg.tx_pause = tx_pause;\n+\tpfc->fc_cfg.mode = mode;\n+\n+exit:\n+\treturn rc;\n+}\n", "prefixes": [ "v1", "2/2" ] }