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GET /api/patches/105365/?format=api
{ "id": 105365, "url": "http://patches.dpdk.org/api/patches/105365/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211223130817.14077-1-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211223130817.14077-1-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211223130817.14077-1-getelson@nvidia.com", "date": "2021-12-23T13:08:17", "name": "net/mlx5: fix RSS expansion with explicit next protocol", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8ad5b8f40a9169f469291af295064014119b7579", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211223130817.14077-1-getelson@nvidia.com/mbox/", "series": [ { "id": 21015, "url": "http://patches.dpdk.org/api/series/21015/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21015", "date": "2021-12-23T13:08:17", "name": "net/mlx5: fix RSS expansion with explicit next protocol", "version": 1, "mbox": "http://patches.dpdk.org/series/21015/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105365/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/105365/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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b=LFNvuTbGet+m1RcG2UNAGtS1OpqjeXMWW3JK6Lv6xp2aTXNXP95UJCJe3t8NKL42fuUa45Vrh06zpNX/uhq9Ot3U2HS8tHNcs1CqF1e4oS2roVy+ODtgeMpGRF4slXLbqwbDsd2p61wfh12Z/aGL6dqsxXglX7A3X/+cA3Nf4zkPu3xhiBXCWtn3RY/OR7tqaRM9riceyED5LzM+T7br2FSkXru5GxeD4ABGShb99KsIEigC2l0kkr7uktBbbKiFYfDF5pHtOqd8j8Jl/5gUE9fa/vNUOGgyADlBnoP8PfBwi1cuUMmq0bTnKHjjGoyk0lsgp/iKzPxsVvgzXqJk1g==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 12.22.5.235)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 12.22.5.235 as permitted sender) receiver=protection.outlook.com;\n client-ip=12.22.5.235; helo=mail.nvidia.com;", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <rasland@nvidia.com>, <stable@dpdk.org>, \"Matan\n Azrad\" <matan@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Ferruh Yigit <ferruh.yigit@intel.com>, Dekel Peled <dekelp@nvidia.com>", "Subject": "[PATCH] net/mlx5: fix RSS expansion with explicit next protocol", "Date": "Thu, 23 Dec 2021 15:08:17 +0200", "Message-ID": "<20211223130817.14077-1-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "d3561497-ec66-4730-6d61-08d9c6155382", "X-MS-TrafficTypeDiagnostic": "CH2PR12MB3688:EE_", "X-Microsoft-Antispam-PRVS": "\n <CH2PR12MB3688B8F63FC4AAC9BE850B29A57E9@CH2PR12MB3688.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:655;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n /N0rUTRF589izNvVV2gNFNN19zV/btI7HmpfsSxKtsA6vSMjZGQ7MeUImTRvCOs+M8TBcGdCGZbxvfp9kzK5C1LtUhvhjRvWJGsgKqxldDKwlclnxzuFlugu7DKb6dDBFRPKxnvuOUV6CLmfzwsWokfQMK968f4Vob7omPR/d7L5ZWyz8TTWyKXwpVXQAzNXidk3yRIzoo//wCuXmf3q3nz+MmX6LT9evAroQUvxd8lBH7nyW0pYt/PsVYqDSqDDVtcT/oQiMlNoXejevTPXo7+a47Jn8JtsSFRzjTxonqjVh8a3AJ5pssrxnomkyyf2azNPEp2g7Fe9WjCTYpm87fx6LQ8JFnrkDIjHx4oMEWfwNT1Q0jCAgw7ZyHs4c8PXcx1AZsZbHa6VISayLnB9lB333rmDdJkKuHGmZ3BGlDQsFXERD/eDBvKsCO31G3i/2iOhSP+ZWqKX/0ktk+QOC9BBV5JjAwWFy2MWudDgYyJyBOaoN9g7ch0HiFgSwjYOx8O1HmwOxgW2cLm1janl+8wgZbQlcBeYnrASudl1xM2Q20VPOVH2tUkD9Ck0AZvWVDEEbrquz1wowb/ZWIhuQ9oa1bceJVcHZiTodb84bxc99d2UrCgJjZkE72qtFeqRbyQcJxarmuF4PyAlmUEM0PgCJauA+xTbA9qOdngkJDdH73sqoGgkkaCaTfDimwCbD9ImrN2ROkHCXY4frOd7oodV5mdrgB2yLj8GLzbE+2tTFkUWHeGKbcUIXP+0mo52vqEQEGZky9QHnBL6wU9EKER82Jun6VlrCvoDI4bwi78=", "X-Forefront-Antispam-Report": "CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(4636009)(46966006)(40470700002)(36840700001)(316002)(2906002)(54906003)(8936002)(81166007)(356005)(6666004)(8676002)(55016003)(36756003)(40460700001)(6286002)(83380400001)(36860700001)(107886003)(47076005)(70586007)(82310400004)(70206006)(336012)(1076003)(86362001)(7696005)(4326008)(26005)(16526019)(186003)(508600001)(2616005)(426003)(6916009)(5660300002)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Dec 2021 13:08:34.5899 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d3561497-ec66-4730-6d61-08d9c6155382", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT011.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB3688", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The PMD RSS expansion scheme by default compiles flow rules for all\nflow item types that may branch out from a stub supplied\nby application.\nFor example,\nETH can lead to VLAN, IPv4 or IPv6.\nIPv4 can lead to UDP, TCP, IPv4 or IPv6.\n\nIf application explicitly specified next protocol type, expansion must\nuse that option only and not create flows with other protocol types.\n\nThe PMD ignored explicit next protocol values in GRE and VXLAN-GPE.\n\nThe patch updates RSS expansion for GRE and VXLAN-GPE with explicit\nnext protocol settings.\n\nFixes: c7870bfe09dc (\"ethdev: move RSS expansion code to mlx5 driver\")\n\nCc: stable@dpdk.org\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 209 ++++++++++++++++++-----------------\n 1 file changed, 108 insertions(+), 101 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex f34e4b88aa..4e2ff16e30 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -164,128 +164,135 @@ mlx5_flow_is_rss_expandable_item(const struct rte_flow_item *item)\n \treturn false;\n }\n \n+/**\n+ * Network Service Header (NSH) and its next protocol values\n+ * are described in RFC-8393.\n+ */\n+static enum rte_flow_item_type\n+mlx5_nsh_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask)\n+{\n+\tenum rte_flow_item_type type;\n+\n+\tswitch (proto_mask & proto_spec) {\n+\tcase RTE_VXLAN_GPE_TYPE_IPV4:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_IPV4;\n+\t\tbreak;\n+\tcase RTE_VXLAN_GPE_TYPE_IPV6:\n+\t\ttype = RTE_VXLAN_GPE_TYPE_IPV6;\n+\t\tbreak;\n+\tcase RTE_VXLAN_GPE_TYPE_ETH:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_ETH;\n+\t\tbreak;\n+\tdefault:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_END;\n+\t}\n+\treturn type;\n+}\n+\n+static enum rte_flow_item_type\n+mlx5_inet_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask)\n+{\n+\tenum rte_flow_item_type type;\n+\n+\tswitch (proto_mask & proto_spec) {\n+\tcase IPPROTO_UDP:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_UDP;\n+\t\tbreak;\n+\tcase IPPROTO_TCP:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_TCP;\n+\t\tbreak;\n+\tcase IPPROTO_IP:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_IPV4;\n+\t\tbreak;\n+\tcase IPPROTO_IPV6:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_IPV6;\n+\t\tbreak;\n+\tdefault:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_END;\n+\t}\n+\treturn type;\n+}\n+\n+static enum rte_flow_item_type\n+mlx5_ethertype_to_item_type(rte_be16_t type_spec,\n+\t\t\t rte_be16_t type_mask, bool is_tunnel)\n+{\n+\tenum rte_flow_item_type type;\n+\n+\tswitch (rte_be_to_cpu_16(type_spec & type_mask)) {\n+\tcase RTE_ETHER_TYPE_TEB:\n+\t\ttype = is_tunnel ?\n+\t\t RTE_FLOW_ITEM_TYPE_ETH : RTE_FLOW_ITEM_TYPE_END;\n+\t\tbreak;\n+\tcase RTE_ETHER_TYPE_VLAN:\n+\t\ttype = !is_tunnel ?\n+\t\t RTE_FLOW_ITEM_TYPE_VLAN : RTE_FLOW_ITEM_TYPE_END;\n+\t\tbreak;\n+\tcase RTE_ETHER_TYPE_IPV4:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_IPV4;\n+\t\tbreak;\n+\tcase RTE_ETHER_TYPE_IPV6:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_IPV6;\n+\t\tbreak;\n+\tdefault:\n+\t\ttype = RTE_FLOW_ITEM_TYPE_END;\n+\t}\n+\treturn type;\n+}\n+\n static enum rte_flow_item_type\n mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item)\n {\n-\tenum rte_flow_item_type ret = RTE_FLOW_ITEM_TYPE_VOID;\n-\tuint16_t ether_type = 0;\n-\tuint16_t ether_type_m;\n-\tuint8_t ip_next_proto = 0;\n-\tuint8_t ip_next_proto_m;\n+#define MLX5_XSET_ITEM_MASK_SPEC(type, fld) \\\n+\tdo { \\\n+\t\tconst void *m = item->mask; \\\n+\t\tconst void *s = item->spec; \\\n+\t\tmask = m ? \\\n+\t\t\t((const struct rte_flow_item_##type *)m)->fld : \\\n+\t\t\trte_flow_item_##type##_mask.fld; \\\n+\t\tspec = ((const struct rte_flow_item_##type *)s)->fld; \\\n+\t} while (0)\n+\n+\tenum rte_flow_item_type ret;\n+\tuint16_t spec, mask;\n \n \tif (item == NULL || item->spec == NULL)\n-\t\treturn ret;\n+\t\treturn RTE_FLOW_ITEM_TYPE_VOID;\n \tswitch (item->type) {\n \tcase RTE_FLOW_ITEM_TYPE_ETH:\n-\t\tif (item->mask)\n-\t\t\tether_type_m = ((const struct rte_flow_item_eth *)\n-\t\t\t\t\t\t(item->mask))->type;\n-\t\telse\n-\t\t\tether_type_m = rte_flow_item_eth_mask.type;\n-\t\tif (ether_type_m != RTE_BE16(0xFFFF))\n-\t\t\tbreak;\n-\t\tether_type = ((const struct rte_flow_item_eth *)\n-\t\t\t\t(item->spec))->type;\n-\t\tif (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV4;\n-\t\telse if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV6;\n-\t\telse if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_VLAN;\n-\t\telse\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_END;\n+\t\tMLX5_XSET_ITEM_MASK_SPEC(eth, type);\n+\t\tret = mlx5_ethertype_to_item_type(spec, mask, false);\n \t\tbreak;\n \tcase RTE_FLOW_ITEM_TYPE_VLAN:\n-\t\tif (item->mask)\n-\t\t\tether_type_m = ((const struct rte_flow_item_vlan *)\n-\t\t\t\t\t\t(item->mask))->inner_type;\n-\t\telse\n-\t\t\tether_type_m = rte_flow_item_vlan_mask.inner_type;\n-\t\tif (ether_type_m != RTE_BE16(0xFFFF))\n-\t\t\tbreak;\n-\t\tether_type = ((const struct rte_flow_item_vlan *)\n-\t\t\t\t(item->spec))->inner_type;\n-\t\tif (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV4;\n-\t\telse if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV6;\n-\t\telse if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_VLAN;\n-\t\telse\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_END;\n+\t\tMLX5_XSET_ITEM_MASK_SPEC(vlan, inner_type);\n+\t\tret = mlx5_ethertype_to_item_type(spec, mask, false);\n \t\tbreak;\n \tcase RTE_FLOW_ITEM_TYPE_IPV4:\n-\t\tif (item->mask)\n-\t\t\tip_next_proto_m = ((const struct rte_flow_item_ipv4 *)\n-\t\t\t\t\t(item->mask))->hdr.next_proto_id;\n-\t\telse\n-\t\t\tip_next_proto_m =\n-\t\t\t\trte_flow_item_ipv4_mask.hdr.next_proto_id;\n-\t\tif (ip_next_proto_m != 0xFF)\n-\t\t\tbreak;\n-\t\tip_next_proto = ((const struct rte_flow_item_ipv4 *)\n-\t\t\t\t(item->spec))->hdr.next_proto_id;\n-\t\tif (ip_next_proto == IPPROTO_UDP)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_UDP;\n-\t\telse if (ip_next_proto == IPPROTO_TCP)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_TCP;\n-\t\telse if (ip_next_proto == IPPROTO_IP)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV4;\n-\t\telse if (ip_next_proto == IPPROTO_IPV6)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV6;\n-\t\telse\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_END;\n+\t\tMLX5_XSET_ITEM_MASK_SPEC(ipv4, hdr.next_proto_id);\n+\t\tret = mlx5_inet_proto_to_item_type(spec, mask);\n \t\tbreak;\n \tcase RTE_FLOW_ITEM_TYPE_IPV6:\n-\t\tif (item->mask)\n-\t\t\tip_next_proto_m = ((const struct rte_flow_item_ipv6 *)\n-\t\t\t\t\t\t(item->mask))->hdr.proto;\n-\t\telse\n-\t\t\tip_next_proto_m =\n-\t\t\t\trte_flow_item_ipv6_mask.hdr.proto;\n-\t\tif (ip_next_proto_m != 0xFF)\n-\t\t\tbreak;\n-\t\tip_next_proto = ((const struct rte_flow_item_ipv6 *)\n-\t\t\t\t(item->spec))->hdr.proto;\n-\t\tif (ip_next_proto == IPPROTO_UDP)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_UDP;\n-\t\telse if (ip_next_proto == IPPROTO_TCP)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_TCP;\n-\t\telse if (ip_next_proto == IPPROTO_IP)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV4;\n-\t\telse if (ip_next_proto == IPPROTO_IPV6)\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV6;\n-\t\telse\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_END;\n+\t\tMLX5_XSET_ITEM_MASK_SPEC(ipv6, hdr.proto);\n+\t\tret = mlx5_inet_proto_to_item_type(spec, mask);\n \t\tbreak;\n \tcase RTE_FLOW_ITEM_TYPE_GENEVE:\n-\t\tether_type_m = item->mask ?\n-\t\t\t ((const struct rte_flow_item_geneve *)\n-\t\t\t (item->mask))->protocol :\n-\t\t\t rte_flow_item_geneve_mask.protocol;\n-\t\tether_type = ((const struct rte_flow_item_geneve *)\n-\t\t\t (item->spec))->protocol;\n-\t\tether_type_m = rte_be_to_cpu_16(ether_type_m);\n-\t\tether_type = rte_be_to_cpu_16(ether_type);\n-\t\tswitch (ether_type_m & ether_type) {\n-\t\tcase RTE_ETHER_TYPE_TEB:\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_ETH;\n-\t\t\tbreak;\n-\t\tcase RTE_ETHER_TYPE_IPV4:\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV4;\n-\t\t\tbreak;\n-\t\tcase RTE_ETHER_TYPE_IPV6:\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_IPV6;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tret = RTE_FLOW_ITEM_TYPE_END;\n-\t\t}\n+\t\tMLX5_XSET_ITEM_MASK_SPEC(geneve, protocol);\n+\t\tret = mlx5_ethertype_to_item_type(spec, mask, true);\n+\t\tbreak;\n+\tcase RTE_FLOW_ITEM_TYPE_GRE:\n+\t\tMLX5_XSET_ITEM_MASK_SPEC(gre, protocol);\n+\t\tret = mlx5_ethertype_to_item_type(spec, mask, true);\n+\t\tbreak;\n+\tcase RTE_FLOW_ITEM_TYPE_VXLAN_GPE:\n+\t\tMLX5_XSET_ITEM_MASK_SPEC(vxlan_gpe, protocol);\n+\t\tret = mlx5_nsh_proto_to_item_type(spec, mask);\n \t\tbreak;\n \tdefault:\n \t\tret = RTE_FLOW_ITEM_TYPE_VOID;\n \t\tbreak;\n \t}\n \treturn ret;\n+#undef MLX5_XSET_ITEM_MASK_SPEC\n }\n \n static const int *\n", "prefixes": [] }