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{
    "id": 105246,
    "url": "http://patches.dpdk.org/api/patches/105246/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/cff4c053206f3ddbc729cb59286e05bbd4a28aec.1639636621.git.songyl@ramaxel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<cff4c053206f3ddbc729cb59286e05bbd4a28aec.1639636621.git.songyl@ramaxel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/cff4c053206f3ddbc729cb59286e05bbd4a28aec.1639636621.git.songyl@ramaxel.com",
    "date": "2021-12-18T02:51:31",
    "name": "[v1,04/25] net/spnic: introduce event queue",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "6eda397fe850c1ab88f70226211dd0c99774f7fa",
    "submitter": {
        "id": 2455,
        "url": "http://patches.dpdk.org/api/people/2455/?format=api",
        "name": "Yanling Song",
        "email": "songyl@ramaxel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/cff4c053206f3ddbc729cb59286e05bbd4a28aec.1639636621.git.songyl@ramaxel.com/mbox/",
    "series": [
        {
            "id": 20973,
            "url": "http://patches.dpdk.org/api/series/20973/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20973",
            "date": "2021-12-18T02:51:28",
            "name": "Net/SPNIC: support SPNIC into DPDK 22.03",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/20973/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/105246/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/105246/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 17AA5A04A4;\n\tSat, 18 Dec 2021 03:53:12 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7E6904114E;\n\tSat, 18 Dec 2021 03:52:27 +0100 (CET)",
            "from VLXDG1SPAM1.ramaxel.com (email.unionmem.com [221.4.138.186])\n by mails.dpdk.org (Postfix) with ESMTP id 39E1041147\n for <dev@dpdk.org>; Sat, 18 Dec 2021 03:52:25 +0100 (CET)",
            "from V12DG1MBS01.ramaxel.local (v12dg1mbs01.ramaxel.local\n [172.26.18.31])\n by VLXDG1SPAM1.ramaxel.com with ESMTPS id 1BI2pxFv010302\n (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL);\n Sat, 18 Dec 2021 10:51:59 +0800 (GMT-8)\n (envelope-from songyl@ramaxel.com)",
            "from localhost.localdomain (10.64.9.47) by V12DG1MBS01.ramaxel.local\n (172.26.18.31) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Sat, 18\n Dec 2021 10:51:58 +0800"
        ],
        "From": "Yanling Song <songyl@ramaxel.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<songyl@ramaxel.com>, <yanling.song@linux.dev>, <yanggan@ramaxel.com>,\n <ferruh.yigit@intel.com>",
        "Subject": "[PATCH v1 04/25] net/spnic: introduce event queue",
        "Date": "Sat, 18 Dec 2021 10:51:31 +0800",
        "Message-ID": "\n <cff4c053206f3ddbc729cb59286e05bbd4a28aec.1639636621.git.songyl@ramaxel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<cover.1639636621.git.songyl@ramaxel.com>",
        "References": "<cover.1639636621.git.songyl@ramaxel.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.64.9.47]",
        "X-ClientProxiedBy": "V12DG1MBS01.ramaxel.local (172.26.18.31) To\n V12DG1MBS01.ramaxel.local (172.26.18.31)",
        "X-DNSRBL": "",
        "X-MAIL": "VLXDG1SPAM1.ramaxel.com 1BI2pxFv010302",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "This patch introduce event queue to receive response message\nfrom hardware or destiation function when a source function\nsend mbox to it. This commit implements the related data\nstructure, initialization and interfaces handling the message.\n\nSigned-off-by: Yanling Song <songyl@ramaxel.com>\n---\n drivers/net/spnic/base/meson.build   |   1 +\n drivers/net/spnic/base/spnic_eqs.c   | 606 +++++++++++++++++++++++++++\n drivers/net/spnic/base/spnic_eqs.h   | 102 +++++\n drivers/net/spnic/base/spnic_hwdev.c |  44 +-\n drivers/net/spnic/base/spnic_hwdev.h |  22 +\n drivers/net/spnic/base/spnic_mbox.c  |  20 +-\n 6 files changed, 790 insertions(+), 5 deletions(-)\n create mode 100644 drivers/net/spnic/base/spnic_eqs.c\n create mode 100644 drivers/net/spnic/base/spnic_eqs.h",
    "diff": "diff --git a/drivers/net/spnic/base/meson.build b/drivers/net/spnic/base/meson.build\nindex de80eef7c4..ce7457f400 100644\n--- a/drivers/net/spnic/base/meson.build\n+++ b/drivers/net/spnic/base/meson.build\n@@ -2,6 +2,7 @@\n # Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n \n sources = [\n+\t'spnic_eqs.c',\n \t'spnic_hwdev.c',\n \t'spnic_hwif.c',\n \t'spnic_mbox.c'\ndiff --git a/drivers/net/spnic/base/spnic_eqs.c b/drivers/net/spnic/base/spnic_eqs.c\nnew file mode 100644\nindex 0000000000..7953976441\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_eqs.c\n@@ -0,0 +1,606 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#include <ethdev_driver.h>\n+#include <rte_memory.h>\n+#include <rte_memzone.h>\n+#include \"spnic_compat.h\"\n+#include \"spnic_hwdev.h\"\n+#include \"spnic_hwif.h\"\n+#include \"spnic_csr.h\"\n+#include \"spnic_eqs.h\"\n+#include \"spnic_mgmt.h\"\n+#include \"spnic_mbox.h\"\n+\n+#define AEQ_CTRL_0_INTR_IDX_SHIFT\t\t0\n+#define AEQ_CTRL_0_DMA_ATTR_SHIFT\t\t12\n+#define AEQ_CTRL_0_PCI_INTF_IDX_SHIFT\t\t20\n+#define AEQ_CTRL_0_INTR_MODE_SHIFT\t\t31\n+\n+#define AEQ_CTRL_0_INTR_IDX_MASK\t\t0x3FFU\n+#define AEQ_CTRL_0_DMA_ATTR_MASK\t\t0x3FU\n+#define AEQ_CTRL_0_PCI_INTF_IDX_MASK\t\t0x7U\n+#define AEQ_CTRL_0_INTR_MODE_MASK\t\t0x1U\n+\n+#define AEQ_CTRL_0_SET(val, member)\t\t\\\n+\t\t\t\t(((val) & AEQ_CTRL_0_##member##_MASK) << \\\n+\t\t\t\tAEQ_CTRL_0_##member##_SHIFT)\n+\n+#define AEQ_CTRL_0_CLEAR(val, member)\t\t\\\n+\t\t\t\t((val) & (~(AEQ_CTRL_0_##member##_MASK \\\n+\t\t\t\t\t<< AEQ_CTRL_0_##member##_SHIFT)))\n+\n+#define AEQ_CTRL_1_LEN_SHIFT\t\t\t0\n+#define AEQ_CTRL_1_ELEM_SIZE_SHIFT\t\t24\n+#define AEQ_CTRL_1_PAGE_SIZE_SHIFT\t\t28\n+\n+#define AEQ_CTRL_1_LEN_MASK\t\t\t0x1FFFFFU\n+#define AEQ_CTRL_1_ELEM_SIZE_MASK\t\t0x3U\n+#define AEQ_CTRL_1_PAGE_SIZE_MASK\t\t0xFU\n+\n+#define AEQ_CTRL_1_SET(val, member)\t\t\\\n+\t\t\t\t(((val) & AEQ_CTRL_1_##member##_MASK) << \\\n+\t\t\t\tAEQ_CTRL_1_##member##_SHIFT)\n+\n+#define AEQ_CTRL_1_CLEAR(val, member)\t\t\\\n+\t\t\t\t((val) & (~(AEQ_CTRL_1_##member##_MASK \\\n+\t\t\t\t\t<< AEQ_CTRL_1_##member##_SHIFT)))\n+\n+#define SPNIC_EQ_PROD_IDX_MASK\t\t\t0xFFFFF\n+#define SPNIC_TASK_PROCESS_EQE_LIMIT\t\t1024\n+#define SPNIC_EQ_UPDATE_CI_STEP                 64\n+\n+#define EQ_ELEM_DESC_TYPE_SHIFT\t\t\t0\n+#define EQ_ELEM_DESC_SRC_SHIFT\t\t\t7\n+#define EQ_ELEM_DESC_SIZE_SHIFT\t\t\t8\n+#define EQ_ELEM_DESC_WRAPPED_SHIFT\t\t31\n+\n+#define EQ_ELEM_DESC_TYPE_MASK\t\t\t0x7FU\n+#define EQ_ELEM_DESC_SRC_MASK\t\t\t0x1U\n+#define EQ_ELEM_DESC_SIZE_MASK\t\t\t0xFFU\n+#define EQ_ELEM_DESC_WRAPPED_MASK\t\t0x1U\n+\n+#define EQ_ELEM_DESC_GET(val, member)\t\t\\\n+\t\t\t\t(((val) >> EQ_ELEM_DESC_##member##_SHIFT) & \\\n+\t\t\t\tEQ_ELEM_DESC_##member##_MASK)\n+\n+#define EQ_CI_SIMPLE_INDIR_CI_SHIFT\t\t0\n+#define EQ_CI_SIMPLE_INDIR_ARMED_SHIFT\t\t21\n+#define EQ_CI_SIMPLE_INDIR_AEQ_IDX_SHIFT\t30\n+\n+#define EQ_CI_SIMPLE_INDIR_CI_MASK\t\t0x1FFFFFU\n+#define EQ_CI_SIMPLE_INDIR_ARMED_MASK\t\t0x1U\n+#define EQ_CI_SIMPLE_INDIR_AEQ_IDX_MASK\t\t0x3U\n+\n+#define EQ_CI_SIMPLE_INDIR_SET(val, member)\t\t\\\n+\t\t\t(((val) & EQ_CI_SIMPLE_INDIR_##member##_MASK) << \\\n+\t\t\tEQ_CI_SIMPLE_INDIR_##member##_SHIFT)\n+\n+#define EQ_CI_SIMPLE_INDIR_CLEAR(val, member)\t\t\\\n+\t\t\t\t((val) & (~(EQ_CI_SIMPLE_INDIR_##member##_MASK \\\n+\t\t\t\t<< EQ_CI_SIMPLE_INDIR_##member##_SHIFT)))\n+\n+#define EQ_WRAPPED(eq)\t\t((u32)(eq)->wrapped << EQ_VALID_SHIFT)\n+\n+#define EQ_CONS_IDX(eq)\t\t((eq)->cons_idx | \\\n+\t\t\t\t((u32)(eq)->wrapped << EQ_WRAPPED_SHIFT))\n+#define GET_EQ_NUM_PAGES(eq, size)\t\\\n+\t\t((u16)(RTE_ALIGN((u32)((eq)->eq_len * (eq)->elem_size), \\\n+\t\t(size)) / (size)))\n+\n+#define GET_EQ_NUM_ELEMS(eq, pg_size)\t((pg_size) / (u32)(eq)->elem_size)\n+\n+#define GET_EQ_ELEMENT(eq, idx)\t\t\\\n+\t\t(((u8 *)(eq)->virt_addr[(idx) / (eq)->num_elem_in_pg]) + \\\n+\t\t(u32)(((idx) & ((eq)->num_elem_in_pg - 1)) * (eq)->elem_size))\n+\n+#define GET_AEQ_ELEM(eq, idx)\t\t((struct spnic_aeq_elem *)\\\n+\t\t\t\t\tGET_EQ_ELEMENT((eq), (idx)))\n+\n+#define GET_CURR_AEQ_ELEM(eq)\t\tGET_AEQ_ELEM((eq), (eq)->cons_idx)\n+\n+#define PAGE_IN_4K(page_size)\t\t((page_size) >> 12)\n+#define EQ_SET_HW_PAGE_SIZE_VAL(eq)\t\\\n+\t\t((u32)ilog2(PAGE_IN_4K((eq)->page_size)))\n+\n+#define ELEMENT_SIZE_IN_32B(eq)\t\t(((eq)->elem_size) >> 5)\n+#define EQ_SET_HW_ELEM_SIZE_VAL(eq)\t((u32)ilog2(ELEMENT_SIZE_IN_32B(eq)))\n+\n+#define AEQ_DMA_ATTR_DEFAULT\t\t\t0\n+\n+#define EQ_MSIX_RESEND_TIMER_CLEAR\t\t1\n+\n+#define EQ_WRAPPED_SHIFT\t\t\t20\n+\n+#define\tEQ_VALID_SHIFT\t\t\t\t31\n+\n+#define aeq_to_aeqs(eq) \\\n+\t\tcontainer_of((eq) - (eq)->q_id, struct spnic_aeqs, aeq[0])\n+\n+#define AEQ_MSIX_ENTRY_IDX_0\t\t\t0\n+\n+/**\n+ * Write the cons idx to hw\n+ *\n+ * @param[in] eq\n+ *   The event queue to update the cons idx\n+ * @param[in] arm_state\n+ *   Indicate whether report interrupts when generate eq element\n+ */\n+static void set_eq_cons_idx(struct spnic_eq *eq, u32 arm_state)\n+{\n+\tu32 eq_wrap_ci, val;\n+\tu32 addr = SPNIC_CSR_AEQ_CI_SIMPLE_INDIR_ADDR;\n+\n+\teq_wrap_ci = EQ_CONS_IDX(eq);\n+\n+\t/* dpdk pmd driver only aeq0 use int_arm mode */\n+\tif (eq->q_id != 0)\n+\t\tval = EQ_CI_SIMPLE_INDIR_SET(SPNIC_EQ_NOT_ARMED, ARMED);\n+\telse\n+\t\tval = EQ_CI_SIMPLE_INDIR_SET(arm_state, ARMED);\n+\n+\tval = val | EQ_CI_SIMPLE_INDIR_SET(eq_wrap_ci, CI) |\n+\t      EQ_CI_SIMPLE_INDIR_SET(eq->q_id, AEQ_IDX);\n+\n+\tspnic_hwif_write_reg(eq->hwdev->hwif, addr, val);\n+}\n+\n+/**\n+ * Set aeq's ctrls registers\n+ *\n+ * @param[in] eq\n+ *   The event queue for setting\n+ */\n+static void set_aeq_ctrls(struct spnic_eq *eq)\n+{\n+\tstruct spnic_hwif *hwif = eq->hwdev->hwif;\n+\tstruct irq_info *eq_irq = &eq->eq_irq;\n+\tu32 addr, val, ctrl0, ctrl1, page_size_val, elem_size;\n+\tu32 pci_intf_idx = SPNIC_PCI_INTF_IDX(hwif);\n+\n+\t/* Set ctrl0 */\n+\taddr = SPNIC_CSR_AEQ_CTRL_0_ADDR;\n+\n+\tval = spnic_hwif_read_reg(hwif, addr);\n+\n+\tval = AEQ_CTRL_0_CLEAR(val, INTR_IDX) &\n+\t      AEQ_CTRL_0_CLEAR(val, DMA_ATTR) &\n+\t      AEQ_CTRL_0_CLEAR(val, PCI_INTF_IDX) &\n+\t      AEQ_CTRL_0_CLEAR(val, INTR_MODE);\n+\n+\tctrl0 = AEQ_CTRL_0_SET(eq_irq->msix_entry_idx, INTR_IDX) |\n+\t\tAEQ_CTRL_0_SET(AEQ_DMA_ATTR_DEFAULT, DMA_ATTR) |\n+\t\tAEQ_CTRL_0_SET(pci_intf_idx, PCI_INTF_IDX) |\n+\t\tAEQ_CTRL_0_SET(SPNIC_INTR_MODE_ARMED, INTR_MODE);\n+\n+\tval |= ctrl0;\n+\n+\tspnic_hwif_write_reg(hwif, addr, val);\n+\n+\t/* Set ctrl1 */\n+\taddr = SPNIC_CSR_AEQ_CTRL_1_ADDR;\n+\n+\tpage_size_val = EQ_SET_HW_PAGE_SIZE_VAL(eq);\n+\telem_size = EQ_SET_HW_ELEM_SIZE_VAL(eq);\n+\n+\tctrl1 = AEQ_CTRL_1_SET(eq->eq_len, LEN)\t|\n+\t\tAEQ_CTRL_1_SET(elem_size, ELEM_SIZE)\t|\n+\t\tAEQ_CTRL_1_SET(page_size_val, PAGE_SIZE);\n+\n+\tspnic_hwif_write_reg(hwif, addr, ctrl1);\n+}\n+\n+/**\n+ * Initialize all the elements in the aeq\n+ *\n+ * @param[in] eq\n+ *   The event queue\n+ * @param[in] init_val\n+ *   Value to init\n+ */\n+static void aeq_elements_init(struct spnic_eq *eq, u32 init_val)\n+{\n+\tstruct spnic_aeq_elem *aeqe = NULL;\n+\tu32 i;\n+\n+\tfor (i = 0; i < eq->eq_len; i++) {\n+\t\taeqe = GET_AEQ_ELEM(eq, i);\n+\t\taeqe->desc = cpu_to_be32(init_val);\n+\t}\n+\n+\trte_wmb(); /* Write the init values */\n+}\n+\n+/**\n+ * Allocate the pages for the queue\n+ *\n+ * @param[in] eq\n+ *   The event queue\n+ *\n+ * @retval zero : Success\n+ * @retval negative : Failure.\n+ */\n+static int alloc_eq_pages(struct spnic_eq *eq)\n+{\n+\tstruct spnic_hwif *hwif = eq->hwdev->hwif;\n+\tu64 dma_addr_size, virt_addr_size, eq_mz_size;\n+\tu32 reg, init_val;\n+\tu16 pg_num, i;\n+\tint err;\n+\n+\tdma_addr_size = eq->num_pages * sizeof(*eq->dma_addr);\n+\tvirt_addr_size = eq->num_pages * sizeof(*eq->virt_addr);\n+\teq_mz_size = eq->num_pages * sizeof(*eq->eq_mz);\n+\n+\teq->dma_addr = rte_zmalloc(\"eq_dma\", dma_addr_size,\n+\t\t\t\t   SPNIC_MEM_ALLOC_ALIGN_MIN);\n+\tif (!eq->dma_addr)\n+\t\treturn -ENOMEM;\n+\n+\teq->virt_addr = rte_zmalloc(\"eq_va\", virt_addr_size,\n+\t\t\t\t    SPNIC_MEM_ALLOC_ALIGN_MIN);\n+\tif (!eq->virt_addr) {\n+\t\terr = -ENOMEM;\n+\t\tgoto virt_addr_alloc_err;\n+\t}\n+\n+\teq->eq_mz = rte_zmalloc(\"eq_mz\", eq_mz_size, SPNIC_MEM_ALLOC_ALIGN_MIN);\n+\tif (!eq->eq_mz) {\n+\t\terr = -ENOMEM;\n+\t\tgoto eq_mz_alloc_err;\n+\t}\n+\n+\tfor (pg_num = 0; pg_num < eq->num_pages; pg_num++) {\n+\t\teq->eq_mz[pg_num] = rte_eth_dma_zone_reserve(eq->hwdev->eth_dev,\n+\t\t\t\t\t\"eq_mz\", eq->q_id, eq->page_size,\n+\t\t\t\t\teq->page_size, SOCKET_ID_ANY);\n+\t\tif (!eq->eq_mz[pg_num]) {\n+\t\t\terr = -ENOMEM;\n+\t\t\tgoto dma_alloc_err;\n+\t\t}\n+\n+\t\teq->dma_addr[pg_num] = eq->eq_mz[pg_num]->iova;\n+\t\teq->virt_addr[pg_num] = eq->eq_mz[pg_num]->addr;\n+\n+\t\treg = SPNIC_AEQ_HI_PHYS_ADDR_REG(pg_num);\n+\t\tspnic_hwif_write_reg(hwif, reg,\n+\t\t\t\t     upper_32_bits(eq->dma_addr[pg_num]));\n+\n+\t\treg = SPNIC_AEQ_LO_PHYS_ADDR_REG(pg_num);\n+\t\tspnic_hwif_write_reg(hwif, reg,\n+\t\t\t\t     lower_32_bits(eq->dma_addr[pg_num]));\n+\t}\n+\n+\teq->num_elem_in_pg = GET_EQ_NUM_ELEMS(eq, eq->page_size);\n+\tif (eq->num_elem_in_pg & (eq->num_elem_in_pg - 1)) {\n+\t\tPMD_DRV_LOG(ERR, \"Number element in eq page != power of 2\");\n+\t\terr = -EINVAL;\n+\t\tgoto dma_alloc_err;\n+\t}\n+\tinit_val = EQ_WRAPPED(eq);\n+\n+\taeq_elements_init(eq, init_val);\n+\n+\treturn 0;\n+\n+dma_alloc_err:\n+\tfor (i = 0; i < pg_num; i++)\n+\t\trte_memzone_free(eq->eq_mz[i]);\n+\n+eq_mz_alloc_err:\n+\trte_free(eq->virt_addr);\n+\n+virt_addr_alloc_err:\n+\trte_free(eq->dma_addr);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * Free the pages of the queue\n+ *\n+ * @param[in] eq\n+ *   The event queue\n+ */\n+static void free_eq_pages(struct spnic_eq *eq)\n+{\n+\tu16 pg_num;\n+\n+\tfor (pg_num = 0; pg_num < eq->num_pages; pg_num++)\n+\t\trte_memzone_free(eq->eq_mz[pg_num]);\n+\n+\trte_free(eq->eq_mz);\n+\trte_free(eq->virt_addr);\n+\trte_free(eq->dma_addr);\n+}\n+\n+static inline u32 get_page_size(struct spnic_eq *eq)\n+{\n+\tu32 total_size;\n+\tu16 count, n = 0;\n+\n+\ttotal_size = RTE_ALIGN((eq->eq_len * eq->elem_size),\n+\t\t\t       SPNIC_MIN_EQ_PAGE_SIZE);\n+\tif (total_size <= (SPNIC_EQ_MAX_PAGES * SPNIC_MIN_EQ_PAGE_SIZE))\n+\t\treturn SPNIC_MIN_EQ_PAGE_SIZE;\n+\n+\tcount = (u16)(RTE_ALIGN((total_size / SPNIC_EQ_MAX_PAGES),\n+\t\t      SPNIC_MIN_EQ_PAGE_SIZE) / SPNIC_MIN_EQ_PAGE_SIZE);\n+\tif (!(count & (count - 1)))\n+\t\treturn SPNIC_MIN_EQ_PAGE_SIZE * count;\n+\n+\twhile (count) {\n+\t\tcount >>= 1;\n+\t\tn++;\n+\t}\n+\n+\treturn ((u32)SPNIC_MIN_EQ_PAGE_SIZE) << n;\n+}\n+\n+/**\n+ * Initialize aeq\n+ *\n+ * @param[in] eq\n+ *   The event queue\n+ * @param[in] hwdev\n+ *   The pointer to the private hardware device object\n+ * @param[in] q_id\n+ *   Queue id number\n+ * @param[in] q_len\n+ *   The number of EQ elements\n+ *\n+ * @retval zero : Success\n+ * @retval non-zero : Failure.\n+ */\n+static int init_aeq(struct spnic_eq *eq, struct spnic_hwdev *hwdev,\n+\t\t    u16 q_id, u32 q_len)\n+{\n+\tint err = 0;\n+\n+\teq->hwdev = hwdev;\n+\teq->q_id = q_id;\n+\teq->eq_len = q_len;\n+\n+\t/* Indirect access should set q_id first */\n+\tspnic_hwif_write_reg(hwdev->hwif, SPNIC_AEQ_INDIR_IDX_ADDR, eq->q_id);\n+\trte_wmb(); /* write index before config */\n+\n+\t/* Clear eq_len to force eqe drop in hardware */\n+\tspnic_hwif_write_reg(eq->hwdev->hwif, SPNIC_CSR_AEQ_CTRL_1_ADDR, 0);\n+\trte_wmb();\n+\t/* Init aeq pi to 0 before allocating aeq pages */\n+\tspnic_hwif_write_reg(eq->hwdev->hwif, SPNIC_CSR_AEQ_PROD_IDX_ADDR, 0);\n+\n+\teq->cons_idx = 0;\n+\teq->wrapped = 0;\n+\n+\teq->elem_size = SPNIC_AEQE_SIZE;\n+\teq->page_size = get_page_size(eq);\n+\teq->orig_page_size = eq->page_size;\n+\teq->num_pages = GET_EQ_NUM_PAGES(eq, eq->page_size);\n+\tif (eq->num_pages > SPNIC_EQ_MAX_PAGES) {\n+\t\tPMD_DRV_LOG(ERR, \"Too many pages: %d for aeq\", eq->num_pages);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\terr = alloc_eq_pages(eq);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate pages for eq failed\");\n+\t\treturn err;\n+\t}\n+\n+\t/* Pmd driver uses AEQ_MSIX_ENTRY_IDX_0 */\n+\teq->eq_irq.msix_entry_idx = AEQ_MSIX_ENTRY_IDX_0;\n+\tset_aeq_ctrls(eq);\n+\n+\tset_eq_cons_idx(eq, SPNIC_EQ_ARMED);\n+\n+\tif (eq->q_id == 0)\n+\t\tspnic_set_msix_state(hwdev, 0, SPNIC_MSIX_ENABLE);\n+\n+\teq->poll_retry_nr = SPNIC_RETRY_NUM;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Remove aeq\n+ *\n+ * @param[in] eq\n+ *   The event queue\n+ */\n+static void remove_aeq(struct spnic_eq *eq)\n+{\n+\tstruct irq_info *entry = &eq->eq_irq;\n+\n+\tif (eq->q_id == 0)\n+\t\tspnic_set_msix_state(eq->hwdev, entry->msix_entry_idx,\n+\t\t\t\t     SPNIC_MSIX_DISABLE);\n+\n+\t/* Indirect access should set q_id first */\n+\tspnic_hwif_write_reg(eq->hwdev->hwif, SPNIC_AEQ_INDIR_IDX_ADDR,\n+\t\t\t     eq->q_id);\n+\n+\trte_wmb(); /* Write index before config */\n+\n+\t/* Clear eq_len to avoid hw access host memory */\n+\tspnic_hwif_write_reg(eq->hwdev->hwif, SPNIC_CSR_AEQ_CTRL_1_ADDR, 0);\n+\n+\t/* Update cons_idx to avoid invalid interrupt */\n+\teq->cons_idx = spnic_hwif_read_reg(eq->hwdev->hwif,\n+\t\t\t\t\t   SPNIC_CSR_AEQ_PROD_IDX_ADDR);\n+\tset_eq_cons_idx(eq, SPNIC_EQ_NOT_ARMED);\n+\n+\tfree_eq_pages(eq);\n+}\n+\n+/**\n+ * Init all aeqs\n+ *\n+ * @param[in] hwdev\n+ *   The pointer to the private hardware device object\n+ *\n+ * @retval zero : Success\n+ * @retval non-zero : Failure.\n+ */\n+int spnic_aeqs_init(struct spnic_hwdev *hwdev)\n+{\n+\tstruct spnic_aeqs *aeqs = NULL;\n+\tu16 num_aeqs;\n+\tint err;\n+\tu16 i, q_id;\n+\n+\tif (!hwdev)\n+\t\treturn -EINVAL;\n+\n+\tnum_aeqs = SPNIC_HWIF_NUM_AEQS(hwdev->hwif);\n+\tif (num_aeqs > SPNIC_MAX_AEQS) {\n+\t\tPMD_DRV_LOG(INFO, \"Adjust aeq num to %d\", SPNIC_MAX_AEQS);\n+\t\tnum_aeqs = SPNIC_MAX_AEQS;\n+\t} else if (num_aeqs < SPNIC_MIN_AEQS) {\n+\t\tPMD_DRV_LOG(ERR, \"PMD needs %d AEQs, Chip has %d\",\n+\t\t\t    SPNIC_MIN_AEQS, num_aeqs);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\taeqs = rte_zmalloc(\"spnic_aeqs\", sizeof(*aeqs),\n+\t\t\t   SPNIC_MEM_ALLOC_ALIGN_MIN);\n+\tif (!aeqs)\n+\t\treturn -ENOMEM;\n+\n+\thwdev->aeqs = aeqs;\n+\taeqs->hwdev = hwdev;\n+\taeqs->num_aeqs = num_aeqs;\n+\n+\tfor (q_id = 0; q_id < num_aeqs; q_id++) {\n+\t\terr = init_aeq(&aeqs->aeq[q_id], hwdev, q_id,\n+\t\t\t       SPNIC_DEFAULT_AEQ_LEN);\n+\t\tif (err) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Init aeq %d failed\", q_id);\n+\t\t\tgoto init_aeq_err;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+\n+init_aeq_err:\n+\tfor (i = 0; i < q_id; i++)\n+\t\tremove_aeq(&aeqs->aeq[i]);\n+\n+\trte_free(aeqs);\n+\treturn err;\n+}\n+\n+/**\n+ * Free all aeqs\n+ *\n+ * @param[in] hwdev\n+ *   The pointer to the private hardware device object\n+ */\n+void spnic_aeqs_free(struct spnic_hwdev *hwdev)\n+{\n+\tstruct spnic_aeqs *aeqs = hwdev->aeqs;\n+\tu16 q_id;\n+\n+\tfor (q_id = 0; q_id < aeqs->num_aeqs; q_id++)\n+\t\tremove_aeq(&aeqs->aeq[q_id]);\n+\n+\trte_free(aeqs);\n+}\n+\n+static int aeq_elem_handler(struct spnic_eq *eq, u32 aeqe_desc,\n+\t\t\t    struct spnic_aeq_elem *aeqe_pos, void *param)\n+{\n+\tenum spnic_aeq_type event;\n+\tu8 data[SPNIC_AEQE_DATA_SIZE];\n+\tu8 size;\n+\n+\tevent = EQ_ELEM_DESC_GET(aeqe_desc, TYPE);\n+\n+\tmemcpy(data, aeqe_pos->aeqe_data, SPNIC_AEQE_DATA_SIZE);\n+\tspnic_be32_to_cpu(data, SPNIC_AEQE_DATA_SIZE);\n+\tsize = EQ_ELEM_DESC_GET(aeqe_desc, SIZE);\n+\n+\tif (event == SPNIC_MBX_FROM_FUNC) {\n+\t\treturn spnic_mbox_func_aeqe_handler(eq->hwdev, data, size,\n+\t\t\t\t\t\t    param);\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"AEQ hw event not support %d\", event);\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+/**\n+ * Poll one or continue aeqe, and call dedicated process\n+ *\n+ * @param[in] eq\n+ *   The event queue\n+ * @param[in] timeout\n+ *   0   - Poll all aeqe in eq, used in interrupt mode,\n+ *   > 0 - Poll aeq until get aeqe with 'last' field set to 1,\n+ *         used in polling mode.\n+ * @param[in] param\n+ *   Customized parameter\n+ *\n+ * @retval zero : Success\n+ * @retval -EIO : Poll timeout\n+ * @retval -ENODEV : Swe not support\n+ */\n+int spnic_aeq_poll_msg(struct spnic_eq *eq, u32 timeout, void *param)\n+{\n+\tstruct spnic_aeq_elem *aeqe_pos = NULL;\n+\tu32 aeqe_desc = 0;\n+\tu32 eqe_cnt = 0;\n+\tint err = -EFAULT;\n+\tint done = SPNIC_MSG_HANDLER_RES;\n+\tunsigned long end;\n+\tu16 i;\n+\n+\tfor (i = 0; ((timeout == 0) && (i < eq->eq_len)) ||\n+\t     ((timeout > 0) && (done != 0) && (i < eq->eq_len)); i++) {\n+\t\terr = -EIO;\n+\t\tend = jiffies + msecs_to_jiffies(timeout);\n+\t\tdo {\n+\t\t\taeqe_pos = GET_CURR_AEQ_ELEM(eq);\n+\t\t\trte_rmb();\n+\n+\t\t\t/* Data in HW is in Big endian Format */\n+\t\t\taeqe_desc = be32_to_cpu(aeqe_pos->desc);\n+\n+\t\t\t/*\n+\t\t\t * HW updates wrapped bit,\n+\t\t\t * when it adds eq element event\n+\t\t\t */\n+\t\t\tif (EQ_ELEM_DESC_GET(aeqe_desc, WRAPPED)\n+\t\t\t\t!= eq->wrapped) {\n+\t\t\t\terr = 0;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (timeout != 0)\n+\t\t\t\tusleep(1000);\n+\t\t} while (time_before(jiffies, end));\n+\n+\t\tif (err != 0) /* Poll time out */\n+\t\t\tbreak;\n+\n+\t\tdone = aeq_elem_handler(eq, aeqe_desc, aeqe_pos, param);\n+\n+\t\teq->cons_idx++;\n+\t\tif (eq->cons_idx == eq->eq_len) {\n+\t\t\teq->cons_idx = 0;\n+\t\t\teq->wrapped = !eq->wrapped;\n+\t\t}\n+\n+\t\tif (++eqe_cnt >= SPNIC_EQ_UPDATE_CI_STEP) {\n+\t\t\teqe_cnt = 0;\n+\t\t\tset_eq_cons_idx(eq, SPNIC_EQ_NOT_ARMED);\n+\t\t}\n+\t}\n+\n+\tset_eq_cons_idx(eq, SPNIC_EQ_ARMED);\n+\n+\treturn err;\n+}\ndiff --git a/drivers/net/spnic/base/spnic_eqs.h b/drivers/net/spnic/base/spnic_eqs.h\nnew file mode 100644\nindex 0000000000..baefae58fb\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_eqs.h\n@@ -0,0 +1,102 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#ifndef _SPNIC_EQS_H_\n+#define _SPNIC_EQS_H_\n+\n+#define SPNIC_MAX_AEQS\t\t\t4\n+#define SPNIC_MIN_AEQS\t\t\t2\n+#define SPNIC_EQ_MAX_PAGES\t\t4\n+\n+#define SPNIC_AEQE_SIZE                 64\n+\n+#define SPNIC_AEQE_DESC_SIZE\t\t4\n+#define SPNIC_AEQE_DATA_SIZE\t\t\\\n+\t\t\t(SPNIC_AEQE_SIZE - SPNIC_AEQE_DESC_SIZE)\n+\n+/* Linux is 1K, dpdk is 64 */\n+#define SPNIC_DEFAULT_AEQ_LEN\t\t64\n+\n+#define SPNIC_MIN_EQ_PAGE_SIZE\t\t0x1000   /* Min eq page size 4K Bytes */\n+#define SPNIC_MAX_EQ_PAGE_SIZE\t\t0x400000 /* Max eq page size 4M Bytes */\n+\n+#define SPNIC_MIN_AEQ_LEN\t\t64\n+#define SPNIC_MAX_AEQ_LEN\t\t\\\n+\t((SPNIC_MAX_EQ_PAGE_SIZE / SPNIC_AEQE_SIZE) * SPNIC_EQ_MAX_PAGES)\n+\n+#define EQ_IRQ_NAME_LEN\t\t\t64\n+\n+enum spnic_eq_intr_mode {\n+\tSPNIC_INTR_MODE_ARMED,\n+\tSPNIC_INTR_MODE_ALWAYS\n+};\n+\n+enum spnic_eq_ci_arm_state {\n+\tSPNIC_EQ_NOT_ARMED,\n+\tSPNIC_EQ_ARMED\n+};\n+\n+struct irq_info {\n+\tu16 msix_entry_idx; /* IRQ corresponding index number */\n+\tu32 irq_id;         /* The IRQ number from OS */\n+};\n+\n+#define SPNIC_RETRY_NUM\t10\n+\n+enum spnic_aeq_type {\n+\tSPNIC_HW_INTER_INT = 0,\n+\tSPNIC_MBX_FROM_FUNC = 1,\n+\tSPNIC_MSG_FROM_MGMT_CPU = 2,\n+\tSPNIC_API_RSP = 3,\n+\tSPNIC_API_CHAIN_STS = 4,\n+\tSPNIC_MBX_SEND_RSLT = 5,\n+\tSPNIC_MAX_AEQ_EVENTS\n+};\n+\n+struct spnic_eq {\n+\tstruct spnic_hwdev *hwdev;\n+\tu16 q_id;\n+\tu32 page_size;\n+\tu32 orig_page_size;\n+\tu32 eq_len;\n+\n+\tu32 cons_idx;\n+\tu16 wrapped;\n+\n+\tu16 elem_size;\n+\tu16 num_pages;\n+\tu32 num_elem_in_pg;\n+\n+\tstruct irq_info eq_irq;\n+\n+\tconst struct rte_memzone **eq_mz;\n+\trte_iova_t *dma_addr;\n+\tu8 **virt_addr;\n+\n+\tu16 poll_retry_nr;\n+};\n+\n+struct spnic_aeq_elem {\n+\tu8  aeqe_data[SPNIC_AEQE_DATA_SIZE];\n+\tu32 desc;\n+};\n+\n+struct spnic_aeqs {\n+\tstruct spnic_hwdev *hwdev;\n+\n+\tstruct spnic_eq aeq[SPNIC_MAX_AEQS];\n+\tu16 num_aeqs;\n+};\n+\n+int spnic_aeqs_init(struct spnic_hwdev *hwdev);\n+\n+void spnic_aeqs_free(struct spnic_hwdev *hwdev);\n+\n+void spnic_dump_aeq_info(struct spnic_hwdev *hwdev);\n+\n+int spnic_aeq_poll_msg(struct spnic_eq *eq, u32 timeout, void *param);\n+\n+void spnic_dev_handle_aeq_event(struct spnic_hwdev *hwdev, void *param);\n+\n+#endif /* _SPNIC_EQS_H_ */\ndiff --git a/drivers/net/spnic/base/spnic_hwdev.c b/drivers/net/spnic/base/spnic_hwdev.c\nindex bcecbaa895..e45058423c 100644\n--- a/drivers/net/spnic/base/spnic_hwdev.c\n+++ b/drivers/net/spnic/base/spnic_hwdev.c\n@@ -5,10 +5,45 @@\n #include \"spnic_compat.h\"\n #include \"spnic_csr.h\"\n #include \"spnic_hwif.h\"\n+#include \"spnic_eqs.h\"\n #include \"spnic_mgmt.h\"\n #include \"spnic_mbox.h\"\n #include \"spnic_hwdev.h\"\n \n+typedef void (*mgmt_event_cb)(void *handle, void *buf_in, u16 in_size,\n+\t\t\t      void *buf_out, u16 *out_size);\n+\n+struct mgmt_event_handle {\n+\tu16 cmd;\n+\tmgmt_event_cb proc;\n+};\n+\n+const struct mgmt_event_handle mgmt_event_proc[] = {\n+};\n+\n+void pf_handle_mgmt_comm_event(void *handle, __rte_unused void *pri_handle,\n+\t\t\t       u16 cmd, void *buf_in, u16 in_size,\n+\t\t\t       void *buf_out, u16 *out_size)\n+{\n+\tstruct spnic_hwdev *hwdev = handle;\n+\tu32 i, event_num = RTE_DIM(mgmt_event_proc);\n+\n+\tif (!hwdev)\n+\t\treturn;\n+\n+\tfor (i = 0; i < event_num; i++) {\n+\t\tif (cmd == mgmt_event_proc[i].cmd) {\n+\t\t\tif (mgmt_event_proc[i].proc)\n+\t\t\t\tmgmt_event_proc[i].proc(handle, buf_in, in_size,\n+\t\t\t\t\t\t\tbuf_out, out_size);\n+\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tPMD_DRV_LOG(WARNING, \"Unsupported mgmt cpu event %d to process\", cmd);\n+}\n+\n int vf_handle_pf_comm_mbox(void *handle, __rte_unused void *pri_handle,\n \t\t\t   __rte_unused u16 cmd, __rte_unused void *buf_in,\n \t\t\t   __rte_unused u16 in_size, __rte_unused void *buf_out,\n@@ -28,6 +63,12 @@ static int init_mgmt_channel(struct spnic_hwdev *hwdev)\n {\n \tint err;\n \n+\terr = spnic_aeqs_init(hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Init async event queues failed\");\n+\t\treturn err;\n+\t}\n+\n \terr = spnic_func_to_func_init(hwdev);\n \tif (err) {\n \t\tPMD_DRV_LOG(ERR, \"Init mailbox channel failed\");\n@@ -37,6 +78,7 @@ static int init_mgmt_channel(struct spnic_hwdev *hwdev)\n \treturn 0;\n \n func_to_func_init_err:\n+\tspnic_aeqs_free(hwdev);\n \n \treturn err;\n }\n@@ -44,9 +86,9 @@ static int init_mgmt_channel(struct spnic_hwdev *hwdev)\n static void free_mgmt_channel(struct spnic_hwdev *hwdev)\n {\n \tspnic_func_to_func_free(hwdev);\n+\tspnic_aeqs_free(hwdev);\n }\n \n-\n static int spnic_init_comm_ch(struct spnic_hwdev *hwdev)\n {\n \tint err;\ndiff --git a/drivers/net/spnic/base/spnic_hwdev.h b/drivers/net/spnic/base/spnic_hwdev.h\nindex b3a8b32287..a0691eed2e 100644\n--- a/drivers/net/spnic/base/spnic_hwdev.h\n+++ b/drivers/net/spnic/base/spnic_hwdev.h\n@@ -8,6 +8,21 @@\n #include <rte_ether.h>\n \n #define SPNIC_CHIP_FAULT_SIZE\t\t(110 * 1024)\n+struct cfg_mgmt_info;\n+struct spnic_hwif;\n+struct spnic_aeqs;\n+struct spnic_mbox;\n+struct spnic_msg_pf_to_mgmt;\n+\n+struct ffm_intr_info {\n+\tu8 node_id;\n+\t/* Error level of the interrupt source */\n+\tu8 err_level;\n+\t/* Classification by interrupt source properties */\n+\tu16 err_type;\n+\tu32 err_csr_addr;\n+\tu32 err_csr_value;\n+};\n \n struct spnic_hwdev {\n \tvoid *dev_handle; /* Pointer to spnic_nic_dev */\n@@ -18,6 +33,9 @@ struct spnic_hwdev {\n \n \tstruct spnic_hwif *hwif;\n \tstruct spnic_mbox *func_to_func;\n+\tstruct cfg_mgmt_info *cfg_mgmt;\n+\tstruct spnic_aeqs *aeqs;\n+\tstruct spnic_msg_pf_to_mgmt *pf_to_mgmt;\n \tu8 *chip_fault_stats;\n \n \tu16 max_vfs;\n@@ -29,6 +47,10 @@ int vf_handle_pf_comm_mbox(void *handle, __rte_unused void *pri_handle,\n \t\t\t   __rte_unused u16 in_size, __rte_unused void *buf_out,\n \t\t\t   __rte_unused u16 *out_size);\n \n+void pf_handle_mgmt_comm_event(void *handle, __rte_unused void *pri_handle,\n+\t\t\t       u16 cmd, void *buf_in, u16 in_size,\n+\t\t\t       void *buf_out, u16 *out_size);\n+\n int spnic_init_hwdev(struct spnic_hwdev *hwdev);\n \n void spnic_free_hwdev(struct spnic_hwdev *hwdev);\ndiff --git a/drivers/net/spnic/base/spnic_mbox.c b/drivers/net/spnic/base/spnic_mbox.c\nindex d019612cef..1677bd7404 100644\n--- a/drivers/net/spnic/base/spnic_mbox.c\n+++ b/drivers/net/spnic/base/spnic_mbox.c\n@@ -2,13 +2,13 @@\n  * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n  */\n \n-#include <rte_atomic.h>\n #include <ethdev_driver.h>\n #include \"spnic_compat.h\"\n #include \"spnic_hwdev.h\"\n #include \"spnic_csr.h\"\n-#include \"spnic_hwif.h\"\n #include \"spnic_mgmt.h\"\n+#include \"spnic_hwif.h\"\n+#include \"spnic_eqs.h\"\n #include \"spnic_mbox.h\"\n \n #define SPNIC_MBOX_INT_DST_FUNC_SHIFT\t\t\t\t0\n@@ -713,7 +713,9 @@ static int spnic_mbox_to_func(struct spnic_mbox *func_to_func,\n \t/* Use mbox_resp to hole data which responsed from other function */\n \tstruct spnic_recv_mbox *mbox_for_resp = NULL;\n \tstruct mbox_msg_info msg_info = {0};\n+\tstruct spnic_eq *aeq = NULL;\n \tu16 mbox_rsp_idx;\n+\tu32 time;\n \tint err;\n \n \tmbox_rsp_idx = (dst_func == SPNIC_MGMT_SRC_ID) ?\n@@ -748,9 +750,19 @@ static int spnic_mbox_to_func(struct spnic_mbox *func_to_func,\n \t\tgoto send_err;\n \t}\n \n+\ttime = msecs_to_jiffies(timeout ? timeout : SPNIC_MBOX_COMP_TIME);\n+\taeq = &func_to_func->hwdev->aeqs->aeq[SPNIC_MBOX_RSP_MSG_AEQ];\n+\terr = spnic_aeq_poll_msg(aeq, time, NULL);\n+\tif (err) {\n+\t\tset_mbox_to_func_event(func_to_func, EVENT_TIMEOUT);\n+\t\tPMD_DRV_LOG(ERR, \"Send mailbox message time out\");\n+\t\terr = -ETIMEDOUT;\n+\t\tgoto send_err;\n+\t}\n+\n \tif (mod != mbox_for_resp->mod || cmd != mbox_for_resp->cmd) {\n-\t\tPMD_DRV_LOG(ERR, \"Invalid response mbox message, mod: 0x%x, cmd: 0x%x, expect mod: 0x%x, cmd: 0x%x, timeout0x%x\\n\",\n-\t\t\t    mbox_for_resp->mod, mbox_for_resp->cmd, mod, cmd, timeout);\n+\t\tPMD_DRV_LOG(ERR, \"Invalid response mbox message, mod: 0x%x, cmd: 0x%x, expect mod: 0x%x, cmd: 0x%x\\n\",\n+\t\t\t    mbox_for_resp->mod, mbox_for_resp->cmd, mod, cmd);\n \t\terr = -EFAULT;\n \t\tgoto send_err;\n \t}\n",
    "prefixes": [
        "v1",
        "04/25"
    ]
}