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GET /api/patches/105244/?format=api
{ "id": 105244, "url": "http://patches.dpdk.org/api/patches/105244/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/65775aa66dd8704b6dd6c408053a677b163e3aab.1639636621.git.songyl@ramaxel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<65775aa66dd8704b6dd6c408053a677b163e3aab.1639636621.git.songyl@ramaxel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/65775aa66dd8704b6dd6c408053a677b163e3aab.1639636621.git.songyl@ramaxel.com", "date": "2021-12-18T02:51:33", "name": "[v1,06/25] net/spnic: add cmdq and work queue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "27fb2e6bc3897a2ced7039aff09e659089961025", "submitter": { "id": 2455, "url": "http://patches.dpdk.org/api/people/2455/?format=api", "name": "Yanling Song", "email": "songyl@ramaxel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/65775aa66dd8704b6dd6c408053a677b163e3aab.1639636621.git.songyl@ramaxel.com/mbox/", "series": [ { "id": 20973, "url": "http://patches.dpdk.org/api/series/20973/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20973", "date": "2021-12-18T02:51:28", "name": "Net/SPNIC: support SPNIC into DPDK 22.03", "version": 1, "mbox": "http://patches.dpdk.org/series/20973/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105244/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105244/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6CFD2A04A4;\n\tSat, 18 Dec 2021 03:52:50 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8C0324115E;\n\tSat, 18 Dec 2021 03:52:23 +0100 (CET)", "from VLXDG1SPAM1.ramaxel.com (email.ramaxel.com [221.4.138.186])\n by mails.dpdk.org (Postfix) with ESMTP id F2FBF41155\n for <dev@dpdk.org>; Sat, 18 Dec 2021 03:52:20 +0100 (CET)", "from V12DG1MBS01.ramaxel.local (v12dg1mbs01.ramaxel.local\n [172.26.18.31])\n by VLXDG1SPAM1.ramaxel.com with ESMTPS id 1BI2pxKQ010303\n (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL);\n Sat, 18 Dec 2021 10:51:59 +0800 (GMT-8)\n (envelope-from songyl@ramaxel.com)", "from localhost.localdomain (10.64.9.47) by V12DG1MBS01.ramaxel.local\n (172.26.18.31) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Sat, 18\n Dec 2021 10:51:59 +0800" ], "From": "Yanling Song <songyl@ramaxel.com>", "To": "<dev@dpdk.org>", "CC": "<songyl@ramaxel.com>, <yanling.song@linux.dev>, <yanggan@ramaxel.com>,\n <ferruh.yigit@intel.com>", "Subject": "[PATCH v1 06/25] net/spnic: add cmdq and work queue", "Date": "Sat, 18 Dec 2021 10:51:33 +0800", "Message-ID": "\n <65775aa66dd8704b6dd6c408053a677b163e3aab.1639636621.git.songyl@ramaxel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<cover.1639636621.git.songyl@ramaxel.com>", "References": "<cover.1639636621.git.songyl@ramaxel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.64.9.47]", "X-ClientProxiedBy": "V12DG1MBS01.ramaxel.local (172.26.18.31) To\n V12DG1MBS01.ramaxel.local (172.26.18.31)", "X-DNSRBL": "", "X-MAIL": "VLXDG1SPAM1.ramaxel.com 1BI2pxKQ010303", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit introduce cmdq and work queue which can be used to\nsend bulk message data(up to 2KB) to hardware. cmdq provides a\nmechanism to encapsulate the message to be sent and handle the\nresponse data or status. work queue is used to manager the wqe\nin which includes message data buffer description, ctrl info,\nheader info and response message data buffer. This patch\nimplements the initialization and data structure.\n\nSigned-off-by: Yanling Song <songyl@ramaxel.com>\n---\n drivers/net/spnic/base/meson.build | 4 +-\n drivers/net/spnic/base/spnic_cmdq.c | 202 ++++++++++++++++++++++\n drivers/net/spnic/base/spnic_cmdq.h | 228 +++++++++++++++++++++++++\n drivers/net/spnic/base/spnic_hw_comm.c | 222 ++++++++++++++++++++++++\n drivers/net/spnic/base/spnic_hw_comm.h | 176 +++++++++++++++++++\n drivers/net/spnic/base/spnic_hwdev.c | 215 +++++++++++++++++++++++\n drivers/net/spnic/base/spnic_hwdev.h | 8 +-\n drivers/net/spnic/base/spnic_wq.h | 57 +++++++\n 8 files changed, 1109 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/spnic/base/spnic_cmdq.c\n create mode 100644 drivers/net/spnic/base/spnic_cmdq.h\n create mode 100644 drivers/net/spnic/base/spnic_hw_comm.c\n create mode 100644 drivers/net/spnic/base/spnic_hw_comm.h\n create mode 100644 drivers/net/spnic/base/spnic_wq.h", "diff": "diff --git a/drivers/net/spnic/base/meson.build b/drivers/net/spnic/base/meson.build\nindex 3f6a060b37..5e4efac7be 100644\n--- a/drivers/net/spnic/base/meson.build\n+++ b/drivers/net/spnic/base/meson.build\n@@ -7,7 +7,9 @@ sources = [\n \t'spnic_hwif.c',\n \t'spnic_mbox.c',\n \t'spnic_mgmt.c',\n-\t'spnic_nic_event.c'\n+\t'spnic_nic_event.c',\n+\t'spnic_cmdq.c',\n+\t'spnic_hw_comm.c',\n ]\n \n extra_flags = []\ndiff --git a/drivers/net/spnic/base/spnic_cmdq.c b/drivers/net/spnic/base/spnic_cmdq.c\nnew file mode 100644\nindex 0000000000..ccfcf739a0\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_cmdq.c\n@@ -0,0 +1,202 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#include <rte_mbuf.h>\n+\n+#include \"spnic_compat.h\"\n+#include \"spnic_hwdev.h\"\n+#include \"spnic_hwif.h\"\n+#include \"spnic_wq.h\"\n+#include \"spnic_cmd.h\"\n+#include \"spnic_mgmt.h\"\n+#include \"spnic_cmdq.h\"\n+\n+#define CMDQ_CTXT_CURR_WQE_PAGE_PFN_SHIFT\t\t0\n+#define CMDQ_CTXT_EQ_ID_SHIFT\t\t\t\t53\n+#define CMDQ_CTXT_CEQ_ARM_SHIFT\t\t\t\t61\n+#define CMDQ_CTXT_CEQ_EN_SHIFT\t\t\t\t62\n+#define CMDQ_CTXT_HW_BUSY_BIT_SHIFT\t\t\t63\n+\n+#define CMDQ_CTXT_CURR_WQE_PAGE_PFN_MASK\t\t0xFFFFFFFFFFFFF\n+#define CMDQ_CTXT_EQ_ID_MASK\t\t\t\t0xFF\n+#define CMDQ_CTXT_CEQ_ARM_MASK\t\t\t\t0x1\n+#define CMDQ_CTXT_CEQ_EN_MASK\t\t\t\t0x1\n+#define CMDQ_CTXT_HW_BUSY_BIT_MASK\t\t\t0x1\n+\n+#define CMDQ_CTXT_PAGE_INFO_SET(val, member)\t\t\\\n+\t(((u64)(val) & CMDQ_CTXT_##member##_MASK) << CMDQ_CTXT_##member##_SHIFT)\n+\n+#define CMDQ_CTXT_WQ_BLOCK_PFN_SHIFT\t\t\t0\n+#define CMDQ_CTXT_CI_SHIFT\t\t\t\t52\n+\n+#define CMDQ_CTXT_WQ_BLOCK_PFN_MASK\t\t\t0xFFFFFFFFFFFFF\n+#define CMDQ_CTXT_CI_MASK\t\t\t\t0xFFF\n+\n+#define CMDQ_CTXT_BLOCK_INFO_SET(val, member)\t\t\\\n+\t(((u64)(val) & CMDQ_CTXT_##member##_MASK) << CMDQ_CTXT_##member##_SHIFT)\n+\n+#define WAIT_CMDQ_ENABLE_TIMEOUT\t300\n+\n+static int init_cmdq(struct spnic_cmdq *cmdq, struct spnic_hwdev *hwdev,\n+\t\t struct spnic_wq *wq, enum spnic_cmdq_type q_type)\n+{\n+\tvoid *db_base = NULL;\n+\tint err = 0;\n+\tsize_t errcode_size;\n+\tsize_t cmd_infos_size;\n+\n+\tcmdq->wq = wq;\n+\tcmdq->cmdq_type = q_type;\n+\tcmdq->wrapped = 1;\n+\n+\trte_spinlock_init(&cmdq->cmdq_lock);\n+\n+\terrcode_size = wq->q_depth * sizeof(*cmdq->errcode);\n+\tcmdq->errcode = rte_zmalloc(NULL, errcode_size, 0);\n+\tif (!cmdq->errcode) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate errcode for cmdq failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tcmd_infos_size = wq->q_depth * sizeof(*cmdq->cmd_infos);\n+\tcmdq->cmd_infos = rte_zmalloc(NULL, cmd_infos_size, 0);\n+\tif (!cmdq->cmd_infos) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate cmd info for cmdq failed\");\n+\t\terr = -ENOMEM;\n+\t\tgoto cmd_infos_err;\n+\t}\n+\n+\terr = spnic_alloc_db_addr(hwdev, &db_base, NULL);\n+\tif (err)\n+\t\tgoto alloc_db_err;\n+\n+\tcmdq->db_base = (u8 *)db_base;\n+\n+\treturn 0;\n+\n+alloc_db_err:\n+\trte_free(cmdq->cmd_infos);\n+\n+cmd_infos_err:\n+\trte_free(cmdq->errcode);\n+\n+\treturn err;\n+}\n+\n+static void free_cmdq(struct spnic_hwdev *hwdev, struct spnic_cmdq *cmdq)\n+{\n+\tspnic_free_db_addr(hwdev, cmdq->db_base, NULL);\n+\trte_free(cmdq->cmd_infos);\n+\trte_free(cmdq->errcode);\n+}\n+\n+static int spnic_set_cmdq_ctxts(struct spnic_hwdev *hwdev)\n+{\n+\tstruct spnic_cmdqs *cmdqs = hwdev->cmdqs;\n+\tstruct spnic_cmd_cmdq_ctxt cmdq_ctxt;\n+\tenum spnic_cmdq_type cmdq_type;\n+\tu16 out_size = sizeof(cmdq_ctxt);\n+\tint err;\n+\n+\tcmdq_type = SPNIC_CMDQ_SYNC;\n+\tfor (; cmdq_type < SPNIC_MAX_CMDQ_TYPES; cmdq_type++) {\n+\t\tmemset(&cmdq_ctxt, 0, sizeof(cmdq_ctxt));\n+\t\tmemcpy(&cmdq_ctxt.ctxt_info, &cmdqs->cmdq[cmdq_type].cmdq_ctxt,\n+\t\t\tsizeof(cmdq_ctxt.ctxt_info));\n+\t\tcmdq_ctxt.func_idx = spnic_global_func_id(hwdev);\n+\t\tcmdq_ctxt.cmdq_id = cmdq_type;\n+\n+\t\terr = spnic_msg_to_mgmt_sync(hwdev, SPNIC_MOD_COMM,\n+\t\t\t\t\t MGMT_CMD_SET_CMDQ_CTXT,\n+\t\t\t\t\t &cmdq_ctxt, sizeof(cmdq_ctxt),\n+\t\t\t\t\t &cmdq_ctxt, &out_size, 0);\n+\t\tif (err || !out_size || cmdq_ctxt.status) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Set cmdq ctxt failed, err: %d, status: 0x%x, out_size: 0x%x\",\n+\t\t\t\t err, cmdq_ctxt.status, out_size);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t}\n+\n+\tcmdqs->status |= SPNIC_CMDQ_ENABLE;\n+\n+\treturn 0;\n+}\n+\n+int spnic_reinit_cmdq_ctxts(struct spnic_hwdev *hwdev)\n+{\n+\treturn spnic_set_cmdq_ctxts(hwdev);\n+}\n+\n+int spnic_cmdqs_init(struct spnic_hwdev *hwdev)\n+{\n+\tstruct spnic_cmdqs *cmdqs = NULL;\n+\tenum spnic_cmdq_type type, cmdq_type;\n+\tchar cmdq_pool_name[RTE_MEMPOOL_NAMESIZE];\n+\tint err;\n+\n+\tcmdqs = rte_zmalloc(NULL, sizeof(*cmdqs), 0);\n+\tif (!cmdqs)\n+\t\treturn -ENOMEM;\n+\n+\thwdev->cmdqs = cmdqs;\n+\tcmdqs->hwdev = hwdev;\n+\n+\tmemset(cmdq_pool_name, 0, RTE_MEMPOOL_NAMESIZE);\n+\tsnprintf(cmdq_pool_name, sizeof(cmdq_pool_name), \"spnic_cmdq_%u\",\n+\t\t hwdev->port_id);\n+\n+\tcmdqs->cmd_buf_pool = rte_pktmbuf_pool_create(cmdq_pool_name,\n+\t\t\t\tSPNIC_CMDQ_DEPTH * SPNIC_MAX_CMDQ_TYPES,\n+\t\t\t\t0, 0, SPNIC_CMDQ_BUF_SIZE, rte_socket_id());\n+\tif (!cmdqs->cmd_buf_pool) {\n+\t\tPMD_DRV_LOG(ERR, \"Create cmdq buffer pool failed\");\n+\t\terr = -ENOMEM;\n+\t\tgoto pool_create_err;\n+\t}\n+\n+\tcmdq_type = SPNIC_CMDQ_SYNC;\n+\tfor (; cmdq_type < SPNIC_MAX_CMDQ_TYPES; cmdq_type++) {\n+\t\terr = init_cmdq(&cmdqs->cmdq[cmdq_type], hwdev,\n+\t\t\t\t&cmdqs->saved_wqs[cmdq_type], cmdq_type);\n+\t\tif (err) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Initialize cmdq failed\");\n+\t\t\tgoto init_cmdq_err;\n+\t\t}\n+\t}\n+\n+\terr = spnic_set_cmdq_ctxts(hwdev);\n+\tif (err)\n+\t\tgoto init_cmdq_err;\n+\n+\treturn 0;\n+\n+init_cmdq_err:\n+\ttype = SPNIC_CMDQ_SYNC;\n+\tfor (; type < cmdq_type; type++)\n+\t\tfree_cmdq(hwdev, &cmdqs->cmdq[type]);\n+\n+\trte_mempool_free(cmdqs->cmd_buf_pool);\n+\n+pool_create_err:\n+\trte_free(cmdqs);\n+\n+\treturn err;\n+}\n+\n+void spnic_cmdqs_free(struct spnic_hwdev *hwdev)\n+{\n+\tstruct spnic_cmdqs *cmdqs = hwdev->cmdqs;\n+\tenum spnic_cmdq_type cmdq_type = SPNIC_CMDQ_SYNC;\n+\n+\tcmdqs->status &= ~SPNIC_CMDQ_ENABLE;\n+\n+\tfor (; cmdq_type < SPNIC_MAX_CMDQ_TYPES; cmdq_type++)\n+\t\tfree_cmdq(cmdqs->hwdev, &cmdqs->cmdq[cmdq_type]);\n+\n+\trte_mempool_free(cmdqs->cmd_buf_pool);\n+\n+\trte_free(cmdqs->saved_wqs);\n+\n+\trte_free(cmdqs);\n+}\ndiff --git a/drivers/net/spnic/base/spnic_cmdq.h b/drivers/net/spnic/base/spnic_cmdq.h\nnew file mode 100644\nindex 0000000000..71753be6e8\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_cmdq.h\n@@ -0,0 +1,228 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#ifndef _SPNIC_CMDQ_H_\n+#define _SPNIC_CMDQ_H_\n+\n+#define SPNIC_SCMD_DATA_LEN\t\t16\n+\n+/* Pmd driver uses 64, kernel l2nic uses 4096 */\n+#define SPNIC_CMDQ_DEPTH\t\t64\n+\n+#define SPNIC_CMDQ_BUF_SIZE\t\t2048U\n+#define SPNIC_CMDQ_BUF_HW_RSVD\t\t8\n+#define SPNIC_CMDQ_MAX_DATA_SIZE\t(SPNIC_CMDQ_BUF_SIZE\t\\\n+\t\t\t\t\t - SPNIC_CMDQ_BUF_HW_RSVD)\n+\n+#define SPNIC_CEQ_ID_CMDQ\t\t0\n+\n+enum cmdq_scmd_type {\n+\tCMDQ_SET_ARM_CMD = 2,\n+};\n+\n+enum cmdq_wqe_type {\n+\tWQE_LCMD_TYPE,\n+\tWQE_SCMD_TYPE\n+};\n+\n+enum ctrl_sect_len {\n+\tCTRL_SECT_LEN = 1,\n+\tCTRL_DIRECT_SECT_LEN = 2\n+};\n+\n+enum bufdesc_len {\n+\tBUFDESC_LCMD_LEN = 2,\n+\tBUFDESC_SCMD_LEN = 3\n+};\n+\n+enum data_format {\n+\tDATA_SGE,\n+};\n+\n+enum completion_format {\n+\tCOMPLETE_DIRECT,\n+\tCOMPLETE_SGE\n+};\n+\n+enum completion_request {\n+\tCEQ_SET = 1,\n+};\n+\n+enum cmdq_cmd_type {\n+\tSYNC_CMD_DIRECT_RESP,\n+\tSYNC_CMD_SGE_RESP,\n+\tASYNC_CMD\n+};\n+\n+enum spnic_cmdq_type {\n+\tSPNIC_CMDQ_SYNC,\n+\tSPNIC_CMDQ_ASYNC,\n+\tSPNIC_MAX_CMDQ_TYPES\n+};\n+\n+enum spnic_db_src_type {\n+\tSPNIC_DB_SRC_CMDQ_TYPE,\n+\tSPNIC_DB_SRC_L2NIC_SQ_TYPE\n+};\n+\n+enum spnic_cmdq_db_type {\n+\tSPNIC_DB_SQ_RQ_TYPE,\n+\tSPNIC_DB_CMDQ_TYPE\n+};\n+\n+/* Cmdq ack type */\n+enum spnic_ack_type {\n+\tSPNIC_ACK_TYPE_CMDQ,\n+\tSPNIC_ACK_TYPE_SHARE_CQN,\n+\tSPNIC_ACK_TYPE_APP_CQN,\n+\n+\tSPNIC_MOD_ACK_MAX = 15\n+};\n+\n+/* Cmdq wqe ctrls */\n+struct spnic_cmdq_header {\n+\tu32 header_info;\n+\tu32 saved_data;\n+};\n+\n+struct spnic_scmd_bufdesc {\n+\tu32 buf_len;\n+\tu32 rsvd;\n+\tu8 data[SPNIC_SCMD_DATA_LEN];\n+};\n+\n+struct spnic_lcmd_bufdesc {\n+\tu32 rsvd1;\n+\tu64 saved_async_buf;\n+\tu64 rsvd3;\n+};\n+\n+struct spnic_cmdq_db {\n+\tu32 db_head;\n+\tu32 db_info;\n+};\n+\n+struct spnic_status {\n+\tu32 status_info;\n+};\n+\n+struct spnic_ctrl {\n+\tu32 ctrl_info;\n+};\n+\n+struct spnic_sge_resp {\n+\tu32 rsvd;\n+};\n+\n+struct spnic_cmdq_completion {\n+\t/* HW format */\n+\tunion {\n+\t\tstruct spnic_sge_resp sge_resp;\n+\t\tu64 direct_resp;\n+\t};\n+};\n+\n+struct spnic_cmdq_wqe_scmd {\n+\tstruct spnic_cmdq_header header;\n+\tu64 rsvd;\n+\tstruct spnic_status status;\n+\tstruct spnic_ctrl ctrl;\n+\tstruct spnic_cmdq_completion completion;\n+\tstruct spnic_scmd_bufdesc buf_desc;\n+};\n+\n+struct spnic_cmdq_wqe_lcmd {\n+\tstruct spnic_cmdq_header header;\n+\tstruct spnic_status status;\n+\tstruct spnic_ctrl ctrl;\n+\tstruct spnic_cmdq_completion completion;\n+\tstruct spnic_lcmd_bufdesc buf_desc;\n+};\n+\n+struct spnic_cmdq_inline_wqe {\n+\tstruct spnic_cmdq_wqe_scmd wqe_scmd;\n+};\n+\n+struct spnic_cmdq_wqe {\n+\t/* HW format */\n+\tunion {\n+\t\tstruct spnic_cmdq_inline_wqe inline_wqe;\n+\t\tstruct spnic_cmdq_wqe_lcmd wqe_lcmd;\n+\t};\n+};\n+\n+struct spnic_cmdq_ctxt_info {\n+\tu64 curr_wqe_page_pfn;\n+\tu64 wq_block_pfn;\n+};\n+\n+struct spnic_cmd_cmdq_ctxt {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tu16 func_idx;\n+\tu8 cmdq_id;\n+\tu8 rsvd1[5];\n+\n+\tstruct spnic_cmdq_ctxt_info ctxt_info;\n+};\n+\n+enum spnic_cmdq_status {\n+\tSPNIC_CMDQ_ENABLE = BIT(0),\n+};\n+\n+enum spnic_cmdq_cmd_type {\n+\tSPNIC_CMD_TYPE_NONE,\n+\tSPNIC_CMD_TYPE_SET_ARM,\n+\tSPNIC_CMD_TYPE_DIRECT_RESP,\n+\tSPNIC_CMD_TYPE_SGE_RESP\n+};\n+\n+struct spnic_cmdq_cmd_info {\n+\tenum spnic_cmdq_cmd_type cmd_type;\n+};\n+\n+struct spnic_cmdq {\n+\tstruct spnic_wq *wq;\n+\n+\tenum spnic_cmdq_type cmdq_type;\n+\tint wrapped;\n+\n+\tint *errcode;\n+\tu8 *db_base;\n+\n+\trte_spinlock_t cmdq_lock;\n+\n+\tstruct spnic_cmdq_ctxt_info cmdq_ctxt;\n+\n+\tstruct spnic_cmdq_cmd_info *cmd_infos;\n+};\n+\n+struct spnic_cmdqs {\n+\tstruct spnic_hwdev *hwdev;\n+\n+\tstruct rte_mempool *cmd_buf_pool;\n+\n+\tstruct spnic_wq *saved_wqs;\n+\n+\tstruct spnic_cmdq cmdq[SPNIC_MAX_CMDQ_TYPES];\n+\n+\tu32 status;\n+};\n+\n+struct spnic_cmd_buf {\n+\tvoid *buf;\n+\tuint64_t dma_addr;\n+\tstruct rte_mbuf *mbuf;\n+\tu16 size;\n+};\n+\n+int spnic_reinit_cmdq_ctxts(struct spnic_hwdev *hwdev);\n+\n+int spnic_cmdqs_init(struct spnic_hwdev *hwdev);\n+\n+void spnic_cmdqs_free(struct spnic_hwdev *hwdev);\n+\n+#endif /* _SPNIC_CMDQ_H_ */\ndiff --git a/drivers/net/spnic/base/spnic_hw_comm.c b/drivers/net/spnic/base/spnic_hw_comm.c\nnew file mode 100644\nindex 0000000000..7c58989c14\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_hw_comm.c\n@@ -0,0 +1,222 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#include <ethdev_driver.h>\n+#include <rte_bus_pci.h>\n+#include <rte_hash.h>\n+#include <rte_jhash.h>\n+\n+#include \"spnic_compat.h\"\n+#include \"spnic_csr.h\"\n+#include \"spnic_hwdev.h\"\n+#include \"spnic_hwif.h\"\n+#include \"spnic_mgmt.h\"\n+#include \"spnic_cmdq.h\"\n+#include \"spnic_hw_comm.h\"\n+#include \"spnic_cmd.h\"\n+\n+#define\tSPNIC_MSIX_CNT_LLI_TIMER_SHIFT\t\t\t0\n+#define\tSPNIC_MSIX_CNT_LLI_CREDIT_SHIFT\t\t\t8\n+#define\tSPNIC_MSIX_CNT_COALESC_TIMER_SHIFT\t\t8\n+#define\tSPNIC_MSIX_CNT_PENDING_SHIFT\t\t\t8\n+#define\tSPNIC_MSIX_CNT_RESEND_TIMER_SHIFT\t\t29\n+\n+#define\tSPNIC_MSIX_CNT_LLI_TIMER_MASK\t\t\t0xFFU\n+#define\tSPNIC_MSIX_CNT_LLI_CREDIT_MASK\t\t\t0xFFU\n+#define\tSPNIC_MSIX_CNT_COALESC_TIMER_MASK\t\t0xFFU\n+#define\tSPNIC_MSIX_CNT_PENDING_MASK\t\t\t0x1FU\n+#define\tSPNIC_MSIX_CNT_RESEND_TIMER_MASK\t\t0x7U\n+\n+int spnic_get_interrupt_cfg(void *dev, struct interrupt_info *info)\n+{\n+\tstruct spnic_hwdev *hwdev = dev;\n+\tstruct spnic_cmd_msix_config msix_cfg;\n+\tu16 out_size = sizeof(msix_cfg);\n+\tint err;\n+\n+\tif (!hwdev || !info)\n+\t\treturn -EINVAL;\n+\n+\tmemset(&msix_cfg, 0, sizeof(msix_cfg));\n+\tmsix_cfg.func_id = spnic_global_func_id(hwdev);\n+\tmsix_cfg.msix_index = info->msix_index;\n+\tmsix_cfg.opcode = SPNIC_MGMT_CMD_OP_GET;\n+\n+\terr = spnic_msg_to_mgmt_sync(hwdev, SPNIC_MOD_COMM,\n+\t\t\t\t MGMT_CMD_CFG_MSIX_CTRL_REG,\n+\t\t\t\t &msix_cfg, sizeof(msix_cfg),\n+\t\t\t\t &msix_cfg, &out_size, 0);\n+\tif (err || !out_size || msix_cfg.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Get interrupt config failed, err: %d, \"\n+\t\t\t \"status: 0x%x, out size: 0x%x\",\n+\t\t\t err, msix_cfg.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tinfo->lli_credit_limit = msix_cfg.lli_credit_cnt;\n+\tinfo->lli_timer_cfg = msix_cfg.lli_tmier_cnt;\n+\tinfo->pending_limt = msix_cfg.pending_cnt;\n+\tinfo->coalesc_timer_cfg = msix_cfg.coalesct_timer_cnt;\n+\tinfo->resend_timer_cfg = msix_cfg.resend_timer_cnt;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Set interrupt cfg\n+ *\n+ * @param[in] dev\n+ * The pointer to the private hardware device object\n+ * @param[in] info\n+ * Interrupt info\n+ *\n+ * @retval zero : Success\n+ * @retval negative : Failure.\n+ */\n+int spnic_set_interrupt_cfg(void *dev, struct interrupt_info info)\n+{\n+\tstruct spnic_hwdev *hwdev = dev;\n+\tstruct spnic_cmd_msix_config msix_cfg;\n+\tstruct interrupt_info temp_info;\n+\tu16 out_size = sizeof(msix_cfg);\n+\tint err;\n+\n+\tif (!hwdev)\n+\t\treturn -EINVAL;\n+\n+\ttemp_info.msix_index = info.msix_index;\n+\terr = spnic_get_interrupt_cfg(hwdev, &temp_info);\n+\tif (err)\n+\t\treturn -EIO;\n+\n+\tmemset(&msix_cfg, 0, sizeof(msix_cfg));\n+\tmsix_cfg.func_id = spnic_global_func_id(hwdev);\n+\tmsix_cfg.msix_index = (u16)info.msix_index;\n+\tmsix_cfg.opcode = SPNIC_MGMT_CMD_OP_SET;\n+\n+\tmsix_cfg.lli_credit_cnt = temp_info.lli_credit_limit;\n+\tmsix_cfg.lli_tmier_cnt = temp_info.lli_timer_cfg;\n+\tmsix_cfg.pending_cnt = temp_info.pending_limt;\n+\tmsix_cfg.coalesct_timer_cnt = temp_info.coalesc_timer_cfg;\n+\tmsix_cfg.resend_timer_cnt = temp_info.resend_timer_cfg;\n+\n+\tif (info.lli_set) {\n+\t\tmsix_cfg.lli_credit_cnt = info.lli_credit_limit;\n+\t\tmsix_cfg.lli_tmier_cnt = info.lli_timer_cfg;\n+\t}\n+\n+\tif (info.interrupt_coalesc_set) {\n+\t\tmsix_cfg.pending_cnt = info.pending_limt;\n+\t\tmsix_cfg.coalesct_timer_cnt = info.coalesc_timer_cfg;\n+\t\tmsix_cfg.resend_timer_cnt = info.resend_timer_cfg;\n+\t}\n+\n+\terr = spnic_msg_to_mgmt_sync(hwdev, SPNIC_MOD_COMM,\n+\t\t\t\t MGMT_CMD_CFG_MSIX_CTRL_REG,\n+\t\t\t\t &msix_cfg, sizeof(msix_cfg),\n+\t\t\t\t &msix_cfg, &out_size, 0);\n+\tif (err || !out_size || msix_cfg.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Set interrupt config failed, err: %d, \"\n+\t\t\t \"status: 0x%x, out size: 0x%x\",\n+\t\t\t err, msix_cfg.status, out_size);\n+\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int spnic_set_wq_page_size(void *hwdev, u16 func_idx, u32 page_size)\n+{\n+\tstruct spnic_cmd_wq_page_size page_size_info;\n+\tu16 out_size = sizeof(page_size_info);\n+\tint err;\n+\n+\tmemset(&page_size_info, 0, sizeof(page_size_info));\n+\tpage_size_info.func_idx = func_idx;\n+\tpage_size_info.page_size = SPNIC_PAGE_SIZE_HW(page_size);\n+\tpage_size_info.opcode = SPNIC_MGMT_CMD_OP_SET;\n+\n+\terr = spnic_msg_to_mgmt_sync(hwdev, SPNIC_MOD_COMM,\n+\t\t\t\t MGMT_CMD_CFG_PAGESIZE,\n+\t\t\t\t &page_size_info, sizeof(page_size_info),\n+\t\t\t\t &page_size_info, &out_size, 0);\n+\tif (err || !out_size || page_size_info.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Set wq page size failed, err: %d, \"\n+\t\t\t \"status: 0x%x, out_size: 0x%0x\",\n+\t\t\t err, page_size_info.status, out_size);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int spnic_set_cmdq_depth(void *hwdev, u16 cmdq_depth)\n+{\n+\tstruct spnic_cmd_root_ctxt root_ctxt;\n+\tu16 out_size = sizeof(root_ctxt);\n+\tint err;\n+\n+\tmemset(&root_ctxt, 0, sizeof(root_ctxt));\n+\troot_ctxt.func_idx = spnic_global_func_id(hwdev);\n+\troot_ctxt.set_cmdq_depth = 1;\n+\troot_ctxt.cmdq_depth = (u8)ilog2(cmdq_depth);\n+\n+\terr = spnic_msg_to_mgmt_sync(hwdev, SPNIC_MOD_COMM, MGMT_CMD_SET_VAT,\n+\t\t\t\t &root_ctxt, sizeof(root_ctxt),\n+\t\t\t\t &root_ctxt, &out_size, 0);\n+\tif (err || !out_size || root_ctxt.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Set cmdq depth failed, err: %d, status: 0x%x, out_size: 0x%x\",\n+\t\t\t err, root_ctxt.status, out_size);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Set the dma attributes for entry\n+ *\n+ * @param[in] hwdev\n+ * The pointer to the private hardware device object\n+ * @param[in] entry_idx\n+ * The entry index in the dma table\n+ * @param[in] st\n+ * PCIE TLP steering tag\n+ * @param[in] at\n+ * PCIE TLP AT field\n+ * @param[in] ph\n+ * PCIE TLP Processing Hint field\n+ * @param[in] no_snooping\n+ * PCIE TLP No snooping\n+ * @param[in] tph_en\n+ * PCIE TLP Processing Hint Enable\n+ */\n+int spnic_set_dma_attr_tbl(struct spnic_hwdev *hwdev, u32 entry_idx, u8 st,\n+\t\t\t u8 at, u8 ph, u8 no_snooping, u8 tph_en)\n+{\n+\tstruct comm_cmd_dma_attr_config dma_attr;\n+\tu16 out_size = sizeof(dma_attr);\n+\tint err;\n+\n+\tmemset(&dma_attr, 0, sizeof(dma_attr));\n+\tdma_attr.func_id = spnic_global_func_id(hwdev);\n+\tdma_attr.entry_idx = entry_idx;\n+\tdma_attr.st = st;\n+\tdma_attr.at = at;\n+\tdma_attr.ph = ph;\n+\tdma_attr.no_snooping = no_snooping;\n+\tdma_attr.tph_en = tph_en;\n+\n+\terr = spnic_msg_to_mgmt_sync(hwdev, SPNIC_MOD_COMM,\n+\t\t\t\t MGMT_CMD_SET_DMA_ATTR,\n+\t\t\t\t &dma_attr, sizeof(dma_attr),\n+\t\t\t\t &dma_attr, &out_size, 0);\n+\tif (err || !out_size || dma_attr.head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set dma attr, err: %d, status: 0x%x, out_size: 0x%x\\n\",\n+\t\t\t err, dma_attr.head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/spnic/base/spnic_hw_comm.h b/drivers/net/spnic/base/spnic_hw_comm.h\nnew file mode 100644\nindex 0000000000..c905f49b7a\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_hw_comm.h\n@@ -0,0 +1,176 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#ifndef _SPNIC_HW_COMM_H_\n+#define _SPNIC_HW_COMM_H_\n+\n+#define SPNIC_MGMT_CMD_OP_GET\t0\n+#define SPNIC_MGMT_CMD_OP_SET\t1\n+\n+#define\tSPNIC_MSIX_CNT_LLI_TIMER_SHIFT\t\t\t0\n+#define\tSPNIC_MSIX_CNT_LLI_CREDIT_SHIFT\t\t\t8\n+#define\tSPNIC_MSIX_CNT_COALESC_TIMER_SHIFT\t\t8\n+#define\tSPNIC_MSIX_CNT_PENDING_SHIFT\t\t\t8\n+#define\tSPNIC_MSIX_CNT_RESEND_TIMER_SHIFT\t\t29\n+\n+#define\tSPNIC_MSIX_CNT_LLI_TIMER_MASK\t\t\t0xFFU\n+#define\tSPNIC_MSIX_CNT_LLI_CREDIT_MASK\t\t\t0xFFU\n+#define\tSPNIC_MSIX_CNT_COALESC_TIMER_MASK\t\t0xFFU\n+#define\tSPNIC_MSIX_CNT_PENDING_MASK\t\t\t0x1FU\n+#define\tSPNIC_MSIX_CNT_RESEND_TIMER_MASK\t\t0x7U\n+\n+#define SPNIC_MSIX_CNT_SET(val, member)\t\t\\\n+\t\t(((val) & SPNIC_MSIX_CNT_##member##_MASK) << \\\n+\t\tSPNIC_MSIX_CNT_##member##_SHIFT)\n+\n+#define MSG_TO_MGMT_SYNC_RETURN_ERR(err, out_size, status)\t\\\n+\t\t((err) || (status) || !(out_size))\n+\n+struct spnic_cmd_msix_config {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tu16 func_id;\n+\tu8 opcode;\n+\tu8 rsvd1;\n+\tu16 msix_index;\n+\tu8 pending_cnt;\n+\tu8 coalesct_timer_cnt;\n+\tu8 resend_timer_cnt;\n+\tu8 lli_tmier_cnt;\n+\tu8 lli_credit_cnt;\n+\tu8 rsvd2[5];\n+};\n+\n+#define SPNIC_PAGE_SIZE_HW(pg_size)\t((u8)ilog2((u32)((pg_size) >> 12)))\n+\n+struct spnic_cmd_wq_page_size {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tu16 func_idx;\n+\tu8 opcode;\n+\t/*\n+\t * Real size is 4KB * 2^page_size, range(0~20) must be checked\n+\t * by driver\n+\t */\n+\tu8 page_size;\n+\n+\tu32 rsvd1;\n+};\n+\n+struct spnic_reset {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tu16 func_id;\n+\tu16 rsvd1[3];\n+\tu64 reset_flag;\n+};\n+\n+struct spnic_cmd_root_ctxt {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tu16 func_idx;\n+\tu8 set_cmdq_depth;\n+\tu8 cmdq_depth;\n+\tu16 rx_buf_sz;\n+\tu8 lro_en;\n+\tu8 rsvd1;\n+\tu16 sq_depth;\n+\tu16 rq_depth;\n+\tu64 rsvd2;\n+};\n+\n+enum spnic_fw_ver_type {\n+\tSPNIC_FW_VER_TYPE_BOOT,\n+\tSPNIC_FW_VER_TYPE_MPU,\n+\tSPNIC_FW_VER_TYPE_NPU,\n+\tSPNIC_FW_VER_TYPE_SMU,\n+\tSPNIC_FW_VER_TYPE_CFG,\n+};\n+\n+struct comm_cmd_dma_attr_config {\n+\tstruct mgmt_msg_head head;\n+\n+\tu16 func_id;\n+\tu8 entry_idx;\n+\tu8 st;\n+\tu8 at;\n+\tu8 ph;\n+\tu8 no_snooping;\n+\tu8 tph_en;\n+\tu32 resv1;\n+};\n+\n+#define SPNIC_FW_VERSION_LEN\t\t16\n+#define SPNIC_FW_COMPILE_TIME_LEN\t20\n+#define SPNIC_MGMT_VERSION_MAX_LEN\t32\n+struct spnic_cmd_get_fw_version {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tu16 fw_type;\n+\tu16 rsvd1;\n+\tu8 ver[SPNIC_FW_VERSION_LEN];\n+\tu8 time[SPNIC_FW_COMPILE_TIME_LEN];\n+};\n+\n+struct spnic_cmd_clear_doorbell {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tu16 func_idx;\n+\tu16 rsvd1[3];\n+};\n+\n+struct spnic_cmd_clear_resource {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tu16 func_idx;\n+\tu16 rsvd1[3];\n+};\n+\n+struct spnic_cmd_board_info {\n+\tu8 status;\n+\tu8 version;\n+\tu8 rsvd0[6];\n+\n+\tstruct spnic_board_info info;\n+\n+\tu32 rsvd1[25];\n+};\n+\n+struct interrupt_info {\n+\tu32 lli_set;\n+\tu32 interrupt_coalesc_set;\n+\tu16 msix_index;\n+\tu8 lli_credit_limit;\n+\tu8 lli_timer_cfg;\n+\tu8 pending_limt;\n+\tu8 coalesc_timer_cfg;\n+\tu8 resend_timer_cfg;\n+};\n+\n+int spnic_get_interrupt_cfg(void *dev, struct interrupt_info *info);\n+\n+int spnic_set_interrupt_cfg(void *dev, struct interrupt_info info);\n+\n+int spnic_set_wq_page_size(void *hwdev, u16 func_idx, u32 page_size);\n+\n+int spnic_set_cmdq_depth(void *hwdev, u16 cmdq_depth);\n+\n+int spnic_set_dma_attr_tbl(struct spnic_hwdev *hwdev, u32 entry_idx, u8 st,\n+\t\t\t u8 at, u8 ph, u8 no_snooping, u8 tph_en);\n+\n+#endif\ndiff --git a/drivers/net/spnic/base/spnic_hwdev.c b/drivers/net/spnic/base/spnic_hwdev.c\nindex 2b5154f8a4..5671cb860c 100644\n--- a/drivers/net/spnic/base/spnic_hwdev.c\n+++ b/drivers/net/spnic/base/spnic_hwdev.c\n@@ -9,7 +9,64 @@\n #include \"spnic_mgmt.h\"\n #include \"spnic_cmd.h\"\n #include \"spnic_mbox.h\"\n+#include \"spnic_cmdq.h\"\n #include \"spnic_hwdev.h\"\n+#include \"spnic_hw_comm.h\"\n+\n+enum spnic_pcie_nosnoop {\n+\tSPNIC_PCIE_SNOOP = 0,\n+\tSPNIC_PCIE_NO_SNOOP = 1\n+};\n+\n+enum spnic_pcie_tph {\n+\tSPNIC_PCIE_TPH_DISABLE = 0,\n+\tSPNIC_PCIE_TPH_ENABLE = 1\n+};\n+\n+#define SPNIC_DMA_ATTR_INDIR_IDX_SHIFT\t\t\t\t0\n+\n+#define SPNIC_DMA_ATTR_INDIR_IDX_MASK\t\t\t\t0x3FF\n+\n+#define SPNIC_DMA_ATTR_INDIR_IDX_SET(val, member)\t\t\t\\\n+\t\t(((u32)(val) & SPNIC_DMA_ATTR_INDIR_##member##_MASK) << \\\n+\t\t\tSPNIC_DMA_ATTR_INDIR_##member##_SHIFT)\n+\n+#define SPNIC_DMA_ATTR_INDIR_IDX_CLEAR(val, member)\t\t\\\n+\t\t((val) & (~(SPNIC_DMA_ATTR_INDIR_##member##_MASK\t\\\n+\t\t\t<< SPNIC_DMA_ATTR_INDIR_##member##_SHIFT)))\n+\n+#define SPNIC_DMA_ATTR_ENTRY_ST_SHIFT\t\t\t\t0\n+#define SPNIC_DMA_ATTR_ENTRY_AT_SHIFT\t\t\t\t8\n+#define SPNIC_DMA_ATTR_ENTRY_PH_SHIFT\t\t\t\t10\n+#define SPNIC_DMA_ATTR_ENTRY_NO_SNOOPING_SHIFT\t\t\t12\n+#define SPNIC_DMA_ATTR_ENTRY_TPH_EN_SHIFT\t\t\t13\n+\n+#define SPNIC_DMA_ATTR_ENTRY_ST_MASK\t\t\t\t0xFF\n+#define SPNIC_DMA_ATTR_ENTRY_AT_MASK\t\t\t\t0x3\n+#define SPNIC_DMA_ATTR_ENTRY_PH_MASK\t\t\t\t0x3\n+#define SPNIC_DMA_ATTR_ENTRY_NO_SNOOPING_MASK\t\t\t0x1\n+#define SPNIC_DMA_ATTR_ENTRY_TPH_EN_MASK\t\t\t0x1\n+\n+#define SPNIC_DMA_ATTR_ENTRY_SET(val, member)\t\t\t\\\n+\t\t(((u32)(val) & SPNIC_DMA_ATTR_ENTRY_##member##_MASK) << \\\n+\t\t\tSPNIC_DMA_ATTR_ENTRY_##member##_SHIFT)\n+\n+#define SPNIC_DMA_ATTR_ENTRY_CLEAR(val, member)\t\t\\\n+\t\t((val) & (~(SPNIC_DMA_ATTR_ENTRY_##member##_MASK\t\\\n+\t\t\t<< SPNIC_DMA_ATTR_ENTRY_##member##_SHIFT)))\n+\n+#define SPNIC_PCIE_ST_DISABLE\t\t\t0\n+#define SPNIC_PCIE_AT_DISABLE\t\t\t0\n+#define SPNIC_PCIE_PH_DISABLE\t\t\t0\n+\n+#define PCIE_MSIX_ATTR_ENTRY\t\t\t0\n+\n+#define SPNIC_CHIP_PRESENT\t\t\t1\n+#define SPNIC_CHIP_ABSENT\t\t\t0\n+\n+#define SPNIC_DEAULT_EQ_MSIX_PENDING_LIMIT\t0\n+#define SPNIC_DEAULT_EQ_MSIX_COALESC_TIMER_CFG\t0xFF\n+#define SPNIC_DEAULT_EQ_MSIX_RESEND_TIMER_CFG\t7\n \n typedef void (*mgmt_event_cb)(void *handle, void *buf_in, u16 in_size,\n \t\t\t void *buf_out, u16 *out_size);\n@@ -100,6 +157,78 @@ void pf_handle_mgmt_comm_event(void *handle, __rte_unused void *pri_handle,\n \tPMD_DRV_LOG(WARNING, \"Unsupported mgmt cpu event %d to process\", cmd);\n }\n \n+/**\n+ * Initialize the default dma attributes\n+ *\n+ * @param[in] hwdev\n+ * The pointer to the private hardware device object\n+ *\n+ * @retval zero: Success\n+ * @retval non-zero: Failure\n+ */\n+static int dma_attr_table_init(struct spnic_hwdev *hwdev)\n+{\n+\tu32 addr, val, dst_attr;\n+\n+\t/* Use indirect access should set entry_idx first */\n+\taddr = SPNIC_CSR_DMA_ATTR_INDIR_IDX_ADDR;\n+\tval = spnic_hwif_read_reg(hwdev->hwif, addr);\n+\tval = SPNIC_DMA_ATTR_INDIR_IDX_CLEAR(val, IDX);\n+\n+\tval |= SPNIC_DMA_ATTR_INDIR_IDX_SET(PCIE_MSIX_ATTR_ENTRY, IDX);\n+\n+\tspnic_hwif_write_reg(hwdev->hwif, addr, val);\n+\n+\trte_wmb(); /* Write index before config */\n+\n+\taddr = SPNIC_CSR_DMA_ATTR_TBL_ADDR;\n+\tval = spnic_hwif_read_reg(hwdev->hwif, addr);\n+\n+\tdst_attr = SPNIC_DMA_ATTR_ENTRY_SET(SPNIC_PCIE_ST_DISABLE, ST)\t|\n+\t\tSPNIC_DMA_ATTR_ENTRY_SET(SPNIC_PCIE_AT_DISABLE, AT)\t|\n+\t\tSPNIC_DMA_ATTR_ENTRY_SET(SPNIC_PCIE_PH_DISABLE, PH)\t|\n+\t\tSPNIC_DMA_ATTR_ENTRY_SET(SPNIC_PCIE_SNOOP, NO_SNOOPING)\t|\n+\t\tSPNIC_DMA_ATTR_ENTRY_SET(SPNIC_PCIE_TPH_DISABLE, TPH_EN);\n+\n+\tif (val == dst_attr)\n+\t\treturn 0;\n+\n+\treturn spnic_set_dma_attr_tbl(hwdev, PCIE_MSIX_ATTR_ENTRY,\n+\t\t\t\t SPNIC_PCIE_ST_DISABLE,\n+\t\t\t\t SPNIC_PCIE_AT_DISABLE,\n+\t\t\t\t SPNIC_PCIE_PH_DISABLE,\n+\t\t\t\t SPNIC_PCIE_SNOOP,\n+\t\t\t\t SPNIC_PCIE_TPH_DISABLE);\n+}\n+\n+static int init_aeqs_msix_attr(struct spnic_hwdev *hwdev)\n+{\n+\tstruct spnic_aeqs *aeqs = hwdev->aeqs;\n+\tstruct interrupt_info info = {0};\n+\tstruct spnic_eq *eq = NULL;\n+\tu16 q_id;\n+\tint err;\n+\n+\tinfo.lli_set = 0;\n+\tinfo.interrupt_coalesc_set = 1;\n+\tinfo.pending_limt = SPNIC_DEAULT_EQ_MSIX_PENDING_LIMIT;\n+\tinfo.coalesc_timer_cfg = SPNIC_DEAULT_EQ_MSIX_COALESC_TIMER_CFG;\n+\tinfo.resend_timer_cfg = SPNIC_DEAULT_EQ_MSIX_RESEND_TIMER_CFG;\n+\n+\tfor (q_id = 0; q_id < aeqs->num_aeqs; q_id++) {\n+\t\teq = &aeqs->aeq[q_id];\n+\t\tinfo.msix_index = eq->eq_irq.msix_entry_idx;\n+\t\terr = spnic_set_interrupt_cfg(hwdev, info);\n+\t\tif (err) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Set msix attr for aeq %d failed\",\n+\t\t\t\tq_id);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int spnic_comm_pf_to_mgmt_init(struct spnic_hwdev *hwdev)\n {\n \tint err;\n@@ -124,6 +253,35 @@ static void spnic_comm_pf_to_mgmt_free(struct spnic_hwdev *hwdev)\n \tspnic_pf_to_mgmt_free(hwdev);\n }\n \n+static int spnic_comm_cmdqs_init(struct spnic_hwdev *hwdev)\n+{\n+\tint err;\n+\n+\terr = spnic_cmdqs_init(hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Init cmd queues failed\");\n+\t\treturn err;\n+\t}\n+\n+\terr = spnic_set_cmdq_depth(hwdev, SPNIC_CMDQ_DEPTH);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Set cmdq depth failed\");\n+\t\tgoto set_cmdq_depth_err;\n+\t}\n+\n+\treturn 0;\n+\n+set_cmdq_depth_err:\n+\tspnic_cmdqs_free(hwdev);\n+\n+\treturn err;\n+}\n+\n+static void spnic_comm_cmdqs_free(struct spnic_hwdev *hwdev)\n+{\n+\tspnic_cmdqs_free(hwdev);\n+}\n+\n static int init_mgmt_channel(struct spnic_hwdev *hwdev)\n {\n \tint err;\n@@ -164,6 +322,51 @@ static void free_mgmt_channel(struct spnic_hwdev *hwdev)\n \tspnic_aeqs_free(hwdev);\n }\n \n+#define SPNIC_DEFAULT_WQ_PAGE_SIZE\t0x100000\n+#define SPNIC_HW_WQ_PAGE_SIZE\t\t0x1000\n+\n+static int init_cmdqs_channel(struct spnic_hwdev *hwdev)\n+{\n+\tint err;\n+\n+\terr = dma_attr_table_init(hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Init dma attr table failed\");\n+\t\tgoto dma_attr_init_err;\n+\t}\n+\n+\terr = init_aeqs_msix_attr(hwdev);\n+\tif (err)\n+\t\tgoto init_aeqs_msix_err;\n+\n+\t/* Set default wq page_size */\n+\thwdev->wq_page_size = SPNIC_DEFAULT_WQ_PAGE_SIZE;\n+\terr = spnic_set_wq_page_size(hwdev, spnic_global_func_id(hwdev),\n+\t\t\t\t hwdev->wq_page_size);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Set wq page size failed\");\n+\t\tgoto init_wq_pg_size_err;\n+\t}\n+\n+\terr = spnic_comm_cmdqs_init(hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Init cmd queues failed\");\n+\t\tgoto cmdq_init_err;\n+\t}\n+\n+\treturn 0;\n+\n+cmdq_init_err:\n+\tif (SPNIC_FUNC_TYPE(hwdev) != TYPE_VF)\n+\t\tspnic_set_wq_page_size(hwdev, spnic_global_func_id(hwdev),\n+\t\t\t\t\tSPNIC_HW_WQ_PAGE_SIZE);\n+init_wq_pg_size_err:\n+init_aeqs_msix_err:\n+dma_attr_init_err:\n+\n+\treturn err;\n+}\n+\n static int spnic_init_comm_ch(struct spnic_hwdev *hwdev)\n {\n \tint err;\n@@ -174,11 +377,23 @@ static int spnic_init_comm_ch(struct spnic_hwdev *hwdev)\n \t\treturn err;\n \t}\n \n+\terr = init_cmdqs_channel(hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Init cmdq channel failed\");\n+\t\tgoto init_cmdqs_channel_err;\n+\t}\n+\n \treturn 0;\n+\n+init_cmdqs_channel_err:\n+\tfree_mgmt_channel(hwdev);\n+\n+\treturn err;\n }\n \n static void spnic_uninit_comm_ch(struct spnic_hwdev *hwdev)\n {\n+\tspnic_comm_cmdqs_free(hwdev);\n \tfree_mgmt_channel(hwdev);\n }\n \ndiff --git a/drivers/net/spnic/base/spnic_hwdev.h b/drivers/net/spnic/base/spnic_hwdev.h\nindex 4e77d776ee..8c581c7480 100644\n--- a/drivers/net/spnic/base/spnic_hwdev.h\n+++ b/drivers/net/spnic/base/spnic_hwdev.h\n@@ -91,13 +91,17 @@ struct spnic_hwdev {\n \tvoid *dev_handle; /* Pointer to spnic_nic_dev */\n \tvoid *pci_dev; /* Pointer to rte_pci_device */\n \tvoid *eth_dev; /* Pointer to rte_eth_dev */\n-\n+\tstruct spnic_hwif *hwif;\n \tuint16_t port_id;\n \n-\tstruct spnic_hwif *hwif;\n+\tu32 wq_page_size;\n+\n \tstruct spnic_mbox *func_to_func;\n \tstruct cfg_mgmt_info *cfg_mgmt;\n+\n+\tstruct spnic_cmdqs *cmdqs;\n \tstruct spnic_aeqs *aeqs;\n+\n \tstruct spnic_msg_pf_to_mgmt *pf_to_mgmt;\n \tu8 *chip_fault_stats;\n \tstruct spnic_hw_stats hw_stats;\ndiff --git a/drivers/net/spnic/base/spnic_wq.h b/drivers/net/spnic/base/spnic_wq.h\nnew file mode 100644\nindex 0000000000..032d45e79e\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_wq.h\n@@ -0,0 +1,57 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#ifndef _SPNIC_WQ_H_\n+#define _SPNIC_WQ_H_\n+\n+/* Use 0-level CLA, page size must be: SQ 16B(wqe) * 64k(max_q_depth) */\n+#define SPNIC_DEFAULT_WQ_PAGE_SIZE\t0x100000\n+#define SPNIC_HW_WQ_PAGE_SIZE\t\t0x1000\n+\n+#define CMDQ_BLOCKS_PER_PAGE\t\t8\n+#define CMDQ_BLOCK_SIZE\t\t\t512UL\n+#define CMDQ_PAGE_SIZE\t\t\tRTE_ALIGN((CMDQ_BLOCKS_PER_PAGE * \\\n+\t\t\t\t\t\tCMDQ_BLOCK_SIZE), PAGE_SIZE)\n+\n+#define CMDQ_BASE_VADDR(cmdq_pages, wq)\t\\\n+\t\t\t((u64 *)(((u64)((cmdq_pages)->cmdq_page_vaddr)) \\\n+\t\t\t\t+ (u64)((wq)->block_idx * CMDQ_BLOCK_SIZE)))\n+\n+#define CMDQ_BASE_PADDR(cmdq_pages, wq)\t\\\n+\t\t\t(((u64)((cmdq_pages)->cmdq_page_paddr)) \\\n+\t\t\t\t+ (u64)(wq)->block_idx * CMDQ_BLOCK_SIZE)\n+\n+#define CMDQ_BASE_ADDR(cmdq_pages, wq)\t\\\n+\t\t\t((u64 *)(((u64)((cmdq_pages)->cmdq_shadow_page_vaddr)) \\\n+\t\t\t\t+ (u64)((wq)->block_idx * CMDQ_BLOCK_SIZE)))\n+\n+#define MASKED_WQE_IDX(wq, idx)\t((idx) & (wq)->mask)\n+\n+#define\tWQ_WQE_ADDR(wq, idx) ((void *)((u64)((wq)->queue_buf_vaddr) + \\\n+\t\t\t ((idx) << (wq)->wqebb_shift)))\n+\n+struct spnic_wq {\n+\t/* The addresses are 64 bit in the HW */\n+\tu64 queue_buf_vaddr;\n+\n+\tu16 q_depth;\n+\tu16 mask;\n+\trte_atomic32_t delta;\n+\n+\tu32 cons_idx;\n+\tu32 prod_idx;\n+\n+\tu64 queue_buf_paddr;\n+\n+\tu32 wqebb_size;\n+\tu32 wqebb_shift;\n+\n+\tu32 wq_buf_size;\n+\n+\tconst struct rte_memzone *wq_mz;\n+\n+\tu32 rsvd[5];\n+};\n+\n+#endif /* _SPNIC_WQ_H_ :*/\n", "prefixes": [ "v1", "06/25" ] }