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GET /api/patches/105241/?format=api
{ "id": 105241, "url": "http://patches.dpdk.org/api/patches/105241/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/cd728bcbf84fd7128f2959f0935b0ef37e8ab3fd.1639636621.git.songyl@ramaxel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<cd728bcbf84fd7128f2959f0935b0ef37e8ab3fd.1639636621.git.songyl@ramaxel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/cd728bcbf84fd7128f2959f0935b0ef37e8ab3fd.1639636621.git.songyl@ramaxel.com", "date": "2021-12-18T02:51:29", "name": "[v1,02/25] net/spnic: initialize the HW interface", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6b8071a889f5155bbe885987abc89754c2bcb00d", "submitter": { "id": 2455, "url": "http://patches.dpdk.org/api/people/2455/?format=api", "name": "Yanling Song", "email": "songyl@ramaxel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/cd728bcbf84fd7128f2959f0935b0ef37e8ab3fd.1639636621.git.songyl@ramaxel.com/mbox/", "series": [ { "id": 20973, "url": "http://patches.dpdk.org/api/series/20973/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20973", "date": "2021-12-18T02:51:28", "name": "Net/SPNIC: support SPNIC into DPDK 22.03", "version": 1, "mbox": "http://patches.dpdk.org/series/20973/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105241/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105241/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 00A2BA04A4;\n\tSat, 18 Dec 2021 03:52:21 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C2BFF41142;\n\tSat, 18 Dec 2021 03:52:16 +0100 (CET)", "from VLXDG1SPAM1.ramaxel.com (email.ramaxel.com [221.4.138.186])\n by mails.dpdk.org (Postfix) with ESMTP id 123684067C\n for <dev@dpdk.org>; Sat, 18 Dec 2021 03:52:13 +0100 (CET)", "from V12DG1MBS01.ramaxel.local (v12dg1mbs01.ramaxel.local\n [172.26.18.31])\n by VLXDG1SPAM1.ramaxel.com with ESMTPS id 1BI2pwo5010301\n (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL);\n Sat, 18 Dec 2021 10:51:58 +0800 (GMT-8)\n (envelope-from songyl@ramaxel.com)", "from localhost.localdomain (10.64.9.47) by V12DG1MBS01.ramaxel.local\n (172.26.18.31) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Sat, 18\n Dec 2021 10:51:58 +0800" ], "From": "Yanling Song <songyl@ramaxel.com>", "To": "<dev@dpdk.org>", "CC": "<songyl@ramaxel.com>, <yanling.song@linux.dev>, <yanggan@ramaxel.com>,\n <ferruh.yigit@intel.com>", "Subject": "[PATCH v1 02/25] net/spnic: initialize the HW interface", "Date": "Sat, 18 Dec 2021 10:51:29 +0800", "Message-ID": "\n <cd728bcbf84fd7128f2959f0935b0ef37e8ab3fd.1639636621.git.songyl@ramaxel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<cover.1639636621.git.songyl@ramaxel.com>", "References": "<cover.1639636621.git.songyl@ramaxel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.64.9.47]", "X-ClientProxiedBy": "V12DG1MBS01.ramaxel.local (172.26.18.31) To\n V12DG1MBS01.ramaxel.local (172.26.18.31)", "X-DNSRBL": "", "X-MAIL": "VLXDG1SPAM1.ramaxel.com 1BI2pwo5010301", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add HW interface registers and initialize the HW\ninterface.\n\nSigned-off-by: Yanling Song <songyl@ramaxel.com>\n---\n drivers/net/spnic/base/meson.build | 2 +\n drivers/net/spnic/base/spnic_csr.h | 104 ++++\n drivers/net/spnic/base/spnic_hwdev.c | 41 ++\n drivers/net/spnic/base/spnic_hwdev.h | 29 +\n drivers/net/spnic/base/spnic_hwif.c | 774 +++++++++++++++++++++++++++\n drivers/net/spnic/base/spnic_hwif.h | 155 ++++++\n drivers/net/spnic/spnic_ethdev.c | 66 +++\n drivers/net/spnic/spnic_ethdev.h | 48 +-\n 8 files changed, 1212 insertions(+), 7 deletions(-)\n create mode 100644 drivers/net/spnic/base/spnic_csr.h\n create mode 100644 drivers/net/spnic/base/spnic_hwdev.c\n create mode 100644 drivers/net/spnic/base/spnic_hwdev.h\n create mode 100644 drivers/net/spnic/base/spnic_hwif.c\n create mode 100644 drivers/net/spnic/base/spnic_hwif.h", "diff": "diff --git a/drivers/net/spnic/base/meson.build b/drivers/net/spnic/base/meson.build\nindex e83a473881..edd6e94772 100644\n--- a/drivers/net/spnic/base/meson.build\n+++ b/drivers/net/spnic/base/meson.build\n@@ -2,6 +2,8 @@\n # Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n \n sources = [\n+\t'spnic_hwdev.c',\n+\t'spnic_hwif.c'\n ]\n \n extra_flags = []\ndiff --git a/drivers/net/spnic/base/spnic_csr.h b/drivers/net/spnic/base/spnic_csr.h\nnew file mode 100644\nindex 0000000000..602d5de6b1\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_csr.h\n@@ -0,0 +1,104 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#ifndef _SPNIC_CSR_H_\n+#define _SPNIC_CSR_H_\n+\n+#define PCI_VENDOR_ID_RAMAXEL\t\t\t0x1E81\n+\n+/* Device ids */\n+#define SPNIC_DEV_ID_PF\t\t\t\t0x9020\n+#define SPNIC_DEV_ID_VF\t\t\t\t0x9001\n+\n+/*\n+ * Bit30/bit31 for bar index flag\n+ * 00: bar0\n+ * 01: bar1\n+ * 10: bar2\n+ * 11: bar3\n+ */\n+#define SPNIC_CFG_REGS_FLAG\t\t\t0x40000000\n+\n+#define SPNIC_MGMT_REGS_FLAG\t\t\t0xC0000000\n+\n+#define SPNIC_REGS_FLAG_MAKS\t\t\t0x3FFFFFFF\n+\n+#define SPNIC_VF_CFG_REG_OFFSET 0x2000\n+\n+#define SPNIC_HOST_CSR_BASE_ADDR\t\t(SPNIC_MGMT_REGS_FLAG + 0x6000)\n+#define SPNIC_CSR_GLOBAL_BASE_ADDR\t\t(SPNIC_MGMT_REGS_FLAG + 0x6400)\n+\n+/* HW interface registers */\n+#define SPNIC_CSR_FUNC_ATTR0_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x0)\n+#define SPNIC_CSR_FUNC_ATTR1_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x4)\n+#define SPNIC_CSR_FUNC_ATTR2_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x8)\n+#define SPNIC_CSR_FUNC_ATTR3_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0xC)\n+#define SPNIC_CSR_FUNC_ATTR4_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x10)\n+#define SPNIC_CSR_FUNC_ATTR5_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x14)\n+#define SPNIC_CSR_FUNC_ATTR6_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x18)\n+\n+#define SPNIC_FUNC_CSR_MAILBOX_DATA_OFF\t0x80\n+#define SPNIC_FUNC_CSR_MAILBOX_CONTROL_OFF\t(SPNIC_CFG_REGS_FLAG + 0x0100)\n+#define SPNIC_FUNC_CSR_MAILBOX_INT_OFFSET_OFF\t(SPNIC_CFG_REGS_FLAG + 0x0104)\n+#define SPNIC_FUNC_CSR_MAILBOX_RESULT_H_OFF\t(SPNIC_CFG_REGS_FLAG + 0x0108)\n+#define SPNIC_FUNC_CSR_MAILBOX_RESULT_L_OFF\t(SPNIC_CFG_REGS_FLAG + 0x010C)\n+\n+#define SPNIC_PPF_ELECTION_OFFSET\t\t0x0\n+#define SPNIC_MPF_ELECTION_OFFSET\t\t0x20\n+\n+#define SPNIC_CSR_PPF_ELECTION_ADDR\t\t\\\n+\t\t\t(SPNIC_HOST_CSR_BASE_ADDR + SPNIC_PPF_ELECTION_OFFSET)\n+\n+#define SPNIC_CSR_GLOBAL_MPF_ELECTION_ADDR\t\t\\\n+\t\t\t(SPNIC_HOST_CSR_BASE_ADDR + SPNIC_MPF_ELECTION_OFFSET)\n+\n+#define SPNIC_CSR_DMA_ATTR_TBL_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x380)\n+#define SPNIC_CSR_DMA_ATTR_INDIR_IDX_ADDR\t(SPNIC_CFG_REGS_FLAG + 0x390)\n+\n+/* MSI-X registers */\n+#define SPNIC_CSR_MSIX_INDIR_IDX_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x310)\n+#define SPNIC_CSR_MSIX_CTRL_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x300)\n+#define SPNIC_CSR_MSIX_CNT_ADDR\t\t (SPNIC_CFG_REGS_FLAG + 0x304)\n+#define SPNIC_CSR_FUNC_MSI_CLR_WR_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x58)\n+\n+#define SPNIC_MSI_CLR_INDIR_RESEND_TIMER_CLR_SHIFT\t0\n+#define SPNIC_MSI_CLR_INDIR_INT_MSK_SET_SHIFT\t\t1\n+#define SPNIC_MSI_CLR_INDIR_INT_MSK_CLR_SHIFT\t\t2\n+#define SPNIC_MSI_CLR_INDIR_AUTO_MSK_SET_SHIFT\t\t3\n+#define SPNIC_MSI_CLR_INDIR_AUTO_MSK_CLR_SHIFT\t\t4\n+#define SPNIC_MSI_CLR_INDIR_SIMPLE_INDIR_IDX_SHIFT\t22\n+\n+#define SPNIC_MSI_CLR_INDIR_RESEND_TIMER_CLR_MASK\t0x1U\n+#define SPNIC_MSI_CLR_INDIR_INT_MSK_SET_MASK\t\t0x1U\n+#define SPNIC_MSI_CLR_INDIR_INT_MSK_CLR_MASK\t\t0x1U\n+#define SPNIC_MSI_CLR_INDIR_AUTO_MSK_SET_MASK\t\t0x1U\n+#define SPNIC_MSI_CLR_INDIR_AUTO_MSK_CLR_MASK\t\t0x1U\n+#define SPNIC_MSI_CLR_INDIR_SIMPLE_INDIR_IDX_MASK\t0x3FFU\n+\n+#define SPNIC_MSI_CLR_INDIR_SET(val, member)\t\t\\\n+\t\t(((val) & SPNIC_MSI_CLR_INDIR_##member##_MASK) << \\\n+\t\tSPNIC_MSI_CLR_INDIR_##member##_SHIFT)\n+\n+/* EQ registers */\n+#define SPNIC_AEQ_INDIR_IDX_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x210)\n+\n+#define SPNIC_AEQ_MTT_OFF_BASE_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x240)\n+\n+#define SPNIC_CSR_EQ_PAGE_OFF_STRIDE\t\t\t8\n+\n+#define SPNIC_AEQ_HI_PHYS_ADDR_REG(pg_num)\t\\\n+\t\t(SPNIC_AEQ_MTT_OFF_BASE_ADDR + \\\n+\t\t(pg_num) * SPNIC_CSR_EQ_PAGE_OFF_STRIDE)\n+\n+#define SPNIC_AEQ_LO_PHYS_ADDR_REG(pg_num)\t\\\n+\t\t(SPNIC_AEQ_MTT_OFF_BASE_ADDR + \\\n+\t\t(pg_num) * SPNIC_CSR_EQ_PAGE_OFF_STRIDE + 4)\n+\n+#define SPNIC_CSR_AEQ_CTRL_0_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x200)\n+#define SPNIC_CSR_AEQ_CTRL_1_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x204)\n+#define SPNIC_CSR_AEQ_CONS_IDX_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x208)\n+#define SPNIC_CSR_AEQ_PROD_IDX_ADDR\t\t(SPNIC_CFG_REGS_FLAG + 0x20C)\n+#define SPNIC_CSR_AEQ_CI_SIMPLE_INDIR_ADDR\t(SPNIC_CFG_REGS_FLAG + 0x50)\n+\n+#endif /* _SPNIC_CSR_H_ */\ndiff --git a/drivers/net/spnic/base/spnic_hwdev.c b/drivers/net/spnic/base/spnic_hwdev.c\nnew file mode 100644\nindex 0000000000..de73f244fd\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_hwdev.c\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#include \"spnic_compat.h\"\n+#include \"spnic_csr.h\"\n+#include \"spnic_hwif.h\"\n+#include \"spnic_hwdev.h\"\n+\n+int spnic_init_hwdev(struct spnic_hwdev *hwdev)\n+{\n+\tint err;\n+\n+\thwdev->chip_fault_stats = rte_zmalloc(\"chip_fault_stats\",\n+\t\t\t\t\t SPNIC_CHIP_FAULT_SIZE,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!hwdev->chip_fault_stats) {\n+\t\tPMD_DRV_LOG(ERR, \"Alloc memory for chip_fault_stats failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\terr = spnic_init_hwif(hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize hwif failed\");\n+\t\tgoto init_hwif_err;\n+\t}\n+\n+\treturn 0;\n+\n+init_hwif_err:\n+\trte_free(hwdev->chip_fault_stats);\n+\n+\treturn -EFAULT;\n+}\n+\n+void spnic_free_hwdev(struct spnic_hwdev *hwdev)\n+{\n+\tspnic_free_hwif(hwdev);\n+\n+\trte_free(hwdev->chip_fault_stats);\n+}\ndiff --git a/drivers/net/spnic/base/spnic_hwdev.h b/drivers/net/spnic/base/spnic_hwdev.h\nnew file mode 100644\nindex 0000000000..a6cb8bc36e\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_hwdev.h\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#ifndef _SPNIC_HWDEV_H_\n+#define _SPNIC_HWDEV_H_\n+\n+#include <rte_ether.h>\n+\n+#define SPNIC_CHIP_FAULT_SIZE\t\t(110 * 1024)\n+\n+struct spnic_hwdev {\n+\tvoid *dev_handle; /* Pointer to spnic_nic_dev */\n+\tvoid *pci_dev; /* Pointer to rte_pci_device */\n+\tvoid *eth_dev; /* Pointer to rte_eth_dev */\n+\n+\tuint16_t port_id;\n+\n+\tstruct spnic_hwif *hwif;\n+\tu8 *chip_fault_stats;\n+\n+\tu16 max_vfs;\n+\tu16 link_status;\n+};\n+\n+int spnic_init_hwdev(struct spnic_hwdev *hwdev);\n+\n+void spnic_free_hwdev(struct spnic_hwdev *hwdev);\n+#endif /* _SPNIC_HWDEV_H_ */\ndiff --git a/drivers/net/spnic/base/spnic_hwif.c b/drivers/net/spnic/base/spnic_hwif.c\nnew file mode 100644\nindex 0000000000..9daaa7abd9\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_hwif.c\n@@ -0,0 +1,774 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#include <rte_bus_pci.h>\n+#include \"spnic_compat.h\"\n+#include \"spnic_csr.h\"\n+#include \"spnic_hwdev.h\"\n+#include \"spnic_hwif.h\"\n+\n+#define WAIT_HWIF_READY_TIMEOUT\t\t\t10000\n+\n+#define DB_IDX(db, db_base)\t\\\n+\t((u32)(((ulong)(db) - (ulong)(db_base)) /\t\\\n+\tSPNIC_DB_PAGE_SIZE))\n+\n+#define SPNIC_AF0_FUNC_GLOBAL_IDX_SHIFT\t\t0\n+#define SPNIC_AF0_P2P_IDX_SHIFT\t\t\t12\n+#define SPNIC_AF0_PCI_INTF_IDX_SHIFT\t\t17\n+#define SPNIC_AF0_VF_IN_PF_SHIFT\t\t20\n+#define SPNIC_AF0_FUNC_TYPE_SHIFT\t\t28\n+\n+#define SPNIC_AF0_FUNC_GLOBAL_IDX_MASK\t\t0xFFF\n+#define SPNIC_AF0_P2P_IDX_MASK\t\t\t0x1F\n+#define SPNIC_AF0_PCI_INTF_IDX_MASK\t\t0x7\n+#define SPNIC_AF0_VF_IN_PF_MASK\t\t\t0xFF\n+#define SPNIC_AF0_FUNC_TYPE_MASK\t\t0x1\n+\n+#define SPNIC_AF0_GET(val, member)\t\t\t\t\\\n+\t(((val) >> SPNIC_AF0_##member##_SHIFT) & SPNIC_AF0_##member##_MASK)\n+\n+#define SPNIC_AF1_PPF_IDX_SHIFT\t\t\t0\n+#define SPNIC_AF1_AEQS_PER_FUNC_SHIFT\t\t8\n+#define SPNIC_AF1_MGMT_INIT_STATUS_SHIFT\t30\n+#define SPNIC_AF1_PF_INIT_STATUS_SHIFT\t\t31\n+\n+#define SPNIC_AF1_PPF_IDX_MASK\t\t\t0x3F\n+#define SPNIC_AF1_AEQS_PER_FUNC_MASK\t\t0x3\n+#define SPNIC_AF1_MGMT_INIT_STATUS_MASK\t\t0x1\n+#define SPNIC_AF1_PF_INIT_STATUS_MASK\t\t0x1\n+\n+#define SPNIC_AF1_GET(val, member)\t\t\t\t\\\n+\t(((val) >> SPNIC_AF1_##member##_SHIFT) & SPNIC_AF1_##member##_MASK)\n+\n+#define SPNIC_AF2_CEQS_PER_FUNC_SHIFT\t\t0\n+#define SPNIC_AF2_DMA_ATTR_PER_FUNC_SHIFT\t9\n+#define SPNIC_AF2_IRQS_PER_FUNC_SHIFT\t\t16\n+\n+#define SPNIC_AF2_CEQS_PER_FUNC_MASK\t\t0x1FF\n+#define SPNIC_AF2_DMA_ATTR_PER_FUNC_MASK\t0x7\n+#define SPNIC_AF2_IRQS_PER_FUNC_MASK\t\t0x7FF\n+\n+#define SPNIC_AF2_GET(val, member)\t\t\t\t\\\n+\t(((val) >> SPNIC_AF2_##member##_SHIFT) & SPNIC_AF2_##member##_MASK)\n+\n+#define SPNIC_AF3_GLOBAL_VF_ID_OF_NXT_PF_SHIFT\t0\n+#define SPNIC_AF3_GLOBAL_VF_ID_OF_PF_SHIFT\t16\n+\n+#define SPNIC_AF3_GLOBAL_VF_ID_OF_NXT_PF_MASK\t0xFFF\n+#define SPNIC_AF3_GLOBAL_VF_ID_OF_PF_MASK\t0xFFF\n+\n+#define SPNIC_AF3_GET(val, member)\t\t\t\t\\\n+\t(((val) >> SPNIC_AF3_##member##_SHIFT) & SPNIC_AF3_##member##_MASK)\n+\n+#define SPNIC_AF4_DOORBELL_CTRL_SHIFT\t\t0\n+#define SPNIC_AF4_DOORBELL_CTRL_MASK\t\t0x1\n+\n+#define SPNIC_AF4_GET(val, member)\t\t\t\t\\\n+\t(((val) >> SPNIC_AF4_##member##_SHIFT) & SPNIC_AF4_##member##_MASK)\n+\n+#define SPNIC_AF4_SET(val, member)\t\t\t\t\\\n+\t(((val) & SPNIC_AF4_##member##_MASK) << SPNIC_AF4_##member##_SHIFT)\n+\n+#define SPNIC_AF4_CLEAR(val, member)\t\t\t\t\\\n+\t((val) & (~(SPNIC_AF4_##member##_MASK <<\t\t\\\n+\tSPNIC_AF4_##member##_SHIFT)))\n+\n+#define SPNIC_AF5_OUTBOUND_CTRL_SHIFT\t\t0\n+#define SPNIC_AF5_OUTBOUND_CTRL_MASK\t\t0x1\n+\n+#define SPNIC_AF5_GET(val, member)\t\t\t\t\\\n+\t(((val) >> SPNIC_AF5_##member##_SHIFT) & SPNIC_AF5_##member##_MASK)\n+\n+#define SPNIC_AF5_SET(val, member)\t\t\t\t\\\n+\t(((val) & SPNIC_AF5_##member##_MASK) << SPNIC_AF5_##member##_SHIFT)\n+\n+#define SPNIC_AF5_CLEAR(val, member)\t\t\t\t\\\n+\t((val) & (~(SPNIC_AF5_##member##_MASK <<\t\t\\\n+\tSPNIC_AF5_##member##_SHIFT)))\n+\n+#define SPNIC_AF6_PF_STATUS_SHIFT\t\t0\n+#define SPNIC_AF6_PF_STATUS_MASK\t\t0xFFFF\n+\n+#define SPNIC_AF6_SET(val, member)\t\t\t\t\\\n+\t((((u32)(val)) & SPNIC_AF6_##member##_MASK) <<\t\t\\\n+\tSPNIC_AF6_##member##_SHIFT)\n+\n+#define SPNIC_AF6_GET(val, member)\t\t\t\t\\\n+\t(((val) >> SPNIC_AF6_##member##_SHIFT) & SPNIC_AF6_##member##_MASK)\n+\n+#define SPNIC_AF6_CLEAR(val, member)\t\t\t\t\\\n+\t((val) & (~(SPNIC_AF6_##member##_MASK <<\t\t\\\n+\tSPNIC_AF6_##member##_SHIFT)))\n+\n+#define SPNIC_PPF_ELECTION_IDX_SHIFT\t\t0\n+\n+#define SPNIC_PPF_ELECTION_IDX_MASK\t\t0x3F\n+\n+#define SPNIC_PPF_ELECTION_SET(val, member)\t\t\t\\\n+\t(((val) & SPNIC_PPF_ELECTION_##member##_MASK) <<\t\\\n+\t\tSPNIC_PPF_ELECTION_##member##_SHIFT)\n+\n+#define SPNIC_PPF_ELECTION_GET(val, member)\t\t\t\\\n+\t(((val) >> SPNIC_PPF_ELECTION_##member##_SHIFT) &\t\\\n+\t\tSPNIC_PPF_ELECTION_##member##_MASK)\n+\n+#define SPNIC_PPF_ELECTION_CLEAR(val, member)\t\t\t\\\n+\t((val) & (~(SPNIC_PPF_ELECTION_##member##_MASK\t\\\n+\t\t<< SPNIC_PPF_ELECTION_##member##_SHIFT)))\n+\n+#define SPNIC_MPF_ELECTION_IDX_SHIFT\t\t0\n+\n+#define SPNIC_MPF_ELECTION_IDX_MASK\t\t0x1F\n+\n+#define SPNIC_MPF_ELECTION_SET(val, member)\t\t\t\\\n+\t(((val) & SPNIC_MPF_ELECTION_##member##_MASK) <<\t\\\n+\t\tSPNIC_MPF_ELECTION_##member##_SHIFT)\n+\n+#define SPNIC_MPF_ELECTION_GET(val, member)\t\t\t\\\n+\t(((val) >> SPNIC_MPF_ELECTION_##member##_SHIFT) &\t\\\n+\t\tSPNIC_MPF_ELECTION_##member##_MASK)\n+\n+#define SPNIC_MPF_ELECTION_CLEAR(val, member)\t\t\t\\\n+\t((val) & (~(SPNIC_MPF_ELECTION_##member##_MASK\t\\\n+\t\t<< SPNIC_MPF_ELECTION_##member##_SHIFT)))\n+\n+#define SPNIC_GET_REG_FLAG(reg)\t((reg) & (~(SPNIC_REGS_FLAG_MAKS)))\n+\n+#define SPNIC_GET_REG_ADDR(reg)\t((reg) & (SPNIC_REGS_FLAG_MAKS))\n+\n+#define SPNIC_IS_VF_DEV(pdev)\t((pdev)->id.device_id == SPNIC_DEV_ID_VF)\n+\n+u32 spnic_hwif_read_reg(struct spnic_hwif *hwif, u32 reg)\n+{\n+\tif (SPNIC_GET_REG_FLAG(reg) == SPNIC_MGMT_REGS_FLAG)\n+\t\treturn be32_to_cpu(rte_read32(hwif->mgmt_regs_base +\n+\t\t\t\t SPNIC_GET_REG_ADDR(reg)));\n+\telse\n+\t\treturn be32_to_cpu(rte_read32(hwif->cfg_regs_base +\n+\t\t\t\t SPNIC_GET_REG_ADDR(reg)));\n+}\n+\n+void spnic_hwif_write_reg(struct spnic_hwif *hwif, u32 reg, u32 val)\n+{\n+\tif (SPNIC_GET_REG_FLAG(reg) == SPNIC_MGMT_REGS_FLAG)\n+\t\trte_write32(cpu_to_be32(val),\n+\t\t hwif->mgmt_regs_base + SPNIC_GET_REG_ADDR(reg));\n+\telse\n+\t\trte_write32(cpu_to_be32(val),\n+\t\t hwif->cfg_regs_base + SPNIC_GET_REG_ADDR(reg));\n+}\n+\n+/**\n+ * Judge whether HW initialization ok\n+ *\n+ * @param[in] hwdev\n+ * The pointer to the private hardware device object\n+ *\n+ * @retval zero: Success\n+ * @retval negative: Failure\n+ */\n+static int hwif_ready(struct spnic_hwdev *hwdev)\n+{\n+\tu32 addr, attr1;\n+\n+\taddr = SPNIC_CSR_FUNC_ATTR1_ADDR;\n+\tattr1 = spnic_hwif_read_reg(hwdev->hwif, addr);\n+\tif (attr1 == SPNIC_PCIE_LINK_DOWN)\n+\t\treturn -EBUSY;\n+\n+\tif (!SPNIC_AF1_GET(attr1, MGMT_INIT_STATUS))\n+\t\treturn -EBUSY;\n+\n+\treturn 0;\n+}\n+\n+static int wait_hwif_ready(struct spnic_hwdev *hwdev)\n+{\n+\tulong timeout = 0;\n+\n+\tdo {\n+\t\tif (!hwif_ready(hwdev))\n+\t\t\treturn 0;\n+\n+\t\trte_delay_ms(1);\n+\t\ttimeout++;\n+\t} while (timeout <= WAIT_HWIF_READY_TIMEOUT);\n+\n+\tPMD_DRV_LOG(ERR, \"Hwif is not ready\");\n+\treturn -EBUSY;\n+}\n+\n+/**\n+ * Set the attributes as members in hwif\n+ *\n+ * @param[in] hwif\n+ * The hardware interface of a pci function device\n+ * @param[in] attr0\n+ * The first attribute that was read from the hw\n+ * @param[in] attr1\n+ * The second attribute that was read from the hw\n+ * @param[in] attr2\n+ * The third attribute that was read from the hw\n+ * @param[in] attr3\n+ * The fourth attribute that was read from the hw\n+ */\n+static void set_hwif_attr(struct spnic_hwif *hwif, u32 attr0, u32 attr1,\n+\t\t\t u32 attr2, u32 attr3)\n+{\n+\thwif->attr.func_global_idx = SPNIC_AF0_GET(attr0, FUNC_GLOBAL_IDX);\n+\thwif->attr.port_to_port_idx = SPNIC_AF0_GET(attr0, P2P_IDX);\n+\thwif->attr.pci_intf_idx = SPNIC_AF0_GET(attr0, PCI_INTF_IDX);\n+\thwif->attr.vf_in_pf = SPNIC_AF0_GET(attr0, VF_IN_PF);\n+\thwif->attr.func_type = SPNIC_AF0_GET(attr0, FUNC_TYPE);\n+\n+\thwif->attr.ppf_idx = SPNIC_AF1_GET(attr1, PPF_IDX);\n+\thwif->attr.num_aeqs = BIT(SPNIC_AF1_GET(attr1, AEQS_PER_FUNC));\n+\n+\thwif->attr.num_ceqs = (u8)SPNIC_AF2_GET(attr2, CEQS_PER_FUNC);\n+\thwif->attr.num_irqs = SPNIC_AF2_GET(attr2, IRQS_PER_FUNC);\n+\thwif->attr.num_dma_attr = BIT(SPNIC_AF2_GET(attr2, DMA_ATTR_PER_FUNC));\n+\n+\thwif->attr.global_vf_id_of_pf = SPNIC_AF3_GET(attr3,\n+\t\t\t\t\t\t GLOBAL_VF_ID_OF_PF);\n+}\n+\n+/**\n+ * Read and set the attributes as members in hwif\n+ *\n+ * @param[in] hwif\n+ * The hardware interface of a pci function device\n+ */\n+static void get_hwif_attr(struct spnic_hwif *hwif)\n+{\n+\tu32 addr, attr0, attr1, attr2, attr3;\n+\n+\taddr = SPNIC_CSR_FUNC_ATTR0_ADDR;\n+\tattr0 = spnic_hwif_read_reg(hwif, addr);\n+\n+\taddr = SPNIC_CSR_FUNC_ATTR1_ADDR;\n+\tattr1 = spnic_hwif_read_reg(hwif, addr);\n+\n+\taddr = SPNIC_CSR_FUNC_ATTR2_ADDR;\n+\tattr2 = spnic_hwif_read_reg(hwif, addr);\n+\n+\taddr = SPNIC_CSR_FUNC_ATTR3_ADDR;\n+\tattr3 = spnic_hwif_read_reg(hwif, addr);\n+\n+\tset_hwif_attr(hwif, attr0, attr1, attr2, attr3);\n+}\n+\n+void spnic_set_pf_status(struct spnic_hwif *hwif, enum spnic_pf_status status)\n+{\n+\tu32 attr6 = SPNIC_AF6_SET(status, PF_STATUS);\n+\tu32 addr = SPNIC_CSR_FUNC_ATTR6_ADDR;\n+\n+\tif (hwif->attr.func_type == TYPE_VF)\n+\t\treturn;\n+\n+\tspnic_hwif_write_reg(hwif, addr, attr6);\n+}\n+\n+enum spnic_pf_status spnic_get_pf_status(struct spnic_hwif *hwif)\n+{\n+\tu32 attr6 = spnic_hwif_read_reg(hwif, SPNIC_CSR_FUNC_ATTR6_ADDR);\n+\n+\treturn SPNIC_AF6_GET(attr6, PF_STATUS);\n+}\n+\n+static enum spnic_doorbell_ctrl\n+spnic_get_doorbell_ctrl_status(struct spnic_hwif *hwif)\n+{\n+\tu32 attr4 = spnic_hwif_read_reg(hwif, SPNIC_CSR_FUNC_ATTR4_ADDR);\n+\n+\treturn SPNIC_AF4_GET(attr4, DOORBELL_CTRL);\n+}\n+\n+static enum spnic_outbound_ctrl\n+spnic_get_outbound_ctrl_status(struct spnic_hwif *hwif)\n+{\n+\tu32 attr5 = spnic_hwif_read_reg(hwif, SPNIC_CSR_FUNC_ATTR5_ADDR);\n+\n+\treturn SPNIC_AF5_GET(attr5, OUTBOUND_CTRL);\n+}\n+\n+void spnic_enable_doorbell(struct spnic_hwif *hwif)\n+{\n+\tu32 addr, attr4;\n+\n+\taddr = SPNIC_CSR_FUNC_ATTR4_ADDR;\n+\tattr4 = spnic_hwif_read_reg(hwif, addr);\n+\n+\tattr4 = SPNIC_AF4_CLEAR(attr4, DOORBELL_CTRL);\n+\tattr4 |= SPNIC_AF4_SET(ENABLE_DOORBELL, DOORBELL_CTRL);\n+\n+\tspnic_hwif_write_reg(hwif, addr, attr4);\n+}\n+\n+void spnic_disable_doorbell(struct spnic_hwif *hwif)\n+{\n+\tu32 addr, attr4;\n+\n+\taddr = SPNIC_CSR_FUNC_ATTR4_ADDR;\n+\tattr4 = spnic_hwif_read_reg(hwif, addr);\n+\n+\tattr4 = SPNIC_AF4_CLEAR(attr4, DOORBELL_CTRL);\n+\tattr4 |= SPNIC_AF4_SET(DISABLE_DOORBELL, DOORBELL_CTRL);\n+\n+\tspnic_hwif_write_reg(hwif, addr, attr4);\n+}\n+\n+/**\n+ * Try to set hwif as ppf and set the type of hwif in this case\n+ *\n+ * @param[in] hwif\n+ * The hardware interface of a pci function device\n+ */\n+static void set_ppf(struct spnic_hwif *hwif)\n+{\n+\tstruct spnic_func_attr *attr = &hwif->attr;\n+\tu32 addr, val, ppf_election;\n+\n+\taddr = SPNIC_CSR_PPF_ELECTION_ADDR;\n+\n+\tval = spnic_hwif_read_reg(hwif, addr);\n+\tval = SPNIC_PPF_ELECTION_CLEAR(val, IDX);\n+\n+\tppf_election = SPNIC_PPF_ELECTION_SET(attr->func_global_idx, IDX);\n+\tval |= ppf_election;\n+\n+\tspnic_hwif_write_reg(hwif, addr, val);\n+\n+\t/* Check PPF */\n+\tval = spnic_hwif_read_reg(hwif, addr);\n+\n+\tattr->ppf_idx = SPNIC_PPF_ELECTION_GET(val, IDX);\n+\tif (attr->ppf_idx == attr->func_global_idx)\n+\t\tattr->func_type = TYPE_PPF;\n+}\n+\n+/**\n+ * Get the mpf index from the hwif\n+ *\n+ * @param[in] hwif\n+ * The hardware interface of a pci function device\n+ */\n+static void get_mpf(struct spnic_hwif *hwif)\n+{\n+\tstruct spnic_func_attr *attr = &hwif->attr;\n+\tu32 mpf_election, addr;\n+\n+\taddr = SPNIC_CSR_GLOBAL_MPF_ELECTION_ADDR;\n+\n+\tmpf_election = spnic_hwif_read_reg(hwif, addr);\n+\tattr->mpf_idx = SPNIC_MPF_ELECTION_GET(mpf_election, IDX);\n+}\n+\n+/**\n+ * Try to set hwif as mpf and set the mpf idx in hwif\n+ *\n+ * @param[in] hwif\n+ * The hardware interface of a pci function device\n+ */\n+static void set_mpf(struct spnic_hwif *hwif)\n+{\n+\tstruct spnic_func_attr *attr = &hwif->attr;\n+\tu32 addr, val, mpf_election;\n+\n+\taddr = SPNIC_CSR_GLOBAL_MPF_ELECTION_ADDR;\n+\n+\tval = spnic_hwif_read_reg(hwif, addr);\n+\n+\tval = SPNIC_MPF_ELECTION_CLEAR(val, IDX);\n+\tmpf_election = SPNIC_MPF_ELECTION_SET(attr->func_global_idx, IDX);\n+\n+\tval |= mpf_election;\n+\tspnic_hwif_write_reg(hwif, addr, val);\n+}\n+\n+static void init_db_area_idx(struct spnic_free_db_area *free_db_area,\n+\t\t\t u64 db_dwqe_len)\n+{\n+\tu32 i, db_max_areas;\n+\n+\tdb_max_areas = (db_dwqe_len > SPNIC_DB_DWQE_SIZE) ?\n+\t\t SPNIC_DB_MAX_AREAS :\n+\t\t (u32)(db_dwqe_len / SPNIC_DB_PAGE_SIZE);\n+\n+\tfor (i = 0; i < db_max_areas; i++)\n+\t\tfree_db_area->db_idx[i] = i;\n+\n+\tfree_db_area->num_free = db_max_areas;\n+\tfree_db_area->db_max_areas = db_max_areas;\n+\n+\trte_spinlock_init(&free_db_area->idx_lock);\n+}\n+\n+static int get_db_idx(struct spnic_hwif *hwif, u32 *idx)\n+{\n+\tstruct spnic_free_db_area *free_db_area = &hwif->free_db_area;\n+\tu32 pos;\n+\tu32 pg_idx;\n+\n+\trte_spinlock_lock(&free_db_area->idx_lock);\n+\n+\tdo {\n+\t\tif (free_db_area->num_free == 0) {\n+\t\t\trte_spinlock_unlock(&free_db_area->idx_lock);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tfree_db_area->num_free--;\n+\n+\t\tpos = free_db_area->alloc_pos++;\n+\t\t/* Doorbell max areas should be 2^n */\n+\t\tpos &= free_db_area->db_max_areas - 1;\n+\n+\t\tpg_idx = free_db_area->db_idx[pos];\n+\n+\t\tfree_db_area->db_idx[pos] = 0xFFFFFFFF;\n+\t} while (pg_idx >= free_db_area->db_max_areas);\n+\n+\trte_spinlock_unlock(&free_db_area->idx_lock);\n+\n+\t*idx = pg_idx;\n+\n+\treturn 0;\n+}\n+\n+static void free_db_idx(struct spnic_hwif *hwif, u32 idx)\n+{\n+\tstruct spnic_free_db_area *free_db_area = &hwif->free_db_area;\n+\tu32 pos;\n+\n+\tif (idx >= free_db_area->db_max_areas)\n+\t\treturn;\n+\n+\trte_spinlock_lock(&free_db_area->idx_lock);\n+\n+\tpos = free_db_area->return_pos++;\n+\tpos &= free_db_area->db_max_areas - 1;\n+\n+\tfree_db_area->db_idx[pos] = idx;\n+\n+\tfree_db_area->num_free++;\n+\n+\trte_spinlock_unlock(&free_db_area->idx_lock);\n+}\n+\n+void spnic_free_db_addr(void *hwdev, const void *db_base,\n+\t\t\t __rte_unused void *dwqe_base)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\tu32 idx;\n+\n+\tif (!hwdev || !db_base)\n+\t\treturn;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\tidx = DB_IDX(db_base, hwif->db_base);\n+\n+\tfree_db_idx(hwif, idx);\n+}\n+\n+int spnic_alloc_db_addr(void *hwdev, void **db_base, void **dwqe_base)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\tu32 idx;\n+\tint err;\n+\n+\tif (!hwdev || !db_base)\n+\t\treturn -EINVAL;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\n+\terr = get_db_idx(hwif, &idx);\n+\tif (err)\n+\t\treturn -EFAULT;\n+\n+\t*db_base = hwif->db_base + idx * SPNIC_DB_PAGE_SIZE;\n+\n+\tif (!dwqe_base)\n+\t\treturn 0;\n+\n+\t*dwqe_base = (u8 *)*db_base + SPNIC_DWQE_OFFSET;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Set msix state\n+ *\n+ * @param[in] hwdev\n+ * The pointer to the private hardware device object\n+ * @param[in] msix_idx\n+ * MSIX index\n+ * @param[in] flag\n+ * MSIX state flag, 0-enable, 1-disable\n+ */\n+void spnic_set_msix_state(void *hwdev, u16 msix_idx, enum spnic_msix_state flag)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\tu32 mask_bits;\n+\tu32 addr;\n+\tu8 int_msk = 1;\n+\n+\tif (!hwdev)\n+\t\treturn;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\n+\tif (flag)\n+\t\tmask_bits = SPNIC_MSI_CLR_INDIR_SET(int_msk, INT_MSK_SET);\n+\telse\n+\t\tmask_bits = SPNIC_MSI_CLR_INDIR_SET(int_msk, INT_MSK_CLR);\n+\tmask_bits = mask_bits |\n+\t\t SPNIC_MSI_CLR_INDIR_SET(msix_idx, SIMPLE_INDIR_IDX);\n+\n+\taddr = SPNIC_CSR_FUNC_MSI_CLR_WR_ADDR;\n+\tspnic_hwif_write_reg(hwif, addr, mask_bits);\n+}\n+\n+static void disable_all_msix(struct spnic_hwdev *hwdev)\n+{\n+\tu16 num_irqs = hwdev->hwif->attr.num_irqs;\n+\tu16 i;\n+\n+\tfor (i = 0; i < num_irqs; i++)\n+\t\tspnic_set_msix_state(hwdev, i, SPNIC_MSIX_DISABLE);\n+}\n+\n+void spnic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx,\n+\t\t\t\t\t u8 clear_resend_en)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\tu32 msix_ctrl = 0, addr;\n+\n+\tif (!hwdev)\n+\t\treturn;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\n+\tmsix_ctrl = SPNIC_MSI_CLR_INDIR_SET(msix_idx, SIMPLE_INDIR_IDX) |\n+\t\t SPNIC_MSI_CLR_INDIR_SET(clear_resend_en, RESEND_TIMER_CLR);\n+\n+\taddr = SPNIC_CSR_FUNC_MSI_CLR_WR_ADDR;\n+\tspnic_hwif_write_reg(hwif, addr, msix_ctrl);\n+}\n+#ifdef SPNIC_RELEASE\n+static int wait_until_doorbell_flush_states(struct spnic_hwif *hwif,\n+\t\t\t\t\t enum spnic_doorbell_ctrl states)\n+{\n+\tenum spnic_doorbell_ctrl db_ctrl;\n+\tu32 cnt = 0;\n+\n+\tif (!hwif)\n+\t\treturn -EINVAL;\n+\n+\twhile (cnt < SPNIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT) {\n+\t\tdb_ctrl = spnic_get_doorbell_ctrl_status(hwif);\n+\t\tif (db_ctrl == states)\n+\t\t\treturn 0;\n+\n+\t\trte_delay_ms(1);\n+\t\tcnt++;\n+\t}\n+\n+\treturn -EFAULT;\n+}\n+#endif\n+\n+static int wait_until_doorbell_and_outbound_enabled(struct spnic_hwif *hwif)\n+{\n+\tenum spnic_doorbell_ctrl db_ctrl;\n+\tenum spnic_outbound_ctrl outbound_ctrl;\n+\tu32 cnt = 0;\n+\n+\twhile (cnt < SPNIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT) {\n+\t\tdb_ctrl = spnic_get_doorbell_ctrl_status(hwif);\n+\t\toutbound_ctrl = spnic_get_outbound_ctrl_status(hwif);\n+\t\tif (outbound_ctrl == ENABLE_OUTBOUND &&\n+\t\t db_ctrl == ENABLE_DOORBELL)\n+\t\t\treturn 0;\n+\n+\t\trte_delay_ms(1);\n+\t\tcnt++;\n+\t}\n+\n+\treturn -EFAULT;\n+}\n+\n+static void spnic_get_bar_addr(struct spnic_hwdev *hwdev)\n+{\n+\tstruct rte_pci_device *pci_dev = hwdev->pci_dev;\n+\tstruct spnic_hwif *hwif = hwdev->hwif;\n+\tvoid *cfg_regs_base = NULL;\n+\tvoid *mgmt_reg_base = NULL;\n+\tvoid *intr_reg_base = NULL;\n+\tvoid *db_base = NULL;\n+\tint cfg_bar;\n+\n+\tcfg_bar = SPNIC_IS_VF_DEV(pci_dev) ?\n+\t\t\tSPNIC_VF_PCI_CFG_REG_BAR : SPNIC_PF_PCI_CFG_REG_BAR;\n+\n+\tcfg_regs_base = pci_dev->mem_resource[cfg_bar].addr;\n+\tintr_reg_base = pci_dev->mem_resource[SPNIC_PCI_INTR_REG_BAR].addr;\n+\tif (!SPNIC_IS_VF_DEV(pci_dev)) {\n+\t\tmgmt_reg_base =\n+\t\t\tpci_dev->mem_resource[SPNIC_PCI_MGMT_REG_BAR].addr;\n+\t}\n+\tdb_base = pci_dev->mem_resource[SPNIC_PCI_DB_BAR].addr;\n+\n+\t/* If function is VF, mgmt_regs_base will be NULL */\n+\tif (!mgmt_reg_base)\n+\t\thwif->cfg_regs_base = (u8 *)cfg_regs_base +\n+\t\t\t\t SPNIC_VF_CFG_REG_OFFSET;\n+\telse\n+\t\thwif->cfg_regs_base = cfg_regs_base;\n+\thwif->intr_regs_base = intr_reg_base;\n+\thwif->mgmt_regs_base = mgmt_reg_base;\n+\thwif->db_base = db_base;\n+\thwif->db_dwqe_len = pci_dev->mem_resource[SPNIC_PCI_DB_BAR].len;\n+}\n+\n+/**\n+ * Initialize the hw interface\n+ *\n+ * @param[in] hwdev\n+ * The pointer to the private hardware device object\n+ *\n+ * @retval zero : Success\n+ * @retval non-zero : Failure.\n+ */\n+int spnic_init_hwif(void *dev)\n+{\n+\tstruct spnic_hwdev *hwdev = NULL;\n+\tstruct spnic_hwif *hwif;\n+\tint err;\n+\n+\thwif = rte_zmalloc(\"spnic_hwif\", sizeof(struct spnic_hwif),\n+\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!hwif)\n+\t\treturn -ENOMEM;\n+\n+\thwdev = (struct spnic_hwdev *)dev;\n+\thwdev->hwif = hwif;\n+\n+\tspnic_get_bar_addr(hwdev);\n+\n+\tinit_db_area_idx(&hwif->free_db_area, hwif->db_dwqe_len);\n+\n+\terr = wait_hwif_ready(hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Chip status is not ready\");\n+\t\tgoto hwif_ready_err;\n+\t}\n+\n+\tget_hwif_attr(hwif);\n+\n+\terr = wait_until_doorbell_and_outbound_enabled(hwif);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Hw doorbell/outbound is disabled\");\n+\t\tgoto hwif_ready_err;\n+\t}\n+\n+\tif (!SPNIC_IS_VF(hwdev)) {\n+\t\tset_ppf(hwif);\n+\n+\t\tif (SPNIC_IS_PPF(hwdev))\n+\t\t\tset_mpf(hwif);\n+\n+\t\tget_mpf(hwif);\n+\t}\n+\n+\tdisable_all_msix(hwdev);\n+\t/* Disable mgmt cpu reporting any event */\n+\tspnic_set_pf_status(hwdev->hwif, SPNIC_PF_STATUS_INIT);\n+\n+\tPMD_DRV_LOG(INFO, \"global_func_idx: %d, func_type: %d, host_id: %d, ppf: %d, mpf: %d\",\n+\t\t hwif->attr.func_global_idx, hwif->attr.func_type,\n+\t\t hwif->attr.pci_intf_idx, hwif->attr.ppf_idx,\n+\t\t hwif->attr.mpf_idx);\n+\n+\treturn 0;\n+\n+hwif_ready_err:\n+\trte_free(hwdev->hwif);\n+\thwdev->hwif = NULL;\n+\n+\treturn err;\n+}\n+\n+/**\n+ * Free the hw interface\n+ *\n+ * @param[in] dev\n+ * The pointer to the private hardware device object\n+ */\n+void spnic_free_hwif(void *dev)\n+{\n+\tstruct spnic_hwdev *hwdev = (struct spnic_hwdev *)dev;\n+\n+\trte_free(hwdev->hwif);\n+}\n+\n+u16 spnic_global_func_id(void *hwdev)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\n+\tif (!hwdev)\n+\t\treturn 0;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\n+\treturn hwif->attr.func_global_idx;\n+}\n+\n+u8 spnic_pf_id_of_vf(void *hwdev)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\n+\tif (!hwdev)\n+\t\treturn 0;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\n+\treturn hwif->attr.port_to_port_idx;\n+}\n+\n+u8 spnic_pcie_itf_id(void *hwdev)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\n+\tif (!hwdev)\n+\t\treturn 0;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\n+\treturn hwif->attr.pci_intf_idx;\n+}\n+\n+enum func_type spnic_func_type(void *hwdev)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\n+\tif (!hwdev)\n+\t\treturn 0;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\n+\treturn hwif->attr.func_type;\n+}\n+\n+u16 spnic_glb_pf_vf_offset(void *hwdev)\n+{\n+\tstruct spnic_hwif *hwif = NULL;\n+\n+\tif (!hwdev)\n+\t\treturn 0;\n+\n+\thwif = ((struct spnic_hwdev *)hwdev)->hwif;\n+\n+\treturn hwif->attr.global_vf_id_of_pf;\n+}\ndiff --git a/drivers/net/spnic/base/spnic_hwif.h b/drivers/net/spnic/base/spnic_hwif.h\nnew file mode 100644\nindex 0000000000..6755e1377a\n--- /dev/null\n+++ b/drivers/net/spnic/base/spnic_hwif.h\n@@ -0,0 +1,155 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Ramaxel Memory Technology, Ltd\n+ */\n+\n+#ifndef _SPNIC_HWIF_H_\n+#define _SPNIC_HWIF_H_\n+\n+#define SPNIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT\t60000\n+#define SPNIC_PCIE_LINK_DOWN\t\t0xFFFFFFFF\n+\n+/* PCIe bar space */\n+#define SPNIC_VF_PCI_CFG_REG_BAR\t0\n+#define SPNIC_PF_PCI_CFG_REG_BAR\t1\n+\n+#define SPNIC_PCI_INTR_REG_BAR\t\t2\n+#define SPNIC_PCI_MGMT_REG_BAR\t\t3 /* Only PF has mgmt bar */\n+#define SPNIC_PCI_DB_BAR\t\t4\n+\n+#define SPNIC_DB_DWQE_SIZE\t\t0x00400000\n+\n+/* Doorbell or direct wqe page size is 4K */\n+#define SPNIC_DB_PAGE_SIZE\t\t0x00001000ULL\n+#define SPNIC_DWQE_OFFSET\t\t0x00000800ULL\n+\n+#define SPNIC_DB_MAX_AREAS\t(SPNIC_DB_DWQE_SIZE / SPNIC_DB_PAGE_SIZE)\n+\n+enum func_type {\n+\tTYPE_PF,\n+\tTYPE_VF,\n+\tTYPE_PPF,\n+\tTYPE_UNKNOWN\n+};\n+\n+enum spnic_msix_state {\n+\tSPNIC_MSIX_ENABLE,\n+\tSPNIC_MSIX_DISABLE\n+};\n+\n+struct spnic_free_db_area {\n+\tu32 db_idx[SPNIC_DB_MAX_AREAS];\n+\n+\tu32 num_free;\n+\n+\tu32 alloc_pos;\n+\tu32 return_pos;\n+\tu32 db_max_areas;\n+\n+\t/* Spinlock for allocating doorbell area */\n+\trte_spinlock_t idx_lock;\n+};\n+\n+struct spnic_func_attr {\n+\tu16 func_global_idx;\n+\tu8 port_to_port_idx;\n+\tu8 pci_intf_idx;\n+\tu8 vf_in_pf;\n+\tenum func_type func_type;\n+\n+\tu8 mpf_idx;\n+\n+\tu8 ppf_idx;\n+\n+\tu16 num_irqs; /* Max: 2 ^ 15 */\n+\tu8 num_aeqs; /* Max: 2 ^ 3 */\n+\tu8 num_ceqs; /* Max: 2 ^ 7 */\n+\n+\tu8 num_dma_attr; /* Max: 2 ^ 6 */\n+\n+\tu16 global_vf_id_of_pf;\n+};\n+\n+struct spnic_hwif {\n+\t/* Configure virtual address, PF is bar1, VF is bar0/1 */\n+\tu8 *cfg_regs_base;\n+\t/* Interrupt configuration register address, PF is bar2, VF is bar2/3 */\n+\tu8 *intr_regs_base;\n+\t/* For PF bar3 virtual address, if function is VF should set NULL */\n+\tu8 *mgmt_regs_base;\n+\tu8 *db_base;\n+\tu64 db_dwqe_len;\n+\tstruct spnic_free_db_area free_db_area;\n+\n+\tstruct spnic_func_attr attr;\n+\n+\tvoid *pdev;\n+};\n+\n+enum spnic_outbound_ctrl {\n+\tENABLE_OUTBOUND = 0x0,\n+\tDISABLE_OUTBOUND = 0x1\n+};\n+\n+enum spnic_doorbell_ctrl {\n+\tENABLE_DOORBELL = 0x0,\n+\tDISABLE_DOORBELL = 0x1\n+};\n+\n+enum spnic_pf_status {\n+\tSPNIC_PF_STATUS_INIT = 0X0,\n+\tSPNIC_PF_STATUS_ACTIVE_FLAG = 0x11,\n+\tSPNIC_PF_STATUS_FLR_START_FLAG = 0x12,\n+\tSPNIC_PF_STATUS_FLR_FINISH_FLAG = 0x13\n+};\n+\n+#define SPNIC_HWIF_NUM_AEQS(hwif)\t\t((hwif)->attr.num_aeqs)\n+#define SPNIC_HWIF_NUM_IRQS(hwif)\t\t((hwif)->attr.num_irqs)\n+#define SPNIC_HWIF_GLOBAL_IDX(hwif)\t\t((hwif)->attr.func_global_idx)\n+#define SPNIC_HWIF_GLOBAL_VF_OFFSET(hwif) ((hwif)->attr.global_vf_id_of_pf)\n+#define SPNIC_HWIF_PPF_IDX(hwif)\t\t((hwif)->attr.ppf_idx)\n+#define SPNIC_PCI_INTF_IDX(hwif)\t\t((hwif)->attr.pci_intf_idx)\n+\n+#define SPNIC_FUNC_TYPE(dev)\t\t((dev)->hwif->attr.func_type)\n+#define SPNIC_IS_PF(dev)\t\t(SPNIC_FUNC_TYPE(dev) == TYPE_PF)\n+#define SPNIC_IS_VF(dev)\t\t(SPNIC_FUNC_TYPE(dev) == TYPE_VF)\n+#define SPNIC_IS_PPF(dev)\t\t(SPNIC_FUNC_TYPE(dev) == TYPE_PPF)\n+\n+u32 spnic_hwif_read_reg(struct spnic_hwif *hwif, u32 reg);\n+\n+void spnic_hwif_write_reg(struct spnic_hwif *hwif, u32 reg, u32 val);\n+\n+void spnic_set_msix_state(void *hwdev, u16 msix_idx,\n+\t\t\t enum spnic_msix_state flag);\n+\n+void spnic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx,\n+\t\t\t\t u8 clear_resend_en);\n+\n+u16 spnic_global_func_id(void *hwdev);\n+\n+u8 spnic_pf_id_of_vf(void *hwdev);\n+\n+u8 spnic_pcie_itf_id(void *hwdev);\n+\n+enum func_type spnic_func_type(void *hwdev);\n+\n+u16 spnic_glb_pf_vf_offset(void *hwdev);\n+\n+void spnic_set_pf_status(struct spnic_hwif *hwif,\n+\t\t\t enum spnic_pf_status status);\n+\n+enum spnic_pf_status spnic_get_pf_status(struct spnic_hwif *hwif);\n+\n+int spnic_alloc_db_addr(void *hwdev, void **db_base, void **dwqe_base);\n+\n+void spnic_free_db_addr(void *hwdev, const void *db_base,\n+\t\t\t__rte_unused void *dwqe_base);\n+\n+void spnic_disable_doorbell(struct spnic_hwif *hwif);\n+\n+void spnic_enable_doorbell(struct spnic_hwif *hwif);\n+\n+int spnic_init_hwif(void *dev);\n+\n+void spnic_free_hwif(void *dev);\n+\n+#endif /* _SPNIC_HWIF_H_ */\ndiff --git a/drivers/net/spnic/spnic_ethdev.c b/drivers/net/spnic/spnic_ethdev.c\nindex b06492a8e9..228ed0c936 100644\n--- a/drivers/net/spnic/spnic_ethdev.c\n+++ b/drivers/net/spnic/spnic_ethdev.c\n@@ -9,15 +9,48 @@\n #include <rte_ether.h>\n \n #include \"base/spnic_compat.h\"\n+#include \"base/spnic_csr.h\"\n+#include \"base/spnic_hwdev.h\"\n+#include \"base/spnic_hwif.h\"\n+\n #include \"spnic_ethdev.h\"\n \n /* Driver-specific log messages type */\n int spnic_logtype;\n \n+#define SPNIC_MAX_UC_MAC_ADDRS\t\t128\n+#define SPNIC_MAX_MC_MAC_ADDRS\t\t128\n+\n+/**\n+ * Close the device.\n+ *\n+ * @param[in] dev\n+ * Pointer to ethernet device structure.\n+ */\n+static int spnic_dev_close(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct spnic_nic_dev *nic_dev =\n+\t\tSPNIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);\n+\n+\tif (rte_bit_relaxed_test_and_set32(SPNIC_DEV_CLOSE, &nic_dev->dev_status)) {\n+\t\tPMD_DRV_LOG(WARNING, \"Device %s already closed\",\n+\t\t\t nic_dev->dev_name);\n+\t\treturn 0;\n+\t}\n+\n+\tspnic_free_hwdev(nic_dev->hwdev);\n+\n+\trte_free(nic_dev->hwdev);\n+\tnic_dev->hwdev = NULL;\n+\n+\treturn 0;\n+}\n+\n static int spnic_func_init(struct rte_eth_dev *eth_dev)\n {\n \tstruct spnic_nic_dev *nic_dev = NULL;\n \tstruct rte_pci_device *pci_dev = NULL;\n+\tint err;\n \n \tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n \n@@ -35,11 +68,42 @@ static int spnic_func_init(struct rte_eth_dev *eth_dev)\n \t\t pci_dev->addr.domain, pci_dev->addr.bus,\n \t\t pci_dev->addr.devid, pci_dev->addr.function);\n \n+\teth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;\n+\t/* Create hardware device */\n+\tnic_dev->hwdev = rte_zmalloc(\"spnic_hwdev\", sizeof(*nic_dev->hwdev),\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!nic_dev->hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate hwdev memory failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\terr = -ENOMEM;\n+\t\tgoto alloc_hwdev_mem_fail;\n+\t}\n+\tnic_dev->hwdev->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tnic_dev->hwdev->dev_handle = nic_dev;\n+\tnic_dev->hwdev->eth_dev = eth_dev;\n+\tnic_dev->hwdev->port_id = eth_dev->data->port_id;\n+\n+\terr = spnic_init_hwdev(nic_dev->hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Init chip hwdev failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_hwdev_fail;\n+\t}\n+\n \trte_bit_relaxed_set32(SPNIC_DEV_INIT, &nic_dev->dev_status);\n \tPMD_DRV_LOG(INFO, \"Initialize %s in primary succeed\",\n \t\t eth_dev->data->name);\n \n \treturn 0;\n+\n+init_hwdev_fail:\n+\trte_free(nic_dev->hwdev);\n+\tnic_dev->hwdev = NULL;\n+\n+alloc_hwdev_mem_fail:\n+\tPMD_DRV_LOG(ERR, \"Initialize %s in primary failed\",\n+\t\t eth_dev->data->name);\n+\treturn err;\n }\n \n static int spnic_dev_init(struct rte_eth_dev *eth_dev)\n@@ -67,6 +131,8 @@ static int spnic_dev_uninit(struct rte_eth_dev *dev)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\tspnic_dev_close(dev);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/spnic/spnic_ethdev.h b/drivers/net/spnic/spnic_ethdev.h\nindex d4ec641d83..654234aaa4 100644\n--- a/drivers/net/spnic/spnic_ethdev.h\n+++ b/drivers/net/spnic/spnic_ethdev.h\n@@ -5,21 +5,55 @@\n #ifndef _SPNIC_ETHDEV_H_\n #define _SPNIC_ETHDEV_H_\n \n-/* Vendor id */\n-#define PCI_VENDOR_ID_RAMAXEL\t0x1E81\n-\n-/* Device ids */\n-#define SPNIC_DEV_ID_PF\t\t\t0x9020\n-#define SPNIC_DEV_ID_VF\t\t\t0x9001\n+#define SPNIC_UINT32_BIT_SIZE\t\t(CHAR_BIT * sizeof(uint32_t))\n+#define SPNIC_VFTA_SIZE\t\t\t(4096 / SPNIC_UINT32_BIT_SIZE)\n+#define SPNIC_MAX_QUEUE_NUM\t\t64\n \n enum spnic_dev_status {\n-\tSPNIC_DEV_INIT\n+\tSPNIC_DEV_INIT,\n+\tSPNIC_DEV_CLOSE,\n+\tSPNIC_DEV_START,\n+\tSPNIC_DEV_INTR_EN\n };\n \n #define SPNIC_DEV_NAME_LEN\t\t32\n struct spnic_nic_dev {\n+\tstruct spnic_hwdev *hwdev; /* Hardware device */\n+\n+\tstruct spnic_txq **txqs;\n+\tstruct spnic_rxq **rxqs;\n+\tstruct rte_mempool *cpy_mpool;\n+\n+\tu16 num_sqs;\n+\tu16 num_rqs;\n+\tu16 max_sqs;\n+\tu16 max_rqs;\n+\n+\tu16 rx_buff_len;\n+\tu16 mtu_size;\n+\n+\tu16 rss_state;\n+\tu8 num_rss;\n+\tu8 rsvd0;\n+\n+\tu32 rx_mode;\n+\tu8 rx_queue_list[SPNIC_MAX_QUEUE_NUM];\n+\trte_spinlock_t queue_list_lock;\n+\tpthread_mutex_t rx_mode_mutex;\n+\n+\tu32 default_cos;\n+\tu32 rx_csum_en;\n+\n \tu32 dev_status;\n+\n+\tbool pause_set;\n+\tpthread_mutex_t pause_mutuex;\n+\n+\tstruct rte_ether_addr default_addr;\n+\tstruct rte_ether_addr *mc_list;\n+\n \tchar dev_name[SPNIC_DEV_NAME_LEN];\n+\tu32 vfta[SPNIC_VFTA_SIZE]; /* VLAN bitmap */\n };\n \n #define SPNIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev) \\\n", "prefixes": [ "v1", "02/25" ] }