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GET /api/patches/105197/?format=api
{ "id": 105197, "url": "http://patches.dpdk.org/api/patches/105197/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211217053601.776086-1-joyce.kong@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211217053601.776086-1-joyce.kong@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211217053601.776086-1-joyce.kong@arm.com", "date": "2021-12-17T05:36:00", "name": "[v1] net/i40e: add flow mark capability to NEON vector routine", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "555bbd36d2f057305a07fbbf69cd2cf21ba94bcb", "submitter": { "id": 970, "url": "http://patches.dpdk.org/api/people/970/?format=api", "name": "Joyce Kong", "email": "joyce.kong@arm.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211217053601.776086-1-joyce.kong@arm.com/mbox/", "series": [ { "id": 20960, "url": "http://patches.dpdk.org/api/series/20960/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20960", "date": "2021-12-17T05:36:00", "name": "[v1] net/i40e: add flow mark capability to NEON vector routine", "version": 1, "mbox": "http://patches.dpdk.org/series/20960/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105197/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/105197/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 699E6A04A6;\n\tFri, 17 Dec 2021 06:36:21 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EBB5C40143;\n\tFri, 17 Dec 2021 06:36:20 +0100 (CET)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by mails.dpdk.org (Postfix) with ESMTP id 085DD4013F\n for <dev@dpdk.org>; Fri, 17 Dec 2021 06:36:18 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 35E3212FC;\n Thu, 16 Dec 2021 21:36:18 -0800 (PST)", "from net-arm-n1amp-02.shanghai.arm.com\n (net-arm-n1amp-02.shanghai.arm.com [10.169.210.110])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5DF523F5A1;\n Thu, 16 Dec 2021 21:36:16 -0800 (PST)" ], "From": "Joyce Kong <joyce.kong@arm.com>", "To": "Ruifeng Wang <ruifeng.wang@arm.com>,\n\tBeilei Xing <beilei.xing@intel.com>", "Cc": "dev@dpdk.org,\n\tnd@arm.com,\n\tJoyce Kong <joyce.kong@arm.com>", "Subject": "[PATCH v1] net/i40e: add flow mark capability to NEON vector routine", "Date": "Fri, 17 Dec 2021 05:36:00 +0000", "Message-Id": "<20211217053601.776086-1-joyce.kong@arm.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit adds a flow director support to i40e NEON\nvector RX path.\n\nI40e can have 16 and 32 byte descriptors, and the Flow\nDirector ID data and indication-bit are in different\nlocations for each size descriptor. The support is\nimplemented in two separate functions as they require\nvastly different operations.\n\nThe 16B descriptor re-purposes the \"filter-status\" u32\nfield to indicate FDIR ID when the FLM bit is set. No\nextra loads are required, however we do have to store\nto mbuf->fdir.hi, which is not stored to in the RX path\nbefore this patch.\n\nThe 32B descriptor requires loading the 2nd 16 bytes of\neach descriptor, to get the FLEXBH_STAT and FD Filter ID\nfrom qword3. The resulting data must also be stored to\nmbuf->fdir.hi, same as the 16B code path.\n\nSigned-off-by: Joyce Kong <joyce.kong@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\n---\n drivers/net/i40e/i40e_rxtx_vec_neon.c | 145 ++++++++++++++++++++++++--\n 1 file changed, 139 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c b/drivers/net/i40e/i40e_rxtx_vec_neon.c\nindex b951ea2dc3..a7ca2c18e5 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_neon.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c\n@@ -77,9 +77,130 @@ i40e_rxq_rearm(struct i40e_rx_queue *rxq)\n \tI40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rx_id);\n }\n \n+#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n+/* NEON version of FDIR mark extraction for 4 32B descriptors at a time */\n+static inline uint32x4_t\n+descs_to_fdir_32b(volatile union i40e_rx_desc *rxdp, struct rte_mbuf **rx_pkt)\n+{\n+\t/* 32B descriptors: Load 2nd half of descriptors for FDIR ID data */\n+\tuint64x2_t desc0_qw23, desc1_qw23, desc2_qw23, desc3_qw23;\n+\tdesc0_qw23 = vld1q_u64((uint64_t *)&(rxdp + 0)->wb.qword2);\n+\tdesc1_qw23 = vld1q_u64((uint64_t *)&(rxdp + 1)->wb.qword2);\n+\tdesc2_qw23 = vld1q_u64((uint64_t *)&(rxdp + 2)->wb.qword2);\n+\tdesc3_qw23 = vld1q_u64((uint64_t *)&(rxdp + 3)->wb.qword2);\n+\n+\t/* FDIR ID data: move last u32 of each desc to 4 u32 lanes */\n+\tuint32x4_t v_unpack_02, v_unpack_13;\n+\tv_unpack_02 = vzipq_u32(vreinterpretq_u32_u64(desc0_qw23),\n+\t\t\t\tvreinterpretq_u32_u64(desc2_qw23)).val[1];\n+\tv_unpack_13 = vzipq_u32(vreinterpretq_u32_u64(desc1_qw23),\n+\t\t\t\tvreinterpretq_u32_u64(desc3_qw23)).val[1];\n+\tuint32x4_t v_fdir_ids = vzipq_u32(v_unpack_02, v_unpack_13).val[1];\n+\n+\t/* Extended Status: extract from each lower 32 bits, to u32 lanes */\n+\tv_unpack_02 = vzipq_u32(vreinterpretq_u32_u64(desc0_qw23),\n+\t\t\t\tvreinterpretq_u32_u64(desc2_qw23)).val[0];\n+\tv_unpack_13 = vzipq_u32(vreinterpretq_u32_u64(desc1_qw23),\n+\t\t\t\tvreinterpretq_u32_u64(desc3_qw23)).val[0];\n+\tuint32x4_t v_flt_status = vzipq_u32(v_unpack_02, v_unpack_13).val[0];\n+\n+\t/* Shift u32 left and right to \"mask away\" bits not required.\n+\t * Data required is 4:5 (zero based), so left shift by 26 (32-6)\n+\t * and then right shift by 30 (32 - 2 bits required).\n+\t */\n+\tv_flt_status = vshlq_n_u32(v_flt_status, 26);\n+\tv_flt_status = vshrq_n_u32(v_flt_status, 30);\n+\n+\t/* Generate constant 1 in all u32 lanes */\n+\tRTE_BUILD_BUG_ON(I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID != 1);\n+\tuint32x4_t v_u32_one = vdupq_n_u32(1);\n+\n+\t/* Per desc mask, bits set if FDIR ID is valid */\n+\tuint32x4_t v_fd_id_mask = vceqq_u32(v_flt_status, v_u32_one);\n+\n+\t/* Mask ID data to zero if the FD_ID bit not set in desc */\n+\tv_fdir_ids = vandq_u32(v_fdir_ids, v_fd_id_mask);\n+\n+\t/* Store data to fdir.hi in mbuf */\n+\trx_pkt[0]->hash.fdir.hi = vgetq_lane_u32(v_fdir_ids, 0);\n+\trx_pkt[1]->hash.fdir.hi = vgetq_lane_u32(v_fdir_ids, 1);\n+\trx_pkt[2]->hash.fdir.hi = vgetq_lane_u32(v_fdir_ids, 2);\n+\trx_pkt[3]->hash.fdir.hi = vgetq_lane_u32(v_fdir_ids, 3);\n+\n+\t/* Convert fdir_id_mask into a single bit, then shift as required for\n+\t * correct location in the mbuf->olflags\n+\t */\n+\tRTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << 13));\n+\tv_fd_id_mask = vshrq_n_u32(v_fd_id_mask, 31);\n+\tv_fd_id_mask = vshlq_n_u32(v_fd_id_mask, 13);\n+\n+\t/* The returned value must be combined into each mbuf. This is already\n+\t * being done for RSS and VLAN mbuf olflags, so return bits to OR in.\n+\t */\n+\treturn v_fd_id_mask;\n+}\n+\n+#else /* 32 or 16B FDIR ID handling */\n+\n+/* Handle 16B descriptor FDIR ID flag setting based on FLM(bit11). See scalar driver\n+ * for scalar implementation of the same functionality.\n+ */\n+static inline uint32x4_t\n+descs_to_fdir_16b(uint32x4_t fltstat, uint64x2_t descs[4], struct rte_mbuf **rx_pkt)\n+{\n+\t/* Unpack filter-status data from descriptors */\n+\tuint32x4_t v_tmp_02 = vzipq_u32(vreinterpretq_u32_u64(descs[0]),\n+\t\t\t\t\tvreinterpretq_u32_u64(descs[2])).val[0];\n+\tuint32x4_t v_tmp_13 = vzipq_u32(vreinterpretq_u32_u64(descs[1]),\n+\t\t\t\t\tvreinterpretq_u32_u64(descs[3])).val[0];\n+\tuint32x4_t v_fdir_ids = vzipq_u32(v_tmp_02, v_tmp_13).val[1];\n+\n+\t/* Generate 111 and 11 in each u32 lane */\n+\tuint32x4_t v_111_mask = vdupq_n_u32(7);\n+\tuint32x4_t v_11_mask = vdupq_n_u32(3);\n+\n+\t/* Compare and mask away FDIR ID data if bit not set */\n+\tuint32x4_t v_u32_bits = vandq_u32(v_111_mask, fltstat);\n+\tuint32x4_t v_fdir_id_mask = vceqq_u32(v_u32_bits, v_11_mask);\n+\tv_fdir_ids = vandq_u32(v_fdir_id_mask, v_fdir_ids);\n+\n+\t/* Store data to fdir.hi in mbuf */\n+\trx_pkt[0]->hash.fdir.hi = vgetq_lane_u32(v_fdir_ids, 0);\n+\trx_pkt[1]->hash.fdir.hi = vgetq_lane_u32(v_fdir_ids, 1);\n+\trx_pkt[2]->hash.fdir.hi = vgetq_lane_u32(v_fdir_ids, 2);\n+\trx_pkt[3]->hash.fdir.hi = vgetq_lane_u32(v_fdir_ids, 3);\n+\n+\t/* Top lane ones mask for FDIR isolation */\n+\tuint32x4_t v_desc_fdir_mask = {0, UINT32_MAX, 0, 0};\n+\n+\t/* Move fdir_id_mask to correct lane, zero RSS in mbuf if fdir hits */\n+\tuint32x4_t v_zeros = {0, 0, 0, 0};\n+\tuint32x4_t v_desc3_shift = vextq_u32(v_fdir_id_mask, v_zeros, 2);\n+\tuint32x4_t v_desc3_mask = vandq_u32(v_desc_fdir_mask, v_desc3_shift);\n+\tdescs[3] = vbslq_u32(v_desc3_mask, v_zeros, vreinterpretq_u32_u64(descs[3]));\n+\n+\tuint32x4_t v_desc2_shift = vextq_u32(v_fdir_id_mask, v_zeros, 1);\n+\tuint32x4_t v_desc2_mask = vandq_u32(v_desc_fdir_mask, v_desc2_shift);\n+\tdescs[2] = vbslq_u32(v_desc2_mask, v_zeros, vreinterpretq_u32_u64(descs[2]));\n+\n+\tuint32x4_t v_desc1_shift = v_fdir_id_mask;\n+\tuint32x4_t v_desc1_mask = vandq_u32(v_desc_fdir_mask, v_desc1_shift);\n+\tdescs[1] = vbslq_u32(v_desc1_mask, v_zeros, vreinterpretq_u32_u64(descs[1]));\n+\n+\tuint32x4_t v_desc0_shift = vextq_u32(v_zeros, v_fdir_id_mask, 3);\n+\tuint32x4_t v_desc0_mask = vandq_u32(v_desc_fdir_mask, v_desc0_shift);\n+\tdescs[0] = vbslq_u32(v_desc0_mask, v_zeros, vreinterpretq_u32_u64(descs[0]));\n+\n+\t/* Shift to 1 or 0 bit per u32 lane, then to RTE_MBUF_F_RX_FDIR_ID offset */\n+\tRTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << 13));\n+\tuint32x4_t v_mask_one_bit = vshrq_n_u32(v_fdir_id_mask, 31);\n+\treturn vshlq_n_u32(v_mask_one_bit, 13);\n+}\n+#endif\n+\n static inline void\n-desc_to_olflags_v(struct i40e_rx_queue *rxq, uint64x2_t descs[4],\n-\t\t struct rte_mbuf **rx_pkts)\n+desc_to_olflags_v(struct i40e_rx_queue *rxq, volatile union i40e_rx_desc *rxdp,\n+\t\t uint64x2_t descs[4], struct rte_mbuf **rx_pkts)\n {\n \tuint32x4_t vlan0, vlan1, rss, l3_l4e;\n \tconst uint64x2_t mbuf_init = {rxq->mbuf_initializer, 0};\n@@ -142,9 +263,9 @@ desc_to_olflags_v(struct i40e_rx_queue *rxq, uint64x2_t descs[4],\n \tvlan0 = vreinterpretq_u32_u8(vqtbl1q_u8(vlan_flags,\n \t\t\t\t\t\tvreinterpretq_u8_u32(vlan1)));\n \n-\trss = vshrq_n_u32(vlan1, 11);\n+\tconst uint32x4_t desc_fltstat = vshrq_n_u32(vlan1, 11);\n \trss = vreinterpretq_u32_u8(vqtbl1q_u8(rss_flags,\n-\t\t\t\t\t vreinterpretq_u8_u32(rss)));\n+\t\t\t\t\t vreinterpretq_u8_u32(desc_fltstat)));\n \n \tl3_l4e = vshrq_n_u32(vlan1, 22);\n \tl3_l4e = vreinterpretq_u32_u8(vqtbl1q_u8(l3_l4e_flags,\n@@ -157,6 +278,18 @@ desc_to_olflags_v(struct i40e_rx_queue *rxq, uint64x2_t descs[4],\n \tvlan0 = vorrq_u32(vlan0, rss);\n \tvlan0 = vorrq_u32(vlan0, l3_l4e);\n \n+\t/* Extract FDIR ID only if FDIR is enabled to avoid useless work */\n+\tif (rxq->fdir_enabled) {\n+#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n+\t\tuint32x4_t v_fdir_ol_flags = descs_to_fdir_32b(rxdp, rx_pkts);\n+#else\n+\t\t(void)rxdp; /* rxdp not required for 16B desc mode */\n+\t\tuint32x4_t v_fdir_ol_flags = descs_to_fdir_16b(desc_fltstat, descs, rx_pkts);\n+#endif\n+\t\t/* OR in ol_flag bits after descriptor specific extraction */\n+\t\tvlan0 = vorrq_u32(vlan0, v_fdir_ol_flags);\n+\t}\n+\n \trearm0 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 0), mbuf_init, 1);\n \trearm1 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 1), mbuf_init, 1);\n \trearm2 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 2), mbuf_init, 1);\n@@ -335,6 +468,8 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,\n \t\t\t\t vreinterpretq_u16_u64(descs[0]),\n \t\t\t\t 7));\n \n+\t\tdesc_to_olflags_v(rxq, rxdp, descs, &rx_pkts[pos]);\n+\n \t\t/* D.1 pkts convert format from desc to pktmbuf */\n \t\tpkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);\n \t\tpkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);\n@@ -363,8 +498,6 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,\n \n \t\tdesc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);\n \n-\t\tdesc_to_olflags_v(rxq, descs, &rx_pkts[pos]);\n-\n \t\tif (likely(pos + RTE_I40E_DESCS_PER_LOOP < nb_pkts)) {\n \t\t\trte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);\n \t\t}\n", "prefixes": [ "v1" ] }