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GET /api/patches/105120/?format=api
{ "id": 105120, "url": "http://patches.dpdk.org/api/patches/105120/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213211425.6332-3-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211213211425.6332-3-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211213211425.6332-3-pbhagavatula@marvell.com", "date": "2021-12-13T21:14:23", "name": "[3/4] event/cnxk: disable default wait time for dequeue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d831303a0230731e4a1f39a9edf83356c7c845a0", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213211425.6332-3-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 20936, "url": "http://patches.dpdk.org/api/series/20936/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20936", "date": "2021-12-13T21:14:21", "name": "[1/4] net/cnxk: avoid command copy from Tx queue", "version": 1, "mbox": "http://patches.dpdk.org/series/20936/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105120/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/105120/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BFB73A034D;\n\tMon, 13 Dec 2021 22:15:40 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 22A4F41148;\n\tMon, 13 Dec 2021 22:15:32 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id BC99141148\n for <dev@dpdk.org>; Mon, 13 Dec 2021 22:15:30 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BDElBZC029954\n for <dev@dpdk.org>; Mon, 13 Dec 2021 13:15:30 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cx88ahnmx-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 13 Dec 2021 13:15:29 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Dec 2021 13:15:28 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 13 Dec 2021 13:15:28 -0800", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 9E7F23F704A;\n Mon, 13 Dec 2021 13:15:26 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=+Xa3irZFGXbJkg4esCECZ9meyE9aDXZQNxZiN/8kk3I=;\n b=MamA9oQrjiA4r1EIztFgVljkjLmFrufQ9EmVP2mWHQ+McdSZ8pRR/iMaT+u/pSRAy41v\n mo75dA1/PAgGAmf4Mr7IgWW+DDfqjSPdGgKjzIP21pL0hyNuR4mjqdPFNt3RQ5Jkg0kj\n U8pNLd7bQ0ZWQEa5E9ngq1MMXeCuSXbbqGdOr7QwUOT9P0slS1AwLbBc45SEXYPwSx3l\n dm1UkKZGY77WXgwUCh/2G4d5y5pNXUhJhNMgaQZMcyKHtEzIrj1MHrGHz5W1vKAR8Dvj\n UaJAworuVDbqXIPFg/h4f7RsHAYoqUryXeCQLEYjyqsB+qVXImz+lU4mSYgtfEa7Q3VQ 1g==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 3/4] event/cnxk: disable default wait time for dequeue", "Date": "Tue, 14 Dec 2021 02:44:23 +0530", "Message-ID": "<20211213211425.6332-3-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211213211425.6332-1-pbhagavatula@marvell.com>", "References": "<20211213211425.6332-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "g2TmiKQCVKsuVYkoGZK7RDaG7U5WjCTm", "X-Proofpoint-ORIG-GUID": "g2TmiKQCVKsuVYkoGZK7RDaG7U5WjCTm", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nSetting WAITW bit enables default min dequeue timeout of 1us.\nAvoid the min dequeue timeout by setting WAITW only when dequeue_timeout\nis configured.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 8 +++++--\n drivers/event/cnxk/cn9k_eventdev.c | 9 ++++++-\n drivers/event/cnxk/cn9k_worker.h | 37 +++++++++++++----------------\n drivers/event/cnxk/cnxk_eventdev.c | 2 +-\n drivers/event/cnxk/cnxk_eventdev.h | 2 ++\n 5 files changed, 34 insertions(+), 24 deletions(-)\n\n--\n2.17.1", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex c57e45a118..380d1ede69 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -15,7 +15,10 @@\n static uint32_t\n cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)\n {\n-\tuint32_t wdata = BIT(16) | 1;\n+\tuint32_t wdata = 1;\n+\n+\tif (dev->deq_tmo_ns)\n+\t\twdata |= BIT(16);\n\n \tswitch (dev->gw_mode) {\n \tcase CN10K_GW_MODE_NONE:\n@@ -88,7 +91,8 @@ cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)\n \tws->xaq_lmt = dev->xaq_lmt;\n\n \t/* Set get_work timeout for HWS */\n-\tval = NSEC2USEC(dev->deq_tmo_ns) - 1;\n+\tval = NSEC2USEC(dev->deq_tmo_ns);\n+\tval = val ? val - 1 : 0;\n \tplt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);\n }\n\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 98294be11f..eeacdf9439 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -72,7 +72,8 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)\n \tuint64_t val;\n\n \t/* Set get_work tmo for HWS */\n-\tval = dev->deq_tmo_ns ? NSEC2USEC(dev->deq_tmo_ns) - 1 : 0;\n+\tval = NSEC2USEC(dev->deq_tmo_ns);\n+\tval = val ? val - 1 : 0;\n \tif (dev->dual_ws) {\n \t\tdws = hws;\n \t\tdws->grp_base = grp_base;\n@@ -696,6 +697,9 @@ cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)\n \t\tdws->hws_id = port_id;\n \t\tdws->swtag_req = 0;\n \t\tdws->vws = 0;\n+\t\tif (dev->deq_tmo_ns)\n+\t\t\tdws->gw_wdata = BIT_ULL(16);\n+\t\tdws->gw_wdata |= 1;\n\n \t\tdata = dws;\n \t} else {\n@@ -714,6 +718,9 @@ cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)\n \t\tws->base = roc_sso_hws_base_get(&dev->sso, port_id);\n \t\tws->hws_id = port_id;\n \t\tws->swtag_req = 0;\n+\t\tif (dev->deq_tmo_ns)\n+\t\t\tws->gw_wdata = BIT_ULL(16);\n+\t\tws->gw_wdata |= 1;\n\n \t\tdata = ws;\n \t}\ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nindex 0f58e00e7f..32bf2345e7 100644\n--- a/drivers/event/cnxk/cn9k_worker.h\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -149,10 +149,8 @@ cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,\n static __rte_always_inline uint16_t\n cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,\n \t\t\t struct rte_event *ev, const uint32_t flags,\n-\t\t\t const void *const lookup_mem,\n-\t\t\t struct cnxk_timesync_info *const tstamp)\n+\t\t\t struct cn9k_sso_hws_dual *dws)\n {\n-\tconst uint64_t set_gw = BIT_ULL(16) | 1;\n \tunion {\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n@@ -161,7 +159,7 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,\n \tuint64_t mbuf;\n\n \tif (flags & NIX_RX_OFFLOAD_PTYPE_F)\n-\t\trte_prefetch_non_temporal(lookup_mem);\n+\t\trte_prefetch_non_temporal(dws->lookup_mem);\n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n \t\t \"rty%=:\t\t\t\t\t\\n\"\n@@ -175,14 +173,14 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,\n \t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n \t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(base + SSOW_LF_GWS_TAG),\n-\t\t [wqp_loc] \"r\"(base + SSOW_LF_GWS_WQP), [gw] \"r\"(set_gw),\n+\t\t [wqp_loc] \"r\"(base + SSOW_LF_GWS_WQP), [gw] \"r\"(dws->gw_wdata),\n \t\t [pong] \"r\"(pair_base + SSOW_LF_GWS_OP_GET_WORK0));\n #else\n \tgw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);\n \twhile ((BIT_ULL(63)) & gw.u64[0])\n \t\tgw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);\n \tgw.u64[1] = plt_read64(base + SSOW_LF_GWS_WQP);\n-\tplt_write64(set_gw, pair_base + SSOW_LF_GWS_OP_GET_WORK0);\n+\tplt_write64(dws->gw_wdata, pair_base + SSOW_LF_GWS_OP_GET_WORK0);\n \tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n\n@@ -202,12 +200,13 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,\n \t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n \t\t\tcn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n \t\t\t\t\t gw.u64[0] & 0xFFFFF, flags,\n-\t\t\t\t\t lookup_mem);\n+\t\t\t\t\t dws->lookup_mem);\n \t\t\t/* Extracting tstamp, if PTP enabled*/\n \t\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)\n \t\t\t\t\t\t\t gw.u64[1]) +\n \t\t\t\t\t\t CNXK_SSO_WQE_SG_PTR);\n-\t\t\tcnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,\n+\t\t\tcnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,\n+\t\t\t\t\t\tdws->tstamp,\n \t\t\t\t\t\tflags & NIX_RX_OFFLOAD_TSTAMP_F,\n \t\t\t\t\t\tflags & NIX_RX_MULTI_SEG_F,\n \t\t\t\t\t\t(uint64_t *)tstamp_ptr);\n@@ -232,9 +231,7 @@ cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev,\n \tuint64_t tstamp_ptr;\n \tuint64_t mbuf;\n\n-\tplt_write64(BIT_ULL(16) | /* wait for work. */\n-\t\t\t 1,\t /* Use Mask set 0. */\n-\t\t ws->base + SSOW_LF_GWS_OP_GET_WORK0);\n+\tplt_write64(ws->gw_wdata, ws->base + SSOW_LF_GWS_OP_GET_WORK0);\n\n \tif (flags & NIX_RX_OFFLOAD_PTYPE_F)\n \t\trte_prefetch_non_temporal(lookup_mem);\n@@ -532,9 +529,9 @@ NIX_RX_FASTPATH_MODES\n \t\t\t\t\t\tSSOW_LF_GWS_TAG); \\\n \t\t\treturn 1; \\\n \t\t} \\\n-\t\tgw = cn9k_sso_hws_dual_get_work( \\\n-\t\t\tdws->base[dws->vws], dws->base[!dws->vws], ev, flags, \\\n-\t\t\tdws->lookup_mem, dws->tstamp); \\\n+\t\tgw = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \\\n+\t\t\t\t\t\tdws->base[!dws->vws], ev, \\\n+\t\t\t\t\t\tflags, dws); \\\n \t\tdws->vws = !dws->vws; \\\n \t\treturn gw; \\\n \t}\n@@ -558,14 +555,14 @@ NIX_RX_FASTPATH_MODES\n \t\t\t\t\t\tSSOW_LF_GWS_TAG); \\\n \t\t\treturn ret; \\\n \t\t} \\\n-\t\tret = cn9k_sso_hws_dual_get_work( \\\n-\t\t\tdws->base[dws->vws], dws->base[!dws->vws], ev, flags, \\\n-\t\t\tdws->lookup_mem, dws->tstamp); \\\n+\t\tret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \\\n+\t\t\t\t\t\t dws->base[!dws->vws], ev, \\\n+\t\t\t\t\t\t flags, dws); \\\n \t\tdws->vws = !dws->vws; \\\n \t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { \\\n-\t\t\tret = cn9k_sso_hws_dual_get_work( \\\n-\t\t\t\tdws->base[dws->vws], dws->base[!dws->vws], ev, \\\n-\t\t\t\tflags, dws->lookup_mem, dws->tstamp); \\\n+\t\t\tret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \\\n+\t\t\t\t\t\t\t dws->base[!dws->vws], \\\n+\t\t\t\t\t\t\t ev, flags, dws); \\\n \t\t\tdws->vws = !dws->vws; \\\n \t\t} \\\n \t\treturn ret; \\\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex 6ad4e23e2b..be021d86c9 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -610,7 +610,7 @@ cnxk_sso_init(struct rte_eventdev *event_dev)\n \t}\n\n \tdev->is_timeout_deq = 0;\n-\tdev->min_dequeue_timeout_ns = USEC2NSEC(1);\n+\tdev->min_dequeue_timeout_ns = 0;\n \tdev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);\n \tdev->max_num_events = -1;\n \tdev->nb_event_queues = 0;\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex ab58508590..e3b5ffa7eb 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -144,6 +144,7 @@ struct cn10k_sso_hws {\n /* Event port a.k.a GWS */\n struct cn9k_sso_hws {\n \tuint64_t base;\n+\tuint64_t gw_wdata;\n \t/* PTP timestamp */\n \tstruct cnxk_timesync_info *tstamp;\n \tvoid *lookup_mem;\n@@ -160,6 +161,7 @@ struct cn9k_sso_hws {\n\n struct cn9k_sso_hws_dual {\n \tuint64_t base[2]; /* Ping and Pong */\n+\tuint64_t gw_wdata;\n \t/* PTP timestamp */\n \tstruct cnxk_timesync_info *tstamp;\n \tvoid *lookup_mem;\n", "prefixes": [ "3/4" ] }