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{
    "id": 105118,
    "url": "http://patches.dpdk.org/api/patches/105118/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213211425.6332-1-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211213211425.6332-1-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211213211425.6332-1-pbhagavatula@marvell.com",
    "date": "2021-12-13T21:14:21",
    "name": "[1/4] net/cnxk: avoid command copy from Tx queue",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b649f5a0b894d84025cde3f91f720d6857263bfd",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213211425.6332-1-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 20936,
            "url": "http://patches.dpdk.org/api/series/20936/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20936",
            "date": "2021-12-13T21:14:21",
            "name": "[1/4] net/cnxk: avoid command copy from Tx queue",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/20936/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/105118/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/105118/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
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        "Received": [
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        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>,\n Anoob Joseph <anoobj@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>, Shijith Thotton\n <sthotton@marvell.com>",
        "CC": "<dev@dpdk.org>",
        "Subject": "[PATCH 1/4] net/cnxk: avoid command copy from Tx queue",
        "Date": "Tue, 14 Dec 2021 02:44:21 +0530",
        "Message-ID": "<20211213211425.6332-1-pbhagavatula@marvell.com>",
        "X-Mailer": "git-send-email 2.17.1",
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        "X-Proofpoint-ORIG-GUID": "e7r2_CnYZbogKJJGDmqt0F6WtaQpdqYI",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01",
        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nTx command is prepared based on offloads enabled and stored in\nTx queue structure at tx_queue_setup phase.\nIn fastpath the command is copied from Tx queue to LMT line for\nall the packets.\nSince, the command contents are mostly constants we can move the\ncommand preparation to fastpath and avoid accessing Tx queue\nmemory.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n Depends-on: Series-20922\n\n drivers/common/cnxk/roc_io.h             |  33 ++++-\n drivers/common/cnxk/roc_io_generic.h     |  15 ++\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c |   2 +-\n drivers/crypto/cnxk/cn9k_ipsec.c         |   2 +-\n drivers/event/cnxk/cn10k_eventdev.c      |  26 +++-\n drivers/event/cnxk/cn10k_worker.h        |  89 ++++++------\n drivers/event/cnxk/cn9k_eventdev.c       |  33 +++--\n drivers/event/cnxk/cn9k_worker.h         |  64 ++++-----\n drivers/event/cnxk/cnxk_eventdev.h       |  13 +-\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 141 ++++++++++++++++---\n drivers/net/cnxk/cn10k_ethdev.c          |  24 +---\n drivers/net/cnxk/cn10k_ethdev.h          |   3 +-\n drivers/net/cnxk/cn10k_tx.h              | 167 ++++++++++++-----------\n drivers/net/cnxk/cn9k_ethdev.c           |  36 ++---\n drivers/net/cnxk/cn9k_ethdev.h           |   3 +-\n drivers/net/cnxk/cn9k_tx.h               | 133 +++++++++++-------\n 16 files changed, 478 insertions(+), 306 deletions(-)\n\n--\n2.17.1",
    "diff": "diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h\nindex fe5f7f46d0..ea7fcd4e9a 100644\n--- a/drivers/common/cnxk/roc_io.h\n+++ b/drivers/common/cnxk/roc_io.h\n@@ -152,13 +152,36 @@ roc_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n \tdst128[1] = src128[1];\n \t/* lmtext receives following value:\n \t * 1: NIX_SUBDC_EXT needed i.e. tx vlan case\n-\t * 2: NIX_SUBDC_EXT + NIX_SUBDC_MEM i.e. tstamp case\n \t */\n-\tif (lmtext) {\n+\tif (lmtext)\n+\t\tdst128[2] = src128[2];\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov64(void *out, const void *in)\n+{\n+\tvolatile const __uint128_t *src128 = (const __uint128_t *)in;\n+\tvolatile __uint128_t *dst128 = (__uint128_t *)out;\n+\n+\tdst128[0] = src128[0];\n+\tdst128[1] = src128[1];\n+\tdst128[2] = src128[2];\n+\tdst128[3] = src128[3];\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov_nv(void *out, const void *in, const uint32_t lmtext)\n+{\n+\tconst __uint128_t *src128 = (const __uint128_t *)in;\n+\t__uint128_t *dst128 = (__uint128_t *)out;\n+\n+\tdst128[0] = src128[0];\n+\tdst128[1] = src128[1];\n+\t/* lmtext receives following value:\n+\t * 1: NIX_SUBDC_EXT needed i.e. tx vlan case\n+\t */\n+\tif (lmtext)\n \t\tdst128[2] = src128[2];\n-\t\tif (lmtext > 1)\n-\t\t\tdst128[3] = src128[3];\n-\t}\n }\n\n static __plt_always_inline void\ndiff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h\nindex ceaa3a38d8..af42e66345 100644\n--- a/drivers/common/cnxk/roc_io_generic.h\n+++ b/drivers/common/cnxk/roc_io_generic.h\n@@ -97,6 +97,21 @@ roc_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n \tmemset(out, 0, sizeof(__uint128_t) * (lmtext ? lmtext > 1 ? 4 : 3 : 2));\n }\n\n+static __plt_always_inline void\n+roc_lmt_mov64(void *out, const void *in)\n+{\n+\tPLT_SET_USED(out);\n+\tPLT_SET_USED(in);\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov_nv(void *out, const void *in, const uint32_t lmtext)\n+{\n+\tPLT_SET_USED(in);\n+\tPLT_SET_USED(lmtext);\n+\tmemset(out, 0, sizeof(__uint128_t) * (lmtext ? lmtext > 1 ? 4 : 3 : 2));\n+}\n+\n static __plt_always_inline void\n roc_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)\n {\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex 449208da8f..53e427a3c1 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -161,7 +161,7 @@ cn9k_cpt_inst_submit(struct cpt_inst_s *inst, uint64_t lmtline,\n\n \tdo {\n \t\t/* Copy CPT command to LMTLINE */\n-\t\troc_lmt_mov((void *)lmtline, inst, 2);\n+\t\troc_lmt_mov64((void *)lmtline, inst);\n\n \t\t/*\n \t\t * Make sure compiler does not reorder memcpy and ldeor.\ndiff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c\nindex a81130b244..117e54cae7 100644\n--- a/drivers/crypto/cnxk/cn9k_ipsec.c\n+++ b/drivers/crypto/cnxk/cn9k_ipsec.c\n@@ -53,7 +53,7 @@ cn9k_cpt_enq_sa_write(struct cn9k_ipsec_sa *sa, struct cnxk_cpt_qp *qp,\n\n \tdo {\n \t\t/* Copy CPT command to LMTLINE */\n-\t\troc_lmt_mov((void *)lmtline, &inst, 2);\n+\t\troc_lmt_mov64((void *)lmtline, &inst);\n \t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n \t} while (lmt_status == 0);\n\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 70e2aa5555..c57e45a118 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -50,7 +50,6 @@ cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)\n \t/* First cache line is reserved for cookie */\n \tws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);\n \tws->base = roc_sso_hws_base_get(&dev->sso, port_id);\n-\tws->tx_base = ws->base;\n \tws->hws_id = port_id;\n \tws->swtag_req = 0;\n \tws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);\n@@ -259,15 +258,13 @@ cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)\n \t\t\tws_cookie,\n \t\t\tsizeof(struct cnxk_sso_hws_cookie) +\n \t\t\t\tsizeof(struct cn10k_sso_hws) +\n-\t\t\t\t(sizeof(uint64_t) * (dev->max_port_id + 1) *\n-\t\t\t\t RTE_MAX_QUEUES_PER_PORT),\n+\t\t\t\tdev->tx_adptr_data_sz,\n \t\t\tRTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n \t\tif (ws_cookie == NULL)\n \t\t\treturn -ENOMEM;\n \t\tws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));\n \t\tmemcpy(&ws->tx_adptr_data, dev->tx_adptr_data,\n-\t\t       sizeof(uint64_t) * (dev->max_port_id + 1) *\n-\t\t\t       RTE_MAX_QUEUES_PER_PORT);\n+\t\t       dev->tx_adptr_data_sz);\n \t\tevent_dev->data->ports[i] = ws;\n \t}\n\n@@ -727,16 +724,35 @@ cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,\n \t\t\t       const struct rte_eth_dev *eth_dev,\n \t\t\t       int32_t tx_queue_id)\n {\n+\tstruct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tuint64_t tx_offloads;\n \tint rc;\n\n \tRTE_SET_USED(id);\n \trc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);\n \tif (rc < 0)\n \t\treturn rc;\n+\n+\t/* Can't enable tstamp if all the ports don't have it enabled. */\n+\ttx_offloads = cnxk_eth_dev->tx_offload_flags;\n+\tif (dev->tx_adptr_configured) {\n+\t\tuint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);\n+\t\tuint8_t tstmp_ena =\n+\t\t\t!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);\n+\n+\t\tif (tstmp_ena && !tstmp_req)\n+\t\t\tdev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);\n+\t\telse if (!tstmp_ena && tstmp_req)\n+\t\t\ttx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);\n+\t}\n+\n+\tdev->tx_offloads |= tx_offloads;\n \trc = cn10k_sso_updt_tx_adptr_data(event_dev);\n \tif (rc < 0)\n \t\treturn rc;\n \tcn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);\n+\tdev->tx_adptr_configured = 1;\n\n \treturn 0;\n }\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex 78d029baaa..e80e4fb895 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -457,18 +457,18 @@ NIX_RX_FASTPATH_MODES\n \t}\n\n static __rte_always_inline struct cn10k_eth_txq *\n-cn10k_sso_hws_xtract_meta(struct rte_mbuf *m,\n-\t\t\t  const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT])\n+cn10k_sso_hws_xtract_meta(struct rte_mbuf *m, const uint64_t *txq_data)\n {\n-\treturn (struct cn10k_eth_txq *)\n-\t\ttxq_data[m->port][rte_event_eth_tx_adapter_txq_get(m)];\n+\treturn (struct cn10k_eth_txq\n+\t\t\t*)(txq_data[(txq_data[m->port] >> 48) +\n+\t\t\t\t    rte_event_eth_tx_adapter_txq_get(m)] &\n+\t\t\t   (BIT_ULL(48) - 1));\n }\n\n static __rte_always_inline void\n-cn10k_sso_tx_one(struct rte_mbuf *m, uint64_t *cmd, uint16_t lmt_id,\n-\t\t uintptr_t lmt_addr, uint8_t sched_type, uintptr_t base,\n-\t\t const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],\n-\t\t const uint32_t flags)\n+cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd,\n+\t\t uint16_t lmt_id, uintptr_t lmt_addr, uint8_t sched_type,\n+\t\t const uint64_t *txq_data, const uint32_t flags)\n {\n \tuint8_t lnum = 0, loff = 0, shft = 0;\n \tstruct cn10k_eth_txq *txq;\n@@ -478,7 +478,7 @@ cn10k_sso_tx_one(struct rte_mbuf *m, uint64_t *cmd, uint16_t lmt_id,\n \tbool sec;\n\n \ttxq = cn10k_sso_hws_xtract_meta(m, txq_data);\n-\tcn10k_nix_tx_skeleton(txq, cmd, flags);\n+\tcn10k_nix_tx_skeleton(txq, cmd, flags, 0);\n \t/* Perform header writes before barrier\n \t * for TSO\n \t */\n@@ -503,23 +503,23 @@ cn10k_sso_tx_one(struct rte_mbuf *m, uint64_t *cmd, uint16_t lmt_id,\n \telse\n \t\tsegdw = cn10k_nix_tx_ext_subs(flags) + 2;\n\n+\tcn10k_nix_xmit_prepare_tstamp(txq, laddr, m->ol_flags, segdw, flags);\n \tif (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)\n \t\tpa = txq->cpt_io_addr | 3 << 4;\n \telse\n \t\tpa = txq->io_addr | ((segdw - 1) << 4);\n\n \tif (!sched_type)\n-\t\troc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);\n+\t\troc_sso_hws_head_wait(ws->base + SSOW_LF_GWS_TAG);\n\n \troc_lmt_submit_steorl(lmt_id, pa);\n }\n\n static __rte_always_inline void\n-cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,\n-\t\t\tuint64_t *cmd, uint16_t lmt_id, uintptr_t lmt_addr,\n-\t\t\tuint8_t sched_type, uintptr_t base,\n-\t\t\tconst uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],\n-\t\t\tconst uint32_t flags)\n+cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs,\n+\t\t\tuint16_t nb_mbufs, uint64_t *cmd, uint16_t lmt_id,\n+\t\t\tuintptr_t lmt_addr, uint8_t sched_type,\n+\t\t\tconst uint64_t *txq_data, const uint32_t flags)\n {\n \tuint16_t port[4], queue[4];\n \tuint16_t i, j, pkts, scalar;\n@@ -542,14 +542,16 @@ cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,\n \t\tif (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||\n \t\t    ((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {\n \t\t\tfor (j = 0; j < 4; j++)\n-\t\t\t\tcn10k_sso_tx_one(mbufs[i + j], cmd, lmt_id,\n-\t\t\t\t\t\t lmt_addr, sched_type, base,\n-\t\t\t\t\t\t txq_data, flags);\n+\t\t\t\tcn10k_sso_tx_one(ws, mbufs[i + j], cmd, lmt_id,\n+\t\t\t\t\t\t lmt_addr, sched_type, txq_data,\n+\t\t\t\t\t\t flags);\n \t\t} else {\n-\t\t\ttxq = (struct cn10k_eth_txq *)\n-\t\t\t\ttxq_data[port[0]][queue[0]];\n-\t\t\tcn10k_nix_xmit_pkts_vector(txq, &mbufs[i], 4, cmd,\n-\t\t\t\t\t\t   base + SSOW_LF_GWS_TAG,\n+\t\t\ttxq = (struct cn10k_eth_txq\n+\t\t\t\t       *)(txq_data[(txq_data[port[0]] >> 48) +\n+\t\t\t\t\t\t   queue[0]] &\n+\t\t\t\t\t  (BIT_ULL(48) - 1));\n+\t\t\tcn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws,\n+\t\t\t\t\t\t   &mbufs[i], 4, cmd,\n \t\t\t\t\t\t   flags | NIX_TX_VWQE_F);\n \t\t}\n \t}\n@@ -557,15 +559,14 @@ cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,\n \tmbufs += i;\n\n \tfor (i = 0; i < scalar; i++) {\n-\t\tcn10k_sso_tx_one(mbufs[i], cmd, lmt_id, lmt_addr, sched_type,\n-\t\t\t\t base, txq_data, flags);\n+\t\tcn10k_sso_tx_one(ws, mbufs[i], cmd, lmt_id, lmt_addr,\n+\t\t\t\t sched_type, txq_data, flags);\n \t}\n }\n\n static __rte_always_inline uint16_t\n cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,\n-\t\t       uint64_t *cmd,\n-\t\t       const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],\n+\t\t       uint64_t *cmd, const uint64_t *txq_data,\n \t\t       const uint32_t flags)\n {\n \tstruct cn10k_eth_txq *txq;\n@@ -582,17 +583,19 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\tuint64_t meta = *(uint64_t *)ev->vec;\n\n \t\tif (meta & BIT(31)) {\n-\t\t\ttxq = (struct cn10k_eth_txq *)\n-\t\t\t\ttxq_data[meta >> 32][meta >> 48];\n-\n-\t\t\tcn10k_nix_xmit_pkts_vector(\n-\t\t\t\ttxq, mbufs, meta & 0xFFFF, cmd,\n-\t\t\t\tws->tx_base + SSOW_LF_GWS_TAG,\n-\t\t\t\tflags | NIX_TX_VWQE_F);\n+\t\t\ttxq = (struct cn10k_eth_txq\n+\t\t\t\t       *)(txq_data[(txq_data[meta >> 32] >>\n+\t\t\t\t\t\t    48) +\n+\t\t\t\t\t\t   (meta >> 48)] &\n+\t\t\t\t\t  (BIT_ULL(48) - 1));\n+\n+\t\t\tcn10k_nix_xmit_pkts_vector(txq, (uint64_t *)ws, mbufs,\n+\t\t\t\t\t\t   meta & 0xFFFF, cmd,\n+\t\t\t\t\t\t   flags | NIX_TX_VWQE_F);\n \t\t} else {\n \t\t\tcn10k_sso_vwqe_split_tx(\n-\t\t\t\tmbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,\n-\t\t\t\tev->sched_type, ws->tx_base, txq_data, flags);\n+\t\t\t\tws, mbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,\n+\t\t\t\tev->sched_type, txq_data, flags);\n \t\t}\n \t\trte_mempool_put(rte_mempool_from_obj(ev->vec), ev->vec);\n \t\treturn (meta & 0xFFFF);\n@@ -600,16 +603,16 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,\n\n \tm = ev->mbuf;\n \tref_cnt = m->refcnt;\n-\tcn10k_sso_tx_one(m, cmd, lmt_id, lmt_addr, ev->sched_type, ws->tx_base,\n-\t\t\t txq_data, flags);\n+\tcn10k_sso_tx_one(ws, m, cmd, lmt_id, lmt_addr, ev->sched_type, txq_data,\n+\t\t\t flags);\n\n \tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n \t\tif (ref_cnt > 1)\n \t\t\treturn 1;\n \t}\n\n-\tcnxk_sso_hws_swtag_flush(ws->tx_base + SSOW_LF_GWS_TAG,\n-\t\t\t\t ws->tx_base + SSOW_LF_GWS_OP_SWTAG_FLUSH);\n+\tcnxk_sso_hws_swtag_flush(ws->base + SSOW_LF_GWS_TAG,\n+\t\t\t\t ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);\n \treturn 1;\n }\n\n@@ -631,9 +634,7 @@ NIX_TX_FASTPATH_MODES\n                                                                                \\\n \t\tRTE_SET_USED(nb_events);                                       \\\n \t\treturn cn10k_sso_hws_event_tx(                                 \\\n-\t\t\tws, &ev[0], cmd,                                       \\\n-\t\t\t(const uint64_t(*)[RTE_MAX_QUEUES_PER_PORT]) &         \\\n-\t\t\t\tws->tx_adptr_data,                             \\\n+\t\t\tws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data,  \\\n \t\t\tflags);                                                \\\n \t}\n\n@@ -646,9 +647,7 @@ NIX_TX_FASTPATH_MODES\n                                                                                \\\n \t\tRTE_SET_USED(nb_events);                                       \\\n \t\treturn cn10k_sso_hws_event_tx(                                 \\\n-\t\t\tws, &ev[0], cmd,                                       \\\n-\t\t\t(const uint64_t(*)[RTE_MAX_QUEUES_PER_PORT]) &         \\\n-\t\t\t\tws->tx_adptr_data,                             \\\n+\t\t\tws, &ev[0], cmd, (const uint64_t *)ws->tx_adptr_data,  \\\n \t\t\t(flags) | NIX_TX_MULTI_SEG_F);                         \\\n \t}\n\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 7858e37146..98294be11f 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -259,17 +259,14 @@ cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)\n \t\t\t\tws_cookie,\n \t\t\t\tsizeof(struct cnxk_sso_hws_cookie) +\n \t\t\t\t\tsizeof(struct cn9k_sso_hws_dual) +\n-\t\t\t\t\t(sizeof(uint64_t) *\n-\t\t\t\t\t (dev->max_port_id + 1) *\n-\t\t\t\t\t RTE_MAX_QUEUES_PER_PORT),\n+\t\t\t\t\tdev->tx_adptr_data_sz,\n \t\t\t\tRTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n \t\t\tif (ws_cookie == NULL)\n \t\t\t\treturn -ENOMEM;\n \t\t\tdws = RTE_PTR_ADD(ws_cookie,\n \t\t\t\t\t  sizeof(struct cnxk_sso_hws_cookie));\n \t\t\tmemcpy(&dws->tx_adptr_data, dev->tx_adptr_data,\n-\t\t\t       sizeof(uint64_t) * (dev->max_port_id + 1) *\n-\t\t\t\t       RTE_MAX_QUEUES_PER_PORT);\n+\t\t\t       dev->tx_adptr_data_sz);\n \t\t\tevent_dev->data->ports[i] = dws;\n \t\t} else {\n \t\t\tstruct cn9k_sso_hws *ws = event_dev->data->ports[i];\n@@ -280,17 +277,14 @@ cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)\n \t\t\t\tws_cookie,\n \t\t\t\tsizeof(struct cnxk_sso_hws_cookie) +\n \t\t\t\t\tsizeof(struct cn9k_sso_hws_dual) +\n-\t\t\t\t\t(sizeof(uint64_t) *\n-\t\t\t\t\t (dev->max_port_id + 1) *\n-\t\t\t\t\t RTE_MAX_QUEUES_PER_PORT),\n+\t\t\t\t\tdev->tx_adptr_data_sz,\n \t\t\t\tRTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n \t\t\tif (ws_cookie == NULL)\n \t\t\t\treturn -ENOMEM;\n \t\t\tws = RTE_PTR_ADD(ws_cookie,\n \t\t\t\t\t sizeof(struct cnxk_sso_hws_cookie));\n \t\t\tmemcpy(&ws->tx_adptr_data, dev->tx_adptr_data,\n-\t\t\t       sizeof(uint64_t) * (dev->max_port_id + 1) *\n-\t\t\t\t       RTE_MAX_QUEUES_PER_PORT);\n+\t\t\t       dev->tx_adptr_data_sz);\n \t\t\tevent_dev->data->ports[i] = ws;\n \t\t}\n \t}\n@@ -1006,17 +1000,36 @@ cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,\n \t\t\t      const struct rte_eth_dev *eth_dev,\n \t\t\t      int32_t tx_queue_id)\n {\n+\tstruct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tuint64_t tx_offloads;\n \tint rc;\n\n \tRTE_SET_USED(id);\n \trc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);\n \tif (rc < 0)\n \t\treturn rc;\n+\n+\t/* Can't enable tstamp if all the ports don't have it enabled. */\n+\ttx_offloads = cnxk_eth_dev->tx_offload_flags;\n+\tif (dev->tx_adptr_configured) {\n+\t\tuint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);\n+\t\tuint8_t tstmp_ena =\n+\t\t\t!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);\n+\n+\t\tif (tstmp_ena && !tstmp_req)\n+\t\t\tdev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);\n+\t\telse if (!tstmp_ena && tstmp_req)\n+\t\t\ttx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);\n+\t}\n+\n+\tdev->tx_offloads |= tx_offloads;\n \tcn9k_sso_txq_fc_update(eth_dev, tx_queue_id, true);\n \trc = cn9k_sso_updt_tx_adptr_data(event_dev);\n \tif (rc < 0)\n \t\treturn rc;\n \tcn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);\n+\tdev->tx_adptr_configured = 1;\n\n \treturn 0;\n }\ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nindex a46d4e786a..0f58e00e7f 100644\n--- a/drivers/event/cnxk/cn9k_worker.h\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -603,20 +603,13 @@ cn9k_sso_txq_fc_wait(const struct cn9k_eth_txq *txq)\n \t\t;\n }\n\n-static __rte_always_inline const struct cn9k_eth_txq *\n-cn9k_sso_hws_xtract_meta(struct rte_mbuf *m,\n-\t\t\t const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT])\n+static __rte_always_inline struct cn9k_eth_txq *\n+cn9k_sso_hws_xtract_meta(struct rte_mbuf *m, uint64_t *txq_data)\n {\n-\treturn (const struct cn9k_eth_txq *)\n-\t\ttxq_data[m->port][rte_event_eth_tx_adapter_txq_get(m)];\n-}\n-\n-static __rte_always_inline void\n-cn9k_sso_hws_prepare_pkt(const struct cn9k_eth_txq *txq, struct rte_mbuf *m,\n-\t\t\t uint64_t *cmd, const uint32_t flags)\n-{\n-\troc_lmt_mov(cmd, txq->cmd, cn9k_nix_tx_ext_subs(flags));\n-\tcn9k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt);\n+\treturn (struct cn9k_eth_txq\n+\t\t\t*)(txq_data[(txq_data[m->port] >> 48) +\n+\t\t\t\t    rte_event_eth_tx_adapter_txq_get(m)] &\n+\t\t\t   (BIT_ULL(48) - 1));\n }\n\n #if defined(RTE_ARCH_ARM64)\n@@ -673,7 +666,7 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base,\n \tnixtx += BIT_ULL(7);\n \tnixtx = (nixtx - 1) & ~(BIT_ULL(7) - 1);\n\n-\troc_lmt_mov((void *)(nixtx + 16), cmd, cn9k_nix_tx_ext_subs(flags));\n+\troc_lmt_mov_nv((void *)(nixtx + 16), cmd, cn9k_nix_tx_ext_subs(flags));\n\n \t/* Load opcode and cptr already prepared at pkt metadata set */\n \tpkt_len -= l2_len;\n@@ -760,12 +753,11 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base,\n\n static __rte_always_inline uint16_t\n cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,\n-\t\t      const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],\n-\t\t      const uint32_t flags)\n+\t\t      uint64_t *txq_data, const uint32_t flags)\n {\n \tstruct rte_mbuf *m = ev->mbuf;\n-\tconst struct cn9k_eth_txq *txq;\n \tuint16_t ref_cnt = m->refcnt;\n+\tstruct cn9k_eth_txq *txq;\n\n \t/* Perform header writes before barrier for TSO */\n \tcn9k_nix_xmit_prepare_tso(m, flags);\n@@ -778,7 +770,8 @@ cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,\n \t    !(flags & NIX_TX_OFFLOAD_SECURITY_F))\n \t\trte_io_wmb();\n \ttxq = cn9k_sso_hws_xtract_meta(m, txq_data);\n-\tcn9k_sso_hws_prepare_pkt(txq, m, cmd, flags);\n+\tcn9k_nix_tx_skeleton(txq, cmd, flags, 0);\n+\tcn9k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt);\n\n \tif (flags & NIX_TX_OFFLOAD_SECURITY_F) {\n \t\tuint64_t ol_flags = m->ol_flags;\n@@ -800,6 +793,8 @@ cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,\n\n \tif (flags & NIX_TX_MULTI_SEG_F) {\n \t\tconst uint16_t segdw = cn9k_nix_prepare_mseg(m, cmd, flags);\n+\t\tcn9k_nix_xmit_prepare_tstamp(txq, cmd, m->ol_flags, segdw,\n+\t\t\t\t\t     flags);\n \t\tif (!CNXK_TT_FROM_EVENT(ev->event)) {\n \t\t\tcn9k_nix_xmit_mseg_prep_lmt(cmd, txq->lmt_addr, segdw);\n \t\t\troc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);\n@@ -812,6 +807,7 @@ cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,\n \t\t\t\t\t       segdw);\n \t\t}\n \t} else {\n+\t\tcn9k_nix_xmit_prepare_tstamp(txq, cmd, m->ol_flags, 4, flags);\n \t\tif (!CNXK_TT_FROM_EVENT(ev->event)) {\n \t\t\tcn9k_nix_xmit_prep_lmt(cmd, txq->lmt_addr, flags);\n \t\t\troc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);\n@@ -858,11 +854,9 @@ NIX_TX_FASTPATH_MODES\n \t\tuint64_t cmd[sz];                                              \\\n                                                                                \\\n \t\tRTE_SET_USED(nb_events);                                       \\\n-\t\treturn cn9k_sso_hws_event_tx(                                  \\\n-\t\t\tws->base, &ev[0], cmd,                                 \\\n-\t\t\t(const uint64_t(*)[RTE_MAX_QUEUES_PER_PORT]) &         \\\n-\t\t\t\tws->tx_adptr_data,                             \\\n-\t\t\tflags);                                                \\\n+\t\treturn cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd,            \\\n+\t\t\t\t\t     (uint64_t *)ws->tx_adptr_data,    \\\n+\t\t\t\t\t     flags);                           \\\n \t}\n\n #define SSO_TX_SEG(fn, sz, flags)                                              \\\n@@ -873,11 +867,9 @@ NIX_TX_FASTPATH_MODES\n \t\tstruct cn9k_sso_hws *ws = port;                                \\\n                                                                                \\\n \t\tRTE_SET_USED(nb_events);                                       \\\n-\t\treturn cn9k_sso_hws_event_tx(                                  \\\n-\t\t\tws->base, &ev[0], cmd,                                 \\\n-\t\t\t(const uint64_t(*)[RTE_MAX_QUEUES_PER_PORT]) &         \\\n-\t\t\t\tws->tx_adptr_data,                             \\\n-\t\t\t(flags) | NIX_TX_MULTI_SEG_F);                         \\\n+\t\treturn cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd,            \\\n+\t\t\t\t\t     (uint64_t *)ws->tx_adptr_data,    \\\n+\t\t\t\t\t     (flags) | NIX_TX_MULTI_SEG_F);    \\\n \t}\n\n #define SSO_DUAL_TX(fn, sz, flags)                                             \\\n@@ -888,11 +880,9 @@ NIX_TX_FASTPATH_MODES\n \t\tuint64_t cmd[sz];                                              \\\n                                                                                \\\n \t\tRTE_SET_USED(nb_events);                                       \\\n-\t\treturn cn9k_sso_hws_event_tx(                                  \\\n-\t\t\tws->base[!ws->vws], &ev[0], cmd,                       \\\n-\t\t\t(const uint64_t(*)[RTE_MAX_QUEUES_PER_PORT]) &         \\\n-\t\t\t\tws->tx_adptr_data,                             \\\n-\t\t\tflags);                                                \\\n+\t\treturn cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd,  \\\n+\t\t\t\t\t     (uint64_t *)ws->tx_adptr_data,    \\\n+\t\t\t\t\t     flags);                           \\\n \t}\n\n #define SSO_DUAL_TX_SEG(fn, sz, flags)                                         \\\n@@ -903,11 +893,9 @@ NIX_TX_FASTPATH_MODES\n \t\tstruct cn9k_sso_hws_dual *ws = port;                           \\\n                                                                                \\\n \t\tRTE_SET_USED(nb_events);                                       \\\n-\t\treturn cn9k_sso_hws_event_tx(                                  \\\n-\t\t\tws->base[!ws->vws], &ev[0], cmd,                       \\\n-\t\t\t(const uint64_t(*)[RTE_MAX_QUEUES_PER_PORT]) &         \\\n-\t\t\t\tws->tx_adptr_data,                             \\\n-\t\t\t(flags) | NIX_TX_MULTI_SEG_F);                         \\\n+\t\treturn cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd,  \\\n+\t\t\t\t\t     (uint64_t *)ws->tx_adptr_data,    \\\n+\t\t\t\t\t     (flags) | NIX_TX_MULTI_SEG_F);    \\\n \t}\n\n #endif\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 4652b58a84..b26df58588 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -99,7 +99,10 @@ struct cnxk_sso_evdev {\n \tuint16_t rx_adptr_pool_cnt;\n \tuint64_t *rx_adptr_pools;\n \tuint64_t *tx_adptr_data;\n+\tsize_t tx_adptr_data_sz;\n \tuint16_t max_port_id;\n+\tuint16_t max_queue_id[RTE_MAX_ETHPORTS];\n+\tuint8_t tx_adptr_configured;\n \tuint16_t tim_adptr_ring_cnt;\n \tuint16_t *timer_adptr_rings;\n \tuint64_t *timer_adptr_sz;\n@@ -131,8 +134,8 @@ struct cn10k_sso_hws {\n \tuint64_t *fc_mem;\n \tuintptr_t grp_base;\n \t/* Tx Fastpath data */\n-\tuint64_t tx_base __rte_cache_aligned;\n-\tuintptr_t lmt_base;\n+\tuintptr_t lmt_base __rte_cache_aligned;\n+\tuint64_t lso_tun_fmt;\n \tuint8_t tx_adptr_data[];\n } __rte_cache_aligned;\n\n@@ -149,7 +152,8 @@ struct cn9k_sso_hws {\n \tuint64_t *fc_mem;\n \tuintptr_t grp_base;\n \t/* Tx Fastpath data */\n-\tuint8_t tx_adptr_data[] __rte_cache_aligned;\n+\tuint64_t lso_tun_fmt __rte_cache_aligned;\n+\tuint8_t tx_adptr_data[];\n } __rte_cache_aligned;\n\n struct cn9k_sso_hws_dual {\n@@ -165,7 +169,8 @@ struct cn9k_sso_hws_dual {\n \tuint64_t *fc_mem;\n \tuintptr_t grp_base;\n \t/* Tx Fastpath data */\n-\tuint8_t tx_adptr_data[] __rte_cache_aligned;\n+\tuint64_t lso_tun_fmt __rte_cache_aligned;\n+\tuint8_t tx_adptr_data[];\n } __rte_cache_aligned;\n\n struct cnxk_sso_hws_cookie {\ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nindex fdcd68ca63..29dce44d39 100644\n--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -345,24 +345,136 @@ cnxk_sso_updt_tx_queue_data(const struct rte_eventdev *event_dev,\n \t\t\t    void *txq)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tuint16_t max_queue_id = dev->max_queue_id[eth_port_id];\n \tuint16_t max_port_id = dev->max_port_id;\n-\tuint64_t *txq_data = dev->tx_adptr_data;\n-\n-\tif (txq_data == NULL || eth_port_id > max_port_id) {\n-\t\tmax_port_id = RTE_MAX(max_port_id, eth_port_id);\n-\t\ttxq_data = rte_realloc_socket(\n-\t\t\ttxq_data,\n-\t\t\t(sizeof(uint64_t) * (max_port_id + 1) *\n-\t\t\t RTE_MAX_QUEUES_PER_PORT),\n-\t\t\tRTE_CACHE_LINE_SIZE, event_dev->data->socket_id);\n+\tuint64_t offset = 0, row = 0;\n+\tuint64_t *txq_data = NULL;\n+\tsize_t size = 0;\n+\tint i, j;\n+\n+\tif (((uint64_t)txq) & 0xFFFF000000000000)\n+\t\treturn -EINVAL;\n+\n+\tif (dev->tx_adptr_data == NULL) {\n+\t\tsize = (eth_port_id + 1);\n+\t\tsize += (eth_port_id + tx_queue_id);\n+\t\trow = 2 * eth_port_id;\n+\t} else {\n+\t\tif (eth_port_id > max_port_id) {\n+\t\t\tsize = (RTE_MAX(eth_port_id, dev->max_queue_id[0]) + 1);\n+\t\t\tfor (i = 1; i < eth_port_id; i++)\n+\t\t\t\tsize += (dev->max_queue_id[i] + 1);\n+\t\t\trow = size;\n+\t\t\tsize += (tx_queue_id + 1);\n+\t\t} else if (tx_queue_id > max_queue_id) {\n+\t\t\tsize = !eth_port_id ? tx_queue_id + 1 :\n+\t\t\t\t\t\t    RTE_MAX(max_port_id,\n+\t\t\t\t\t\t      dev->max_queue_id[0]) +\n+\t\t\t\t\t\t      1;\n+\t\t\tfor (i = 1; i < max_port_id + 1; i++) {\n+\t\t\t\tif (i == eth_port_id) {\n+\t\t\t\t\trow = size;\n+\t\t\t\t\tsize += tx_queue_id + 1;\n+\t\t\t\t} else {\n+\t\t\t\t\tsize += dev->max_queue_id[i] + 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tsize *= sizeof(uint64_t);\n+\n+\tif (size) {\n+\t\tuint64_t *otxq_data = dev->tx_adptr_data;\n+\n+\t\ttxq_data = malloc(size);\n \t\tif (txq_data == NULL)\n \t\t\treturn -ENOMEM;\n+\t\tmemset(txq_data, 0, size);\n+\t\ttxq_data[eth_port_id] = ((uint64_t)row) << 48;\n+\t\ttxq_data[row + tx_queue_id] = (uint64_t)txq;\n+\n+\t\tif (otxq_data != NULL) {\n+\t\t\tfor (i = 0; i < dev->max_queue_id[0] + 1; i++) {\n+\t\t\t\ttxq_data[i] |= (otxq_data[i] &\n+\t\t\t\t\t\t~((BIT_ULL(16) - 1) << 48));\n+\t\t\t}\n+\n+\t\t\tif (eth_port_id > max_port_id) {\n+\t\t\t\tdev->max_queue_id[0] = RTE_MAX(\n+\t\t\t\t\tdev->max_queue_id[0], eth_port_id);\n+\t\t\t\tdev->max_port_id =\n+\t\t\t\t\tRTE_MAX(dev->max_port_id, eth_port_id);\n+\n+\t\t\t\tfor (i = 1; i < eth_port_id; i++) {\n+\t\t\t\t\toffset +=\n+\t\t\t\t\t\t(dev->max_queue_id[i - 1] + 1);\n+\t\t\t\t\ttxq_data[i] |= offset << 48;\n+\t\t\t\t\tfor (j = 0;\n+\t\t\t\t\t     (i < dev->max_port_id) &&\n+\t\t\t\t\t     (j < dev->max_queue_id[i] + 1);\n+\t\t\t\t\t     j++) {\n+\n+\t\t\t\t\t\ttxq_data[offset + j] = otxq_data\n+\t\t\t\t\t\t\t[(otxq_data[i] >> 48) +\n+\t\t\t\t\t\t\t j];\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t\tdev->max_queue_id[eth_port_id] =\n+\t\t\t\t\tRTE_MAX(dev->max_queue_id[eth_port_id],\n+\t\t\t\t\t\ttx_queue_id);\n+\t\t\t} else if (tx_queue_id > max_queue_id) {\n+\t\t\t\tdev->max_queue_id[eth_port_id] =\n+\t\t\t\t\tRTE_MAX(dev->max_queue_id[eth_port_id],\n+\t\t\t\t\t\ttx_queue_id);\n+\t\t\t\tdev->max_port_id =\n+\t\t\t\t\tRTE_MAX(max_port_id, eth_port_id);\n+\t\t\t\tfor (i = 1; i < max_port_id + 1; i++) {\n+\t\t\t\t\toffset +=\n+\t\t\t\t\t\t(dev->max_queue_id[i - 1] + 1);\n+\t\t\t\t\ttxq_data[i] |= offset << 48;\n+\t\t\t\t\tfor (j = 0;\n+\t\t\t\t\t     j < dev->max_queue_id[i] + 1;\n+\t\t\t\t\t     j++) {\n+\t\t\t\t\t\tif (i == eth_port_id &&\n+\t\t\t\t\t\t    j > max_queue_id)\n+\t\t\t\t\t\t\tcontinue;\n+\t\t\t\t\t\ttxq_data[offset + j] = otxq_data\n+\t\t\t\t\t\t\t[(otxq_data[i] >> 48) +\n+\t\t\t\t\t\t\t j];\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else {\n+\t\t\tdev->max_queue_id[0] =\n+\t\t\t\tRTE_MAX(dev->max_queue_id[0], eth_port_id);\n+\t\t\tfor (i = 1; i < eth_port_id; i++) {\n+\t\t\t\toffset += (dev->max_queue_id[i - 1] + 1);\n+\t\t\t\ttxq_data[i] |= offset << 48;\n+\n+\t\t\t\tfor (j = 0; (i < max_port_id) &&\n+\t\t\t\t\t    (j < dev->max_queue_id[i] + 1);\n+\t\t\t\t     j++) {\n+\n+\t\t\t\t\ttxq_data[offset + j] =\n+\t\t\t\t\t\totxq_data[(otxq_data[i] >> 48) +\n+\t\t\t\t\t\t\t  j];\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tdev->max_port_id =\n+\t\t\t\tRTE_MAX(dev->max_port_id, eth_port_id);\n+\t\t\tdev->max_queue_id[eth_port_id] = RTE_MAX(\n+\t\t\t\tdev->max_queue_id[eth_port_id], tx_queue_id);\n+\t\t}\n+\t\tdev->tx_adptr_data_sz = size;\n+\t\tfree(otxq_data);\n+\t\tdev->tx_adptr_data = txq_data;\n+\t} else {\n+\t\ttxq_data = dev->tx_adptr_data;\n+\t\trow = txq_data[eth_port_id] >> 48;\n+\t\ttxq_data[row + tx_queue_id] |= (uint64_t)txq;\n \t}\n\n-\t((uint64_t(*)[RTE_MAX_QUEUES_PER_PORT])\n-\t\t txq_data)[eth_port_id][tx_queue_id] = (uint64_t)txq;\n-\tdev->max_port_id = max_port_id;\n-\tdev->tx_adptr_data = txq_data;\n \treturn 0;\n }\n\n@@ -372,7 +484,6 @@ cnxk_sso_tx_adapter_queue_add(const struct rte_eventdev *event_dev,\n \t\t\t      int32_t tx_queue_id)\n {\n \tstruct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;\n-\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tstruct roc_nix_sq *sq;\n \tint i, ret;\n \tvoid *txq;\n@@ -388,8 +499,6 @@ cnxk_sso_tx_adapter_queue_add(const struct rte_eventdev *event_dev,\n \t\t\tevent_dev, eth_dev->data->port_id, tx_queue_id, txq);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n-\n-\t\tdev->tx_offloads |= cnxk_eth_dev->tx_offload_flags;\n \t}\n\n \treturn 0;\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nindex 8378cbffc2..9bb08e1824 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.c\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -131,53 +131,31 @@ static void\n nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq,\n \t\t      uint16_t qid)\n {\n-\tstruct nix_send_ext_s *send_hdr_ext;\n \tunion nix_send_hdr_w0_u send_hdr_w0;\n-\tstruct nix_send_mem_s *send_mem;\n-\tunion nix_send_sg_s sg_w0;\n-\n-\tRTE_SET_USED(dev);\n\n \t/* Initialize the fields based on basic single segment packet */\n-\tmemset(&txq->cmd, 0, sizeof(txq->cmd));\n \tsend_hdr_w0.u = 0;\n-\tsg_w0.u = 0;\n-\n \tif (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {\n \t\t/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */\n \t\tsend_hdr_w0.sizem1 = 2;\n-\n-\t\tsend_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[0];\n-\t\tsend_hdr_ext->w0.subdc = NIX_SUBDC_EXT;\n \t\tif (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n \t\t\t/* Default: one seg packet would have:\n \t\t\t * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)\n \t\t\t * => 8/2 - 1 = 3\n \t\t\t */\n \t\t\tsend_hdr_w0.sizem1 = 3;\n-\t\t\tsend_hdr_ext->w0.tstmp = 1;\n\n \t\t\t/* To calculate the offset for send_mem,\n \t\t\t * send_hdr->w0.sizem1 * 2\n \t\t\t */\n-\t\t\tsend_mem = (struct nix_send_mem_s *)(txq->cmd + 2);\n-\t\t\tsend_mem->w0.subdc = NIX_SUBDC_MEM;\n-\t\t\tsend_mem->w0.alg = NIX_SENDMEMALG_SETTSTMP;\n-\t\t\tsend_mem->addr = dev->tstamp.tx_tstamp_iova;\n+\t\t\ttxq->ts_mem = dev->tstamp.tx_tstamp_iova;\n \t\t}\n \t} else {\n \t\t/* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */\n \t\tsend_hdr_w0.sizem1 = 1;\n \t}\n-\n \tsend_hdr_w0.sq = qid;\n-\tsg_w0.subdc = NIX_SUBDC_SG;\n-\tsg_w0.segs = 1;\n-\tsg_w0.ld_type = NIX_SENDLDTYPE_LDD;\n-\n \ttxq->send_hdr_w0 = send_hdr_w0.u;\n-\ttxq->sg_w0 = sg_w0.u;\n-\n \trte_wmb();\n }\n\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h\nindex c2a46ad7ec..93b0df96b3 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.h\n+++ b/drivers/net/cnxk/cn10k_ethdev.h\n@@ -9,7 +9,6 @@\n\n struct cn10k_eth_txq {\n \tuint64_t send_hdr_w0;\n-\tuint64_t sg_w0;\n \tint64_t fc_cache_pkts;\n \tuint64_t *fc_mem;\n \tuintptr_t lmt_base;\n@@ -20,8 +19,8 @@ struct cn10k_eth_txq {\n \tuint64_t sa_base;\n \tuint64_t *cpt_fc;\n \tuint16_t cpt_desc;\n-\tuint64_t cmd[4];\n \tuint64_t lso_tun_fmt;\n+\tuint64_t ts_mem;\n } __plt_cache_aligned;\n\n struct cn10k_eth_rxq {\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex 6de8b18b47..b3034c72cb 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -186,23 +186,26 @@ cn10k_cpt_tx_steor_data(void)\n }\n\n static __rte_always_inline void\n-cn10k_nix_tx_skeleton(const struct cn10k_eth_txq *txq, uint64_t *cmd,\n-\t\t      const uint16_t flags)\n+cn10k_nix_tx_skeleton(struct cn10k_eth_txq *txq, uint64_t *cmd,\n+\t\t      const uint16_t flags, const uint16_t static_sz)\n {\n-\t/* Send hdr */\n-\tcmd[0] = txq->send_hdr_w0;\n+\tif (static_sz)\n+\t\tcmd[0] = txq->send_hdr_w0;\n+\telse\n+\t\tcmd[0] = (txq->send_hdr_w0 & 0xFFFFF00000000000) |\n+\t\t\t ((uint64_t)(cn10k_nix_tx_ext_subs(flags) + 1) << 40);\n \tcmd[1] = 0;\n-\tcmd += 2;\n\n-\t/* Send ext if present */\n \tif (flags & NIX_TX_NEED_EXT_HDR) {\n-\t\t*(__uint128_t *)cmd = *(const __uint128_t *)txq->cmd;\n-\t\tcmd += 2;\n+\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F)\n+\t\t\tcmd[2] = (NIX_SUBDC_EXT << 60) | BIT_ULL(15);\n+\t\telse\n+\t\t\tcmd[2] = NIX_SUBDC_EXT << 60;\n+\t\tcmd[3] = 0;\n+\t\tcmd[4] = (NIX_SUBDC_SG << 60) | BIT_ULL(48);\n+\t} else {\n+\t\tcmd[2] = (NIX_SUBDC_SG << 60) | BIT_ULL(48);\n \t}\n-\n-\t/* Send sg */\n-\tcmd[0] = txq->sg_w0;\n-\tcmd[1] = 0;\n }\n\n static __rte_always_inline void\n@@ -718,41 +721,29 @@ cn10k_nix_xmit_mv_lmt_base(uintptr_t lmt_addr, uint64_t *cmd,\n }\n\n static __rte_always_inline void\n-cn10k_nix_xmit_prepare_tstamp(uintptr_t lmt_addr, const uint64_t *cmd,\n+cn10k_nix_xmit_prepare_tstamp(struct cn10k_eth_txq *txq, uintptr_t lmt_addr,\n \t\t\t      const uint64_t ol_flags, const uint16_t no_segdw,\n \t\t\t      const uint16_t flags)\n {\n \tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n-\t\tconst uint8_t is_ol_tstamp = !(ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST);\n-\t\tstruct nix_send_ext_s *send_hdr_ext =\n-\t\t\t(struct nix_send_ext_s *)lmt_addr + 16;\n+\t\tconst uint8_t is_ol_tstamp =\n+\t\t\t!(ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST);\n \t\tuint64_t *lmt = (uint64_t *)lmt_addr;\n \t\tuint16_t off = (no_segdw - 1) << 1;\n \t\tstruct nix_send_mem_s *send_mem;\n\n \t\tsend_mem = (struct nix_send_mem_s *)(lmt + off);\n-\t\tsend_hdr_ext->w0.subdc = NIX_SUBDC_EXT;\n-\t\tsend_hdr_ext->w0.tstmp = 1;\n-\t\tif (flags & NIX_TX_MULTI_SEG_F) {\n-\t\t\t/* Retrieving the default desc values */\n-\t\t\tlmt[off] = cmd[2];\n-\n-\t\t\t/* Using compiler barier to avoid voilation of C\n-\t\t\t * aliasing rules.\n-\t\t\t */\n-\t\t\trte_compiler_barrier();\n-\t\t}\n-\n-\t\t/* Packets for which RTE_MBUF_F_TX_IEEE1588_TMST is not set, tx tstamp\n+\t\t/* Packets for which PKT_TX_IEEE1588_TMST is not set, tx tstamp\n \t\t * should not be recorded, hence changing the alg type to\n-\t\t * NIX_SENDMEMALG_SET and also changing send mem addr field to\n+\t\t * NIX_SENDMEMALG_SUB and also changing send mem addr field to\n \t\t * next 8 bytes as it corrpt the actual tx tstamp registered\n \t\t * address.\n \t\t */\n \t\tsend_mem->w0.subdc = NIX_SUBDC_MEM;\n-\t\tsend_mem->w0.alg = NIX_SENDMEMALG_SETTSTMP - (is_ol_tstamp);\n+\t\tsend_mem->w0.alg =\n+\t\t\tNIX_SENDMEMALG_SETTSTMP + (is_ol_tstamp << 3);\n \t\tsend_mem->addr =\n-\t\t\t(rte_iova_t)(((uint64_t *)cmd[3]) + is_ol_tstamp);\n+\t\t\t(rte_iova_t)(((uint64_t *)txq->ts_mem) + is_ol_tstamp);\n \t}\n }\n\n@@ -841,8 +832,8 @@ cn10k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n }\n\n static __rte_always_inline uint16_t\n-cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n-\t\t    uint64_t *cmd, uintptr_t base, const uint16_t flags)\n+cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, struct rte_mbuf **tx_pkts,\n+\t\t    uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n {\n \tstruct cn10k_eth_txq *txq = tx_queue;\n \tconst rte_iova_t io_addr = txq->io_addr;\n@@ -863,9 +854,8 @@ cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n \t\t/* Reduce the cached count */\n \t\ttxq->fc_cache_pkts -= pkts;\n \t}\n-\n \t/* Get cmd skeleton */\n-\tcn10k_nix_tx_skeleton(txq, cmd, flags);\n+\tcn10k_nix_tx_skeleton(txq, cmd, flags, !(flags & NIX_TX_VWQE_F));\n\n \tif (flags & NIX_TX_OFFLOAD_TSO_F)\n \t\tlso_tun_fmt = txq->lso_tun_fmt;\n@@ -909,14 +899,14 @@ cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n\n \t\t/* Move NIX desc to LMT/NIXTX area */\n \t\tcn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);\n-\t\tcn10k_nix_xmit_prepare_tstamp(laddr, &txq->cmd[0],\n-\t\t\t\t\t      tx_pkts[i]->ol_flags, 4, flags);\n+\t\tcn10k_nix_xmit_prepare_tstamp(txq, laddr, tx_pkts[i]->ol_flags,\n+\t\t\t\t\t      4, flags);\n \t\tif (!(flags & NIX_TX_OFFLOAD_SECURITY_F) || !sec)\n \t\t\tlnum++;\n \t}\n\n \tif (flags & NIX_TX_VWQE_F)\n-\t\troc_sso_hws_head_wait(base);\n+\t\troc_sso_hws_head_wait(ws[0]);\n\n \tleft -= burst;\n \ttx_pkts += burst;\n@@ -967,9 +957,9 @@ cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n }\n\n static __rte_always_inline uint16_t\n-cn10k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t uint16_t pkts, uint64_t *cmd, uintptr_t base,\n-\t\t\t const uint16_t flags)\n+cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws,\n+\t\t\t struct rte_mbuf **tx_pkts, uint16_t pkts,\n+\t\t\t uint64_t *cmd, const uint16_t flags)\n {\n \tstruct cn10k_eth_txq *txq = tx_queue;\n \tuintptr_t pa0, pa1, lbase = txq->lmt_base;\n@@ -987,12 +977,13 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuintptr_t laddr;\n \tbool sec;\n\n-\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n-\n-\tcn10k_nix_tx_skeleton(txq, cmd, flags);\n-\n-\t/* Reduce the cached count */\n-\ttxq->fc_cache_pkts -= pkts;\n+\tif (!(flags & NIX_TX_VWQE_F)) {\n+\t\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\t\t/* Reduce the cached count */\n+\t\ttxq->fc_cache_pkts -= pkts;\n+\t}\n+\t/* Get cmd skeleton */\n+\tcn10k_nix_tx_skeleton(txq, cmd, flags, !(flags & NIX_TX_VWQE_F));\n\n \tif (flags & NIX_TX_OFFLOAD_TSO_F)\n \t\tlso_tun_fmt = txq->lso_tun_fmt;\n@@ -1038,13 +1029,11 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n\n \t\t/* Move NIX desc to LMT/NIXTX area */\n \t\tcn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);\n-\n \t\t/* Store sg list directly on lmt line */\n \t\tsegdw = cn10k_nix_prepare_mseg(tx_pkts[i], (uint64_t *)laddr,\n \t\t\t\t\t       flags);\n-\t\tcn10k_nix_xmit_prepare_tstamp(laddr, &txq->cmd[0],\n-\t\t\t\t\t      tx_pkts[i]->ol_flags, segdw,\n-\t\t\t\t\t      flags);\n+\t\tcn10k_nix_xmit_prepare_tstamp(txq, laddr, tx_pkts[i]->ol_flags,\n+\t\t\t\t\t      segdw, flags);\n \t\tif (!(flags & NIX_TX_OFFLOAD_SECURITY_F) || !sec) {\n \t\t\tlnum++;\n \t\t\tdata128 |= (((__uint128_t)(segdw - 1)) << shft);\n@@ -1053,7 +1042,7 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t}\n\n \tif (flags & NIX_TX_VWQE_F)\n-\t\troc_sso_hws_head_wait(base);\n+\t\troc_sso_hws_head_wait(ws[0]);\n\n \tleft -= burst;\n \ttx_pkts += burst;\n@@ -1474,9 +1463,9 @@ cn10k_nix_xmit_store(struct rte_mbuf *mbuf, uint8_t segdw, uintptr_t laddr,\n }\n\n static __rte_always_inline uint16_t\n-cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t   uint16_t pkts, uint64_t *cmd, uintptr_t base,\n-\t\t\t   const uint16_t flags)\n+cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,\n+\t\t\t   struct rte_mbuf **tx_pkts, uint16_t pkts,\n+\t\t\t   uint64_t *cmd, const uint16_t flags)\n {\n \tuint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;\n \tuint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;\n@@ -1526,25 +1515,42 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\tcn10k_nix_xmit_prepare_tso(tx_pkts[i], flags);\n \t}\n\n-\tsenddesc01_w0 = vld1q_dup_u64(&txq->send_hdr_w0);\n+\tif (!(flags & NIX_TX_VWQE_F)) {\n+\t\tsenddesc01_w0 = vld1q_dup_u64(&txq->send_hdr_w0);\n+\t} else {\n+\t\tuint64_t w0 =\n+\t\t\t(txq->send_hdr_w0 & 0xFFFFF00000000000) |\n+\t\t\t((uint64_t)(cn10k_nix_tx_ext_subs(flags) + 1) << 40);\n+\n+\t\tsenddesc01_w0 = vdupq_n_u64(w0);\n+\t}\n \tsenddesc23_w0 = senddesc01_w0;\n+\n \tsenddesc01_w1 = vdupq_n_u64(0);\n \tsenddesc23_w1 = senddesc01_w1;\n-\tsgdesc01_w0 = vld1q_dup_u64(&txq->sg_w0);\n+\tsgdesc01_w0 = vdupq_n_u64((NIX_SUBDC_SG << 60) | BIT_ULL(48));\n \tsgdesc23_w0 = sgdesc01_w0;\n\n-\t/* Load command defaults into vector variables. */\n \tif (flags & NIX_TX_NEED_EXT_HDR) {\n-\t\tsendext01_w0 = vld1q_dup_u64(&txq->cmd[0]);\n-\t\tsendext23_w0 = sendext01_w0;\n-\t\tsendext01_w1 = vdupq_n_u64(12 | 12U << 24);\n-\t\tsendext23_w1 = sendext01_w1;\n \t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n-\t\t\tsendmem01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n+\t\t\tsendext01_w0 = vdupq_n_u64((NIX_SUBDC_EXT << 60) |\n+\t\t\t\t\t\t   BIT_ULL(15));\n+\t\t\tsendmem01_w0 =\n+\t\t\t\tvdupq_n_u64((NIX_SUBDC_MEM << 60) |\n+\t\t\t\t\t    (NIX_SENDMEMALG_SETTSTMP << 56));\n \t\t\tsendmem23_w0 = sendmem01_w0;\n-\t\t\tsendmem01_w1 = vld1q_dup_u64(&txq->cmd[3]);\n+\t\t\tsendmem01_w1 = vdupq_n_u64(txq->ts_mem);\n \t\t\tsendmem23_w1 = sendmem01_w1;\n+\t\t} else {\n+\t\t\tsendext01_w0 = vdupq_n_u64((NIX_SUBDC_EXT << 60));\n \t\t}\n+\t\tsendext23_w0 = sendext01_w0;\n+\n+\t\tif (flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)\n+\t\t\tsendext01_w1 = vdupq_n_u64(12 | 12U << 24);\n+\t\telse\n+\t\t\tsendext01_w1 = vdupq_n_u64(0);\n+\t\tsendext23_w1 = sendext01_w1;\n \t}\n\n \t/* Get LMT base address and LMT ID as lcore id */\n@@ -2577,7 +2583,7 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\twd.data[0] >>= 16;\n\n \tif (flags & NIX_TX_VWQE_F)\n-\t\troc_sso_hws_head_wait(base);\n+\t\troc_sso_hws_head_wait(ws[0]);\n\n \tleft -= burst;\n\n@@ -2640,12 +2646,11 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n\n \tif (unlikely(scalar)) {\n \t\tif (flags & NIX_TX_MULTI_SEG_F)\n-\t\t\tpkts += cn10k_nix_xmit_pkts_mseg(tx_queue, tx_pkts,\n-\t\t\t\t\t\t\t scalar, cmd, base,\n-\t\t\t\t\t\t\t flags);\n+\t\t\tpkts += cn10k_nix_xmit_pkts_mseg(tx_queue, ws, tx_pkts,\n+\t\t\t\t\t\t\t scalar, cmd, flags);\n \t\telse\n-\t\t\tpkts += cn10k_nix_xmit_pkts(tx_queue, tx_pkts, scalar,\n-\t\t\t\t\t\t    cmd, base, flags);\n+\t\t\tpkts += cn10k_nix_xmit_pkts(tx_queue, ws, tx_pkts,\n+\t\t\t\t\t\t    scalar, cmd, flags);\n \t}\n\n \treturn pkts;\n@@ -2653,16 +2658,16 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n\n #else\n static __rte_always_inline uint16_t\n-cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t   uint16_t pkts, uint64_t *cmd, uintptr_t base,\n-\t\t\t   const uint16_t flags)\n+cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,\n+\t\t\t   struct rte_mbuf **tx_pkts, uint16_t pkts,\n+\t\t\t   uint64_t *cmd, const uint16_t flags)\n {\n+\tRTE_SET_USED(ws);\n \tRTE_SET_USED(tx_queue);\n \tRTE_SET_USED(tx_pkts);\n \tRTE_SET_USED(pkts);\n \tRTE_SET_USED(cmd);\n \tRTE_SET_USED(flags);\n-\tRTE_SET_USED(base);\n \treturn 0;\n }\n #endif\n@@ -2896,7 +2901,7 @@ NIX_TX_FASTPATH_MODES\n \t\tif (((flags)&NIX_TX_OFFLOAD_TSO_F) &&                          \\\n \t\t    !((flags)&NIX_TX_OFFLOAD_L3_L4_CSUM_F))                    \\\n \t\t\treturn 0;                                              \\\n-\t\treturn cn10k_nix_xmit_pkts(tx_queue, tx_pkts, pkts, cmd, 0,    \\\n+\t\treturn cn10k_nix_xmit_pkts(tx_queue, NULL, tx_pkts, pkts, cmd, \\\n \t\t\t\t\t   flags);                             \\\n \t}\n\n@@ -2910,8 +2915,8 @@ NIX_TX_FASTPATH_MODES\n \t\tif (((flags)&NIX_TX_OFFLOAD_TSO_F) &&                          \\\n \t\t    !((flags)&NIX_TX_OFFLOAD_L3_L4_CSUM_F))                    \\\n \t\t\treturn 0;                                              \\\n-\t\treturn cn10k_nix_xmit_pkts_mseg(tx_queue, tx_pkts, pkts, cmd,  \\\n-\t\t\t\t\t\t0,                             \\\n+\t\treturn cn10k_nix_xmit_pkts_mseg(tx_queue, NULL, tx_pkts, pkts, \\\n+\t\t\t\t\t\tcmd,                           \\\n \t\t\t\t\t\tflags | NIX_TX_MULTI_SEG_F);   \\\n \t}\n\n@@ -2925,8 +2930,8 @@ NIX_TX_FASTPATH_MODES\n \t\tif (((flags)&NIX_TX_OFFLOAD_TSO_F) &&                          \\\n \t\t    !((flags)&NIX_TX_OFFLOAD_L3_L4_CSUM_F))                    \\\n \t\t\treturn 0;                                              \\\n-\t\treturn cn10k_nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts,     \\\n-\t\t\t\t\t\t  cmd, 0, (flags));            \\\n+\t\treturn cn10k_nix_xmit_pkts_vector(tx_queue, NULL, tx_pkts,     \\\n+\t\t\t\t\t\t  pkts, cmd, (flags));         \\\n \t}\n\n #define NIX_TX_XMIT_VEC_MSEG(fn, sz, flags)                                    \\\n@@ -2940,7 +2945,7 @@ NIX_TX_FASTPATH_MODES\n \t\t    !((flags)&NIX_TX_OFFLOAD_L3_L4_CSUM_F))                    \\\n \t\t\treturn 0;                                              \\\n \t\treturn cn10k_nix_xmit_pkts_vector(                             \\\n-\t\t\ttx_queue, tx_pkts, pkts, cmd, 0,                       \\\n+\t\t\ttx_queue, NULL, tx_pkts, pkts, cmd,                    \\\n \t\t\t(flags) | NIX_TX_MULTI_SEG_F);                         \\\n \t}\n\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nindex f8f3d3895e..9cb4a8369f 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.c\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -131,51 +131,31 @@ static void\n nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn9k_eth_txq *txq,\n \t\t      uint16_t qid)\n {\n-\tstruct nix_send_ext_s *send_hdr_ext;\n-\tstruct nix_send_hdr_s *send_hdr;\n-\tstruct nix_send_mem_s *send_mem;\n-\tunion nix_send_sg_s *sg;\n+\tunion nix_send_hdr_w0_u send_hdr_w0;\n\n \t/* Initialize the fields based on basic single segment packet */\n-\tmemset(&txq->cmd, 0, sizeof(txq->cmd));\n-\n+\tsend_hdr_w0.u = 0;\n \tif (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {\n-\t\tsend_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];\n \t\t/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */\n-\t\tsend_hdr->w0.sizem1 = 2;\n-\n-\t\tsend_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];\n-\t\tsend_hdr_ext->w0.subdc = NIX_SUBDC_EXT;\n+\t\tsend_hdr_w0.sizem1 = 2;\n \t\tif (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n \t\t\t/* Default: one seg packet would have:\n \t\t\t * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)\n \t\t\t * => 8/2 - 1 = 3\n \t\t\t */\n-\t\t\tsend_hdr->w0.sizem1 = 3;\n-\t\t\tsend_hdr_ext->w0.tstmp = 1;\n+\t\t\tsend_hdr_w0.sizem1 = 3;\n\n \t\t\t/* To calculate the offset for send_mem,\n \t\t\t * send_hdr->w0.sizem1 * 2\n \t\t\t */\n-\t\t\tsend_mem = (struct nix_send_mem_s *)\n-\t\t\t\t(txq->cmd + (send_hdr->w0.sizem1 << 1));\n-\t\t\tsend_mem->w0.cn9k.subdc = NIX_SUBDC_MEM;\n-\t\t\tsend_mem->w0.cn9k.alg = NIX_SENDMEMALG_SETTSTMP;\n-\t\t\tsend_mem->addr = dev->tstamp.tx_tstamp_iova;\n+\t\t\ttxq->ts_mem = dev->tstamp.tx_tstamp_iova;\n \t\t}\n-\t\tsg = (union nix_send_sg_s *)&txq->cmd[4];\n \t} else {\n-\t\tsend_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];\n \t\t/* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */\n-\t\tsend_hdr->w0.sizem1 = 1;\n-\t\tsg = (union nix_send_sg_s *)&txq->cmd[2];\n+\t\tsend_hdr_w0.sizem1 = 1;\n \t}\n-\n-\tsend_hdr->w0.sq = qid;\n-\tsg->subdc = NIX_SUBDC_SG;\n-\tsg->segs = 1;\n-\tsg->ld_type = NIX_SENDLDTYPE_LDD;\n-\n+\tsend_hdr_w0.sq = qid;\n+\ttxq->send_hdr_w0 = send_hdr_w0.u;\n \trte_wmb();\n }\n\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.h b/drivers/net/cnxk/cn9k_ethdev.h\nindex 2b452fe009..8ab924944c 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.h\n+++ b/drivers/net/cnxk/cn9k_ethdev.h\n@@ -9,12 +9,13 @@\n #include <cnxk_security_ar.h>\n\n struct cn9k_eth_txq {\n-\tuint64_t cmd[8];\n+\tuint64_t send_hdr_w0;\n \tint64_t fc_cache_pkts;\n \tuint64_t *fc_mem;\n \tvoid *lmt_addr;\n \trte_iova_t io_addr;\n \tuint64_t lso_tun_fmt;\n+\tuint64_t ts_mem;\n \tuint16_t sqes_per_sqb_log2;\n \tint16_t nb_sqb_bufs_adj;\n \trte_iova_t cpt_io_addr;\ndiff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h\nindex 5e1148a1d2..20525c3a37 100644\n--- a/drivers/net/cnxk/cn9k_tx.h\n+++ b/drivers/net/cnxk/cn9k_tx.h\n@@ -58,6 +58,29 @@ cn9k_nix_tx_ext_subs(const uint16_t flags)\n \t\t\t\t  : 0);\n }\n\n+static __rte_always_inline void\n+cn9k_nix_tx_skeleton(struct cn9k_eth_txq *txq, uint64_t *cmd,\n+\t\t     const uint16_t flags, const uint16_t static_sz)\n+{\n+\tif (static_sz)\n+\t\tcmd[0] = txq->send_hdr_w0;\n+\telse\n+\t\tcmd[0] = (txq->send_hdr_w0 & 0xFFFFF00000000000) |\n+\t\t\t ((uint64_t)(cn9k_nix_tx_ext_subs(flags) + 1) << 40);\n+\tcmd[1] = 0;\n+\n+\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F)\n+\t\t\tcmd[2] = (NIX_SUBDC_EXT << 60) | BIT_ULL(15);\n+\t\telse\n+\t\t\tcmd[2] = NIX_SUBDC_EXT << 60;\n+\t\tcmd[3] = 0;\n+\t\tcmd[4] = (NIX_SUBDC_SG << 60) | BIT_ULL(48);\n+\t} else {\n+\t\tcmd[2] = (NIX_SUBDC_SG << 60) | BIT_ULL(48);\n+\t}\n+}\n+\n static __rte_always_inline void\n cn9k_nix_xmit_prepare_tso(struct rte_mbuf *m, const uint64_t flags)\n {\n@@ -136,11 +159,11 @@ cn9k_nix_xmit_prepare(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags,\n \t\tw1.u = 0;\n \t}\n\n-\tif (!(flags & NIX_TX_MULTI_SEG_F)) {\n+\tif (!(flags & NIX_TX_MULTI_SEG_F))\n \t\tsend_hdr->w0.total = m->data_len;\n-\t\tsend_hdr->w0.aura =\n-\t\t\troc_npa_aura_handle_to_aura(m->pool->pool_id);\n-\t}\n+\telse\n+\t\tsend_hdr->w0.total = m->pkt_len;\n+\tsend_hdr->w0.aura = roc_npa_aura_handle_to_aura(m->pool->pool_id);\n\n \t/*\n \t * L3type:  2 => IPV4\n@@ -287,40 +310,38 @@ cn9k_nix_xmit_prepare(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags,\n \t\t/* Mark mempool object as \"put\" since it is freed by NIX */\n \t\tif (!send_hdr->w0.df)\n \t\t\tRTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);\n+\t} else {\n+\t\tsg->seg1_size = m->data_len;\n+\t\t*(rte_iova_t *)(sg + 1) = rte_mbuf_data_iova(m);\n+\n+\t\t/* NOFF is handled later for multi-seg */\n \t}\n }\n\n static __rte_always_inline void\n-cn9k_nix_xmit_prepare_tstamp(uint64_t *cmd, const uint64_t *send_mem_desc,\n+cn9k_nix_xmit_prepare_tstamp(struct cn9k_eth_txq *txq, uint64_t *cmd,\n \t\t\t     const uint64_t ol_flags, const uint16_t no_segdw,\n \t\t\t     const uint16_t flags)\n {\n \tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n \t\tstruct nix_send_mem_s *send_mem;\n \t\tuint16_t off = (no_segdw - 1) << 1;\n-\t\tconst uint8_t is_ol_tstamp = !(ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST);\n+\t\tconst uint8_t is_ol_tstamp =\n+\t\t\t!(ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST);\n\n \t\tsend_mem = (struct nix_send_mem_s *)(cmd + off);\n-\t\tif (flags & NIX_TX_MULTI_SEG_F) {\n-\t\t\t/* Retrieving the default desc values */\n-\t\t\tcmd[off] = send_mem_desc[6];\n\n-\t\t\t/* Using compiler barier to avoid voilation of C\n-\t\t\t * aliasing rules.\n-\t\t\t */\n-\t\t\trte_compiler_barrier();\n-\t\t}\n-\n-\t\t/* Packets for which RTE_MBUF_F_TX_IEEE1588_TMST is not set, tx tstamp\n+\t\t/* Packets for which PKT_TX_IEEE1588_TMST is not set, tx tstamp\n \t\t * should not be recorded, hence changing the alg type to\n-\t\t * NIX_SENDMEMALG_SET and also changing send mem addr field to\n+\t\t * NIX_SENDMEMALG_SUB and also changing send mem addr field to\n \t\t * next 8 bytes as it corrpt the actual tx tstamp registered\n \t\t * address.\n \t\t */\n+\t\tsend_mem->w0.cn9k.subdc = NIX_SUBDC_MEM;\n \t\tsend_mem->w0.cn9k.alg =\n-\t\t\tNIX_SENDMEMALG_SETTSTMP - (is_ol_tstamp);\n+\t\t\tNIX_SENDMEMALG_SETTSTMP + (is_ol_tstamp << 3);\n\n-\t\tsend_mem->addr = (rte_iova_t)((uint64_t *)send_mem_desc[7] +\n+\t\tsend_mem->addr = (rte_iova_t)(((uint64_t *)txq->ts_mem) +\n \t\t\t\t\t      (is_ol_tstamp));\n \t}\n }\n@@ -367,8 +388,6 @@ cn9k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n \tuint8_t off, i;\n\n \tsend_hdr = (struct nix_send_hdr_s *)cmd;\n-\tsend_hdr->w0.total = m->pkt_len;\n-\tsend_hdr->w0.aura = roc_npa_aura_handle_to_aura(m->pool->pool_id);\n\n \tif (flags & NIX_TX_NEED_EXT_HDR)\n \t\toff = 2;\n@@ -376,13 +395,29 @@ cn9k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n \t\toff = 0;\n\n \tsg = (union nix_send_sg_s *)&cmd[2 + off];\n-\t/* Clear sg->u header before use */\n-\tsg->u &= 0xFC00000000000000;\n+\n+\t/* Start from second segment, first segment is already there */\n+\ti = 1;\n \tsg_u = sg->u;\n-\tslist = &cmd[3 + off];\n+\tnb_segs = m->nb_segs - 1;\n+\tm_next = m->next;\n+\tslist = &cmd[3 + off + 1];\n\n-\ti = 0;\n-\tnb_segs = m->nb_segs;\n+\t/* Set invert df if buffer is not to be freed by H/W */\n+\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n+\t\tsg_u |= (cnxk_nix_prefree_seg(m) << 55);\n+\t\trte_io_wmb();\n+\t}\n+\n+\t/* Mark mempool object as \"put\" since it is freed by NIX */\n+#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n+\tif (!(sg_u & (1ULL << 55)))\n+\t\tRTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);\n+\trte_io_wmb();\n+#endif\n+\tm = m_next;\n+\tif (!m)\n+\t\tgoto done;\n\n \t/* Fill mbuf segments */\n \tdo {\n@@ -417,6 +452,7 @@ cn9k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n \t\tm = m_next;\n \t} while (nb_segs);\n\n+done:\n \tsg->u = sg_u;\n \tsg->segs = i;\n \tsegdw = (uint64_t *)slist - (uint64_t *)&cmd[2 + off];\n@@ -472,7 +508,7 @@ cn9k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n\n \tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n\n-\troc_lmt_mov(cmd, &txq->cmd[0], cn9k_nix_tx_ext_subs(flags));\n+\tcn9k_nix_tx_skeleton(txq, cmd, flags, 1);\n\n \t/* Perform header writes before barrier for TSO */\n \tif (flags & NIX_TX_OFFLOAD_TSO_F) {\n@@ -490,8 +526,8 @@ cn9k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n\n \tfor (i = 0; i < pkts; i++) {\n \t\tcn9k_nix_xmit_prepare(tx_pkts[i], cmd, flags, lso_tun_fmt);\n-\t\tcn9k_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n-\t\t\t\t\t     tx_pkts[i]->ol_flags, 4, flags);\n+\t\tcn9k_nix_xmit_prepare_tstamp(txq, cmd, tx_pkts[i]->ol_flags, 4,\n+\t\t\t\t\t     flags);\n \t\tcn9k_nix_xmit_one(cmd, lmt_addr, io_addr, flags);\n \t}\n\n@@ -514,7 +550,7 @@ cn9k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n\n \tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n\n-\troc_lmt_mov(cmd, &txq->cmd[0], cn9k_nix_tx_ext_subs(flags));\n+\tcn9k_nix_tx_skeleton(txq, cmd, flags, 1);\n\n \t/* Perform header writes before barrier for TSO */\n \tif (flags & NIX_TX_OFFLOAD_TSO_F) {\n@@ -533,9 +569,8 @@ cn9k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tfor (i = 0; i < pkts; i++) {\n \t\tcn9k_nix_xmit_prepare(tx_pkts[i], cmd, flags, lso_tun_fmt);\n \t\tsegdw = cn9k_nix_prepare_mseg(tx_pkts[i], cmd, flags);\n-\t\tcn9k_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n-\t\t\t\t\t     tx_pkts[i]->ol_flags, segdw,\n-\t\t\t\t\t     flags);\n+\t\tcn9k_nix_xmit_prepare_tstamp(txq, cmd, tx_pkts[i]->ol_flags,\n+\t\t\t\t\t     segdw, flags);\n \t\tcn9k_nix_xmit_mseg_one(cmd, lmt_addr, io_addr, segdw);\n \t}\n\n@@ -862,28 +897,34 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tif (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))\n \t\trte_io_wmb();\n\n-\tsenddesc01_w0 = vld1q_dup_u64(&txq->cmd[0]);\n+\tsenddesc01_w0 = vld1q_dup_u64(&txq->send_hdr_w0);\n \tsenddesc23_w0 = senddesc01_w0;\n+\n \tsenddesc01_w1 = vdupq_n_u64(0);\n \tsenddesc23_w1 = senddesc01_w1;\n+\tsgdesc01_w0 = vdupq_n_u64((NIX_SUBDC_SG << 60) | BIT_ULL(48));\n+\tsgdesc23_w0 = sgdesc01_w0;\n\n-\t/* Load command defaults into vector variables. */\n \tif (flags & NIX_TX_NEED_EXT_HDR) {\n-\t\tsendext01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n-\t\tsendext23_w0 = sendext01_w0;\n-\t\tsendext01_w1 = vdupq_n_u64(12 | 12U << 24);\n-\t\tsendext23_w1 = sendext01_w1;\n-\t\tsgdesc01_w0 = vld1q_dup_u64(&txq->cmd[4]);\n-\t\tsgdesc23_w0 = sgdesc01_w0;\n \t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n-\t\t\tsendmem01_w0 = vld1q_dup_u64(&txq->cmd[6]);\n+\t\t\tsendext01_w0 = vdupq_n_u64((NIX_SUBDC_EXT << 60) |\n+\t\t\t\t\t\t   BIT_ULL(15));\n+\t\t\tsendmem01_w0 =\n+\t\t\t\tvdupq_n_u64((NIX_SUBDC_MEM << 60) |\n+\t\t\t\t\t    (NIX_SENDMEMALG_SETTSTMP << 56));\n \t\t\tsendmem23_w0 = sendmem01_w0;\n-\t\t\tsendmem01_w1 = vld1q_dup_u64(&txq->cmd[7]);\n+\t\t\tsendmem01_w1 = vdupq_n_u64(txq->ts_mem);\n \t\t\tsendmem23_w1 = sendmem01_w1;\n+\t\t} else {\n+\t\t\tsendext01_w0 = vdupq_n_u64((NIX_SUBDC_EXT << 60));\n \t\t}\n-\t} else {\n-\t\tsgdesc01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n-\t\tsgdesc23_w0 = sgdesc01_w0;\n+\t\tsendext23_w0 = sendext01_w0;\n+\n+\t\tif (flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)\n+\t\t\tsendext01_w1 = vdupq_n_u64(12 | 12U << 24);\n+\t\telse\n+\t\t\tsendext01_w1 = vdupq_n_u64(0);\n+\t\tsendext23_w1 = sendext01_w1;\n \t}\n\n \tfor (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {\n",
    "prefixes": [
        "1/4"
    ]
}