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GET /api/patches/105108/?format=api
{ "id": 105108, "url": "http://patches.dpdk.org/api/patches/105108/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213111345.5046-2-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211213111345.5046-2-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211213111345.5046-2-pbhagavatula@marvell.com", "date": "2021-12-13T11:13:44", "name": "[v5,2/2] event/cnxk: add external clock support for timer", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "956e87580a8b9f8f12a1b04c6a2786f02a2fd0b5", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213111345.5046-2-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 20928, "url": "http://patches.dpdk.org/api/series/20928/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20928", "date": "2021-12-13T11:13:43", "name": "[v5,1/2] event/cnxk: update min interval calculation", "version": 5, "mbox": "http://patches.dpdk.org/series/20928/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105108/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105108/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CFB8BA0032;\n\tMon, 13 Dec 2021 12:14:01 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EEEA04113D;\n\tMon, 13 Dec 2021 12:13:59 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 5E4394113D\n for <dev@dpdk.org>; Mon, 13 Dec 2021 12:13:58 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BD7j3Bj027614;\n Mon, 13 Dec 2021 03:13:57 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cx21kgp2d-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 13 Dec 2021 03:13:57 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 13 Dec 2021 03:13:56 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 13 Dec 2021 03:13:55 -0800", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 171D83F7068;\n Mon, 13 Dec 2021 03:13:52 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=E/uoangUUZOx9nxlxT4W5yRtg8IIAVvs44ZOk9Y9sac=;\n b=IIy9pIHWTmu+3SY8cZOgHdfdaDEUBbtMTMXy8Yjm6qi4Lvtm3JctL82CshExN0rIdIU+\n xdE0qfO/aJ+yyhbbE5l9Uwj4ffcpkcFc/cf2dZBRkbtOLm6Hihrz4V+zwrUA/502EuiO\n JI1Q5xRtn8xyPVulEghNqZwvPqJVgDsPNVwWTI4Zt7+bXBi4Ipn59fZ8KjYEQvy/ZW5V\n c8hASkjAljI+zoFpSX7j5I+JkfOl1oPwilmMkX5zCcaFZGypDMbnr50WxbIWvytcV38I\n DRaYQCuqdzuP9B1ucPa6e8Q8D7lPRBfiDN5gWv5S18qRBD7+DTm8uE8HZqROgJcDv3/Z lg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori\n <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>, Anatoly Burakov\n <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v5 2/2] event/cnxk: add external clock support for timer", "Date": "Mon, 13 Dec 2021 16:43:44 +0530", "Message-ID": "<20211213111345.5046-2-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211213111345.5046-1-pbhagavatula@marvell.com>", "References": "<20211009080426.18482-1-pbhagavatula@marvell.com>\n <20211213111345.5046-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "EvGOJtzuAM3FUF3d4RYdS-uHnuJGzSXk", "X-Proofpoint-ORIG-GUID": "EvGOJtzuAM3FUF3d4RYdS-uHnuJGzSXk", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_04,2021-12-13_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd external clock support for cnxk timer adapter.\n\nExternal clock mapping is as follows:\nRTE_EVENT_TIMER_ADAPTER_EXT_CLK0 = TIM_CLK_SRC_10NS,\nRTE_EVENT_TIMER_ADAPTER_EXT_CLK1 = TIM_CLK_SRC_GPIO,\nRTE_EVENT_TIMER_ADAPTER_EXT_CLK2 = TIM_CLK_SRC_PTP,\nRTE_EVENT_TIMER_ADAPTER_EXT_CLK3 = TIM_CLK_SRC_SYNCE,\n\nTIM supports clock input from external GPIO, PTP, SYNCE clocks.\nInput resolution is adjusted based on CNTVCT frequency for better\nestimation.\n\nSince TIM is unaware of input clock frequency, application is\nexpected to pass the frequency.\nExample:\n\t-a 0002:0e:00.0,tim_eclk_freq=122880000-0-0\n\nThe order of frequencies above is GPIO-PTP-SYNCE.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 18 ++++\n drivers/common/cnxk/roc_platform.h | 1 +\n drivers/event/cnxk/cn10k_eventdev.c | 3 +-\n drivers/event/cnxk/cnxk_tim_evdev.c | 137 +++++++++++++++++++++++++++-\n drivers/event/cnxk/cnxk_tim_evdev.h | 4 +\n 5 files changed, 160 insertions(+), 3 deletions(-)\n\n--\n2.17.1", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex 1c0ea988f2..8537f6257e 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -164,6 +164,24 @@ Runtime Config Options\n\n -a 0002:0e:00.0,tim_ring_ctl=[2-1023-1-0]\n\n+- ``TIM external clock frequency``\n+\n+ The ``tim_eclk_freq`` devagrs can be used to pass external clock frequencies\n+ when external clock source is selected.\n+\n+ External clock frequencies are mapped as follows::\n+\n+ RTE_EVENT_TIMER_ADAPTER_EXT_CLK0 = TIM_CLK_SRC_10NS,\n+ RTE_EVENT_TIMER_ADAPTER_EXT_CLK1 = TIM_CLK_SRC_GPIO,\n+ RTE_EVENT_TIMER_ADAPTER_EXT_CLK2 = TIM_CLK_SRC_PTP,\n+ RTE_EVENT_TIMER_ADAPTER_EXT_CLK3 = TIM_CLK_SRC_SYNCE\n+\n+ The order of frequencies supplied to device args should be GPIO-PTP-SYNCE.\n+\n+ For Example::\n+\n+ -a 0002:0e:00.0,tim_eclk_freq=122880000-1000000000-0\n+\n Debugging Options\n -----------------\n\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 61d4781209..2742a09190 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -45,6 +45,7 @@\n #define PLT_MAX\t\t\t RTE_MAX\n #define PLT_DIM\t\t\t RTE_DIM\n #define PLT_SET_USED\t\t RTE_SET_USED\n+#define PLT_SWAP\t\t RTE_SWAP\n #define PLT_STATIC_ASSERT(s)\t _Static_assert(s, #s)\n #define PLT_ALIGN\t\t RTE_ALIGN\n #define PLT_ALIGN_MUL_CEIL\t RTE_ALIGN_MUL_CEIL\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex b56426960a..70e2aa5555 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -916,4 +916,5 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT \"=<int>\"\n \t\t\t CNXK_TIM_DISABLE_NPA \"=1\"\n \t\t\t CNXK_TIM_CHNK_SLOTS \"=<int>\"\n \t\t\t CNXK_TIM_RINGS_LMT \"=<int>\"\n-\t\t\t CNXK_TIM_STATS_ENA \"=1\");\n+\t\t\t CNXK_TIM_STATS_ENA \"=1\"\n+\t\t\t CNXK_TIM_EXT_CLK \"=<string>\");\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex becab1d1b1..5d52a39752 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -117,6 +117,80 @@ cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,\n \t\t sizeof(struct rte_event_timer_adapter_conf));\n }\n\n+static inline void\n+sort_multi_array(double ref_arr[], uint64_t arr1[], uint64_t arr2[],\n+\t\t uint64_t arr3[], uint8_t sz)\n+{\n+\tint x;\n+\n+\tfor (x = 0; x < sz - 1; x++) {\n+\t\tif (ref_arr[x] > ref_arr[x + 1]) {\n+\t\t\tPLT_SWAP(ref_arr[x], ref_arr[x + 1]);\n+\t\t\tPLT_SWAP(arr1[x], arr1[x + 1]);\n+\t\t\tPLT_SWAP(arr2[x], arr2[x + 1]);\n+\t\t\tPLT_SWAP(arr3[x], arr3[x + 1]);\n+\t\t\tx = -1;\n+\t\t}\n+\t}\n+}\n+\n+static inline void\n+populate_sample(uint64_t tck[], uint64_t ns[], double diff[], uint64_t dst[],\n+\t\tuint64_t req_tck, uint64_t clk_freq, double tck_ns, uint8_t sz,\n+\t\tbool mov_fwd)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < sz; i++) {\n+\t\ttck[i] = i ? tck[i - 1] : req_tck;\n+\t\tdo {\n+\t\t\tmov_fwd ? tck[i]++ : tck[i]--;\n+\t\t\tns[i] = round((double)tck[i] * tck_ns);\n+\t\t\tif (round((double)tck[i] * tck_ns) >\n+\t\t\t ((double)tck[i] * tck_ns))\n+\t\t\t\tcontinue;\n+\t\t} while (ns[i] % (uint64_t)cnxk_tim_ns_per_tck(clk_freq));\n+\t\tdiff[i] = PLT_MAX((double)ns[i], (double)tck[i] * tck_ns) -\n+\t\t\t PLT_MIN((double)ns[i], (double)tck[i] * tck_ns);\n+\t\tdst[i] = mov_fwd ? tck[i] - req_tck : req_tck - tck[i];\n+\t}\n+}\n+\n+static void\n+tim_adjust_resolution(uint64_t *req_ns, uint64_t *req_tck, double tck_ns,\n+\t\t uint64_t clk_freq, uint64_t max_tmo, uint64_t m_tck)\n+{\n+#define MAX_SAMPLES 5\n+\tdouble rmax_diff[MAX_SAMPLES], rmin_diff[MAX_SAMPLES];\n+\tuint64_t min_tck[MAX_SAMPLES], max_tck[MAX_SAMPLES];\n+\tuint64_t min_dst[MAX_SAMPLES], max_dst[MAX_SAMPLES];\n+\tuint64_t min_ns[MAX_SAMPLES], max_ns[MAX_SAMPLES];\n+\tint i;\n+\n+\tpopulate_sample(max_tck, max_ns, rmax_diff, max_dst, *req_tck, clk_freq,\n+\t\t\ttck_ns, MAX_SAMPLES, true);\n+\tsort_multi_array(rmax_diff, max_dst, max_tck, max_ns, MAX_SAMPLES);\n+\n+\tpopulate_sample(min_tck, min_ns, rmin_diff, min_dst, *req_tck, clk_freq,\n+\t\t\ttck_ns, MAX_SAMPLES, false);\n+\tsort_multi_array(rmin_diff, min_dst, min_tck, min_ns, MAX_SAMPLES);\n+\n+\tfor (i = 0; i < MAX_SAMPLES; i++) {\n+\t\tif (min_dst[i] < max_dst[i] && min_tck[i] > m_tck &&\n+\t\t (max_tmo / min_ns[i]) <=\n+\t\t\t (TIM_MAX_BUCKET_SIZE - TIM_MIN_BUCKET_SIZE)) {\n+\t\t\t*req_tck = min_tck[i];\n+\t\t\t*req_ns = min_ns[i];\n+\t\t\tbreak;\n+\t\t} else if ((max_tmo / max_ns[i]) <\n+\t\t\t (TIM_MAX_BUCKET_SIZE - TIM_MIN_BUCKET_SIZE)) {\n+\t\t\t*req_tck = max_tck[i];\n+\t\t\t*req_ns = max_ns[i];\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n static int\n cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n {\n@@ -178,10 +252,25 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \t\tgoto tim_hw_free;\n \t}\n\n-\t/* Round */\n \ttim_ring->tck_nsec =\n \t\tround(RTE_ALIGN_MUL_NEAR((long double)rcfg->timer_tick_ns,\n \t\t\t\t\t cnxk_tim_ns_per_tck(clk_freq)));\n+\tif (log10(clk_freq) - floor(log10(clk_freq)) != 0.0) {\n+\t\tuint64_t req_ns, req_tck;\n+\t\tdouble tck_ns;\n+\n+\t\treq_ns = tim_ring->tck_nsec;\n+\t\ttck_ns = NSECPERSEC / clk_freq;\n+\t\treq_tck = round(rcfg->timer_tick_ns / tck_ns);\n+\t\ttim_adjust_resolution(&req_ns, &req_tck, tck_ns, clk_freq,\n+\t\t\t\t rcfg->max_tmo_ns, min_intvl_cyc);\n+\t\tif ((tim_ring->tck_nsec != req_ns) &&\n+\t\t !(rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)) {\n+\t\t\trc = -ERANGE;\n+\t\t\tgoto tim_hw_free;\n+\t\t}\n+\t\ttim_ring->tck_nsec = ceil(req_tck * tck_ns);\n+\t}\n\n \ttim_ring->tck_int = round((long double)tim_ring->tck_nsec /\n \t\t\t\t cnxk_tim_ns_per_tck(clk_freq));\n@@ -457,11 +546,16 @@ cnxk_tim_parse_ring_ctl_list(const char *value, void *opaque)\n \tchar *end = NULL;\n \tchar *f = s;\n\n+\tif (s == NULL || !strlen(s))\n+\t\treturn;\n+\n \twhile (*s) {\n \t\tif (*s == '[')\n \t\t\tstart = s;\n \t\telse if (*s == ']')\n \t\t\tend = s;\n+\t\telse\n+\t\t\tcontinue;\n\n \t\tif (start && start < end) {\n \t\t\t*end = 0;\n@@ -488,6 +582,43 @@ cnxk_tim_parse_kvargs_dict(const char *key, const char *value, void *opaque)\n \treturn 0;\n }\n\n+static void\n+cnxk_tim_parse_clk_list(const char *value, void *opaque)\n+{\n+\tenum roc_tim_clk_src src[] = {ROC_TIM_CLK_SRC_GPIO, ROC_TIM_CLK_SRC_PTP,\n+\t\t\t\t ROC_TIM_CLK_SRC_SYNCE,\n+\t\t\t\t ROC_TIM_CLK_SRC_INVALID};\n+\tstruct cnxk_tim_evdev *dev = opaque;\n+\tchar *str = strdup(value);\n+\tchar *tok;\n+\tint i = 0;\n+\n+\tif (str == NULL || !strlen(str))\n+\t\treturn;\n+\n+\ttok = strtok(str, \"-\");\n+\twhile (tok != NULL && src[i] != ROC_TIM_CLK_SRC_INVALID) {\n+\t\tdev->ext_clk_freq[src[i]] = strtoull(tok, NULL, 10);\n+\t\ttok = strtok(NULL, \"-\");\n+\t\ti++;\n+\t}\n+\n+\tfree(str);\n+}\n+\n+static int\n+cnxk_tim_parse_kvargs_dsv(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t/* DSV format GPIO-PTP-SYNCE-BTS use '-' as ','\n+\t * isn't allowed. 0 represents default.\n+\t */\n+\tcnxk_tim_parse_clk_list(value, opaque);\n+\n+\treturn 0;\n+}\n+\n static void\n cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)\n {\n@@ -510,6 +641,8 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)\n \t\t\t &dev->min_ring_cnt);\n \trte_kvargs_process(kvlist, CNXK_TIM_RING_CTL,\n \t\t\t &cnxk_tim_parse_kvargs_dict, &dev);\n+\trte_kvargs_process(kvlist, CNXK_TIM_EXT_CLK, &cnxk_tim_parse_kvargs_dsv,\n+\t\t\t dev);\n\n \trte_kvargs_free(kvlist);\n }\n@@ -558,7 +691,7 @@ cnxk_tim_fini(void)\n {\n \tstruct cnxk_tim_evdev *dev = cnxk_tim_priv_get();\n\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\tif (dev == NULL || rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn;\n\n \troc_tim_fini(&dev->tim);\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nindex 1fb17f571d..6b5342cc34 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.h\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -40,6 +40,7 @@\n #define CNXK_TIM_STATS_ENA \"tim_stats_ena\"\n #define CNXK_TIM_RINGS_LMT \"tim_rings_lmt\"\n #define CNXK_TIM_RING_CTL \"tim_ring_ctl\"\n+#define CNXK_TIM_EXT_CLK \"tim_eclk_freq\"\n\n #define CNXK_TIM_SP\t 0x1\n #define CNXK_TIM_MP\t 0x2\n@@ -95,6 +96,7 @@ struct cnxk_tim_evdev {\n \tuint32_t min_ring_cnt;\n \tuint8_t enable_stats;\n \tuint16_t ring_ctl_cnt;\n+\tuint64_t ext_clk_freq[ROC_TIM_CLK_SRC_INVALID];\n \tstruct cnxk_tim_ctl *ring_ctl_data;\n };\n\n@@ -236,6 +238,8 @@ cnxk_tim_get_clk_freq(struct cnxk_tim_evdev *dev, enum roc_tim_clk_src clk_src,\n \tcase ROC_TIM_CLK_SRC_GPIO:\n \tcase ROC_TIM_CLK_SRC_PTP:\n \tcase ROC_TIM_CLK_SRC_SYNCE:\n+\t\t*freq = dev->ext_clk_freq[clk_src];\n+\t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n", "prefixes": [ "v5", "2/2" ] }