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GET /api/patches/105093/?format=api
{ "id": 105093, "url": "http://patches.dpdk.org/api/patches/105093/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213081732.2096334-11-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211213081732.2096334-11-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211213081732.2096334-11-tduszynski@marvell.com", "date": "2021-12-13T08:17:32", "name": "[v3,10/10] raw/cnxk_gpio: support selftest", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e854fbce0214d5ad8891ad6ce2f152abe4d1f791", "submitter": { "id": 2215, "url": "http://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213081732.2096334-11-tduszynski@marvell.com/mbox/", "series": [ { "id": 20921, "url": "http://patches.dpdk.org/api/series/20921/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20921", "date": "2021-12-13T08:17:22", "name": "Add cnxk_gpio PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/20921/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105093/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105093/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ABD01A00BE;\n\tMon, 13 Dec 2021 09:19:34 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 99E33411F3;\n\tMon, 13 Dec 2021 09:18:39 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id EE567411B6\n for <dev@dpdk.org>; Mon, 13 Dec 2021 09:18:37 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BD7ieBi027462;\n Mon, 13 Dec 2021 00:18:37 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cx21kg3c8-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 13 Dec 2021 00:18:37 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Dec 2021 00:18:35 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 13 Dec 2021 00:18:35 -0800", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 6CFE03F7045;\n Mon, 13 Dec 2021 00:18:34 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=c1rfaLL+yXUE9CduwwtwdclxX609xvN9WlURF6YlHx0=;\n b=OXQkSHhDWJ0ZjX9BeSAh0tbq84oS1AUXozDlC7Khy5Wl1NGVF5qRYBN0Bni1n/cekzjG\n lfTAXSuADDwF8vwWiy+9wqBLeRhyY8qmlMa2tRa9qE4T5UzvaBWYc9F7xnW45Z4n/b3d\n EOUwf6TNNshQdiXoI/rbR0KITxvX1Ymc+cSac4ZvLDjr09Q9QdDUYMaRkqA+73cAnT1D\n bxMOwwraW2hRRWpLuYF9Nj7Igu/MoJmEAqTOilQwJ7wg7DtN8jL44RL33kPRSmI+uO9b\n E2mJ8WbEBxNRUV30pF8nFg22XozMffNrOwDa5QcTdQ12ganCE4PIS4Y7rz22RSm3AK+E ow==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <stephen@networkplumber.org>, Tomasz Duszynski\n <tduszynski@marvell.com>", "Subject": "[PATCH v3 10/10] raw/cnxk_gpio: support selftest", "Date": "Mon, 13 Dec 2021 09:17:32 +0100", "Message-ID": "<20211213081732.2096334-11-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211213081732.2096334-1-tduszynski@marvell.com>", "References": "<20211128154442.4029049-1-tduszynski@marvell.com>\n <20211213081732.2096334-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "rkb4US5nCeqT1-PvWW5SY-oydGE7xrQf", "X-Proofpoint-ORIG-GUID": "rkb4US5nCeqT1-PvWW5SY-oydGE7xrQf", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_03,2021-12-10_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for performing selftest.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\n---\n doc/guides/rawdevs/cnxk_gpio.rst | 11 +\n drivers/raw/cnxk_gpio/cnxk_gpio.c | 1 +\n drivers/raw/cnxk_gpio/cnxk_gpio.h | 2 +\n drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c | 386 +++++++++++++++++++++\n drivers/raw/cnxk_gpio/meson.build | 1 +\n 5 files changed, 401 insertions(+)\n create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c", "diff": "diff --git a/doc/guides/rawdevs/cnxk_gpio.rst b/doc/guides/rawdevs/cnxk_gpio.rst\nindex ad93ec0d44..c03a5b937c 100644\n--- a/doc/guides/rawdevs/cnxk_gpio.rst\n+++ b/doc/guides/rawdevs/cnxk_gpio.rst\n@@ -182,3 +182,14 @@ Message is used to remove installed interrupt handler.\n Message must have type set to ``CNXK_GPIO_MSG_TYPE_UNREGISTER_IRQ``.\n \n Consider using ``rte_pmd_gpio_unregister_gpio()`` wrapper.\n+\n+Self test\n+---------\n+\n+On EAL initialization CNXK GPIO device will be probed and populated into\n+the list of raw devices on condition ``--vdev=cnxk_gpio,gpiochip=<number>`` was\n+passed. ``rte_rawdev_get_dev_id(\"CNXK_GPIO\")`` returns unique device id. Use\n+this identifier for further rawdev function calls.\n+\n+Selftest rawdev API can be used to verify the PMD functionality. Note it blindly\n+assumes that all GPIOs are controllable so some errors during test are expected.\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.c b/drivers/raw/cnxk_gpio/cnxk_gpio.c\nindex f3fdd5a380..c9f87a315a 100644\n--- a/drivers/raw/cnxk_gpio/cnxk_gpio.c\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.c\n@@ -514,6 +514,7 @@ static const struct rte_rawdev_ops cnxk_gpio_rawdev_ops = {\n \t.queue_count = cnxk_gpio_queue_count,\n \t.queue_setup = cnxk_gpio_queue_setup,\n \t.queue_release = cnxk_gpio_queue_release,\n+\t.dev_selftest = cnxk_gpio_selftest,\n };\n \n static int\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.h b/drivers/raw/cnxk_gpio/cnxk_gpio.h\nindex c052ca5735..1b31b5a486 100644\n--- a/drivers/raw/cnxk_gpio/cnxk_gpio.h\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.h\n@@ -23,6 +23,8 @@ struct cnxk_gpiochip {\n \tstruct cnxk_gpio **gpios;\n };\n \n+int cnxk_gpio_selftest(uint16_t dev_id);\n+\n int cnxk_gpio_irq_init(struct cnxk_gpiochip *gpiochip);\n void cnxk_gpio_irq_fini(void);\n int cnxk_gpio_irq_request(int gpio, int cpu);\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c b/drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c\nnew file mode 100644\nindex 0000000000..6502902f86\n--- /dev/null\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c\n@@ -0,0 +1,386 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <fcntl.h>\n+#include <sys/ioctl.h>\n+#include <sys/stat.h>\n+#include <unistd.h>\n+\n+#include <rte_cycles.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+#include <rte_service.h>\n+\n+#include \"cnxk_gpio.h\"\n+#include \"rte_pmd_cnxk_gpio.h\"\n+\n+#define CNXK_GPIO_BUFSZ 128\n+\n+#define OTX_IOC_MAGIC 0xF2\n+#define OTX_IOC_TRIGGER_GPIO_HANDLER \\\n+\t_IO(OTX_IOC_MAGIC, 3)\n+\n+static int fd;\n+\n+static int\n+cnxk_gpio_attr_exists(const char *attr)\n+{\n+\tstruct stat st;\n+\n+\treturn !stat(attr, &st);\n+}\n+\n+static int\n+cnxk_gpio_read_attr(char *attr, char *val)\n+{\n+\tFILE *fp;\n+\tint ret;\n+\n+\tfp = fopen(attr, \"r\");\n+\tif (!fp)\n+\t\treturn -errno;\n+\n+\tret = fscanf(fp, \"%s\", val);\n+\tif (ret < 0)\n+\t\treturn -errno;\n+\tif (ret != 1)\n+\t\treturn -EIO;\n+\n+\tret = fclose(fp);\n+\tif (ret)\n+\t\treturn -errno;\n+\n+\treturn 0;\n+}\n+\n+#define CNXK_GPIO_ERR_STR(err, str, ...) do { \\\n+\tif (err) { \\\n+\t\tRTE_LOG(ERR, PMD, \"%s:%d: \" str \" (%d)\\n\", __func__, __LINE__, \\\n+\t\t\t##__VA_ARGS__, err); \\\n+\t\tgoto out; \\\n+\t} \\\n+} while (0)\n+\n+static int\n+cnxk_gpio_validate_attr(char *attr, const char *expected)\n+{\n+\tchar buf[CNXK_GPIO_BUFSZ];\n+\tint ret;\n+\n+\tret = cnxk_gpio_read_attr(attr, buf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (strncmp(buf, expected, sizeof(buf)))\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n+#define CNXK_GPIO_PATH_FMT \"/sys/class/gpio/gpio%d\"\n+\n+static int\n+cnxk_gpio_test_input(uint16_t dev_id, int base, int gpio)\n+{\n+\tchar buf[CNXK_GPIO_BUFSZ];\n+\tint ret, n;\n+\n+\tn = snprintf(buf, sizeof(buf), CNXK_GPIO_PATH_FMT, base + gpio);\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/direction\");\n+\n+\tret = rte_pmd_gpio_set_pin_dir(dev_id, gpio, CNXK_GPIO_PIN_DIR_IN);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set dir to input\");\n+\tret = cnxk_gpio_validate_attr(buf, \"in\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tret = rte_pmd_gpio_set_pin_value(dev_id, gpio, 1) |\n+\t rte_pmd_gpio_set_pin_value(dev_id, gpio, 0);\n+\tif (!ret) {\n+\t\tret = -EIO;\n+\t\tCNXK_GPIO_ERR_STR(ret, \"input pin overwritten\");\n+\t}\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/edge\");\n+\n+\tret = rte_pmd_gpio_set_pin_edge(dev_id, gpio,\n+\t\t\t\t\tCNXK_GPIO_PIN_EDGE_FALLING);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set edge to falling\");\n+\tret = cnxk_gpio_validate_attr(buf, \"falling\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tret = rte_pmd_gpio_set_pin_edge(dev_id, gpio,\n+\t\t\t\t\tCNXK_GPIO_PIN_EDGE_RISING);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to change edge to rising\");\n+\tret = cnxk_gpio_validate_attr(buf, \"rising\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tret = rte_pmd_gpio_set_pin_edge(dev_id, gpio, CNXK_GPIO_PIN_EDGE_BOTH);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to change edge to both\");\n+\tret = cnxk_gpio_validate_attr(buf, \"both\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tret = rte_pmd_gpio_set_pin_edge(dev_id, gpio, CNXK_GPIO_PIN_EDGE_NONE);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set edge to none\");\n+\tret = cnxk_gpio_validate_attr(buf, \"none\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\t/*\n+\t * calling this makes sure kernel driver switches off inverted\n+\t * logic\n+\t */\n+\trte_pmd_gpio_set_pin_dir(dev_id, gpio, CNXK_GPIO_PIN_DIR_IN);\n+\n+out:\n+\treturn ret;\n+}\n+\n+static int\n+cnxk_gpio_trigger_irq(int gpio)\n+{\n+\tint ret;\n+\n+\tret = ioctl(fd, OTX_IOC_TRIGGER_GPIO_HANDLER, gpio);\n+\n+\treturn ret == -1 ? -errno : 0;\n+}\n+\n+static void\n+cnxk_gpio_irq_handler(int gpio, void *data)\n+{\n+\t*(int *)data = gpio;\n+}\n+\n+static int\n+cnxk_gpio_test_irq(uint16_t dev_id, int gpio)\n+{\n+\tint irq_data, ret;\n+\n+\tret = rte_pmd_gpio_set_pin_dir(dev_id, gpio, CNXK_GPIO_PIN_DIR_IN);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set dir to input\");\n+\n+\tirq_data = 0;\n+\tret = rte_pmd_gpio_register_irq(dev_id, gpio, rte_lcore_id(),\n+\t\t\t\t\tcnxk_gpio_irq_handler, &irq_data);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to register irq handler\");\n+\n+\tret = rte_pmd_gpio_enable_interrupt(dev_id, gpio,\n+\t\t\t\t\t CNXK_GPIO_PIN_EDGE_RISING);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to enable interrupt\");\n+\n+\tret = cnxk_gpio_trigger_irq(gpio);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to trigger irq\");\n+\trte_delay_ms(1);\n+\tret = *(volatile int *)&irq_data == gpio ? 0 : -EIO;\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to test irq\");\n+\n+\tret = rte_pmd_gpio_disable_interrupt(dev_id, gpio);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to disable interrupt\");\n+\n+\tret = rte_pmd_gpio_unregister_irq(dev_id, gpio);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to unregister irq handler\");\n+out:\n+\trte_pmd_gpio_disable_interrupt(dev_id, gpio);\n+\trte_pmd_gpio_unregister_irq(dev_id, gpio);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cnxk_gpio_test_output(uint16_t dev_id, int base, int gpio)\n+{\n+\tchar buf[CNXK_GPIO_BUFSZ];\n+\tint ret, val, n;\n+\n+\tn = snprintf(buf, sizeof(buf), CNXK_GPIO_PATH_FMT, base + gpio);\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/direction\");\n+\tret = rte_pmd_gpio_set_pin_dir(dev_id, gpio, CNXK_GPIO_PIN_DIR_OUT);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set dir to out\");\n+\tret = cnxk_gpio_validate_attr(buf, \"out\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/value\");\n+\tret = rte_pmd_gpio_set_pin_value(dev_id, gpio, 0);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set value to 0\");\n+\tret = cnxk_gpio_validate_attr(buf, \"0\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\tret = rte_pmd_gpio_get_pin_value(dev_id, gpio, &val);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to read value\");\n+\tif (val)\n+\t\tret = -EIO;\n+\tCNXK_GPIO_ERR_STR(ret, \"read %d instead of 0\", val);\n+\n+\tret = rte_pmd_gpio_set_pin_value(dev_id, gpio, 1);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set value to 1\");\n+\tret = cnxk_gpio_validate_attr(buf, \"1\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\tret = rte_pmd_gpio_get_pin_value(dev_id, gpio, &val);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to read value\");\n+\tif (val != 1)\n+\t\tret = -EIO;\n+\tCNXK_GPIO_ERR_STR(ret, \"read %d instead of 1\", val);\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/direction\");\n+\tret = rte_pmd_gpio_set_pin_dir(dev_id, gpio, CNXK_GPIO_PIN_DIR_LOW);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set dir to low\");\n+\tret = cnxk_gpio_validate_attr(buf, \"out\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/value\");\n+\tret = cnxk_gpio_validate_attr(buf, \"0\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/direction\");\n+\tret = rte_pmd_gpio_set_pin_dir(dev_id, gpio, CNXK_GPIO_PIN_DIR_HIGH);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set dir to high\");\n+\tret = cnxk_gpio_validate_attr(buf, \"out\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/value\");\n+\tret = cnxk_gpio_validate_attr(buf, \"1\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/edge\");\n+\tret = rte_pmd_gpio_set_pin_edge(dev_id, gpio,\n+\t\t\t\t\tCNXK_GPIO_PIN_EDGE_FALLING);\n+\tret = ret == 0 ? -EIO : 0;\n+\tCNXK_GPIO_ERR_STR(ret, \"changed edge to falling\");\n+\tret = cnxk_gpio_validate_attr(buf, \"none\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tret = rte_pmd_gpio_set_pin_edge(dev_id, gpio,\n+\t\t\t\t\tCNXK_GPIO_PIN_EDGE_RISING);\n+\tret = ret == 0 ? -EIO : 0;\n+\tCNXK_GPIO_ERR_STR(ret, \"changed edge to rising\");\n+\tret = cnxk_gpio_validate_attr(buf, \"none\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tret = rte_pmd_gpio_set_pin_edge(dev_id, gpio, CNXK_GPIO_PIN_EDGE_BOTH);\n+\tret = ret == 0 ? -EIO : 0;\n+\tCNXK_GPIO_ERR_STR(ret, \"changed edge to both\");\n+\tret = cnxk_gpio_validate_attr(buf, \"none\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\t/* this one should succeed */\n+\tret = rte_pmd_gpio_set_pin_edge(dev_id, gpio, CNXK_GPIO_PIN_EDGE_NONE);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to change edge to none\");\n+\tret = cnxk_gpio_validate_attr(buf, \"none\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/active_low\");\n+\tret = rte_pmd_gpio_set_pin_active_low(dev_id, gpio, 1);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set active_low to 1\");\n+\tret = cnxk_gpio_validate_attr(buf, \"1\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tret = rte_pmd_gpio_get_pin_active_low(dev_id, gpio, &val);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to read active_low\");\n+\tif (val != 1)\n+\t\tret = -EIO;\n+\tCNXK_GPIO_ERR_STR(ret, \"read %d instead of 1\", val);\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/value\");\n+\tret = rte_pmd_gpio_set_pin_value(dev_id, gpio, 1);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set value to 1\");\n+\tret = cnxk_gpio_validate_attr(buf, \"1\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tret = rte_pmd_gpio_set_pin_value(dev_id, gpio, 0);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set value to 0\");\n+\tret = cnxk_gpio_validate_attr(buf, \"0\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+\tsnprintf(buf + n, sizeof(buf) - n, \"/active_low\");\n+\tret = rte_pmd_gpio_set_pin_active_low(dev_id, gpio, 0);\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to set active_low to 0\");\n+\tret = cnxk_gpio_validate_attr(buf, \"0\");\n+\tCNXK_GPIO_ERR_STR(ret, \"failed to validate %s\", buf);\n+\n+out:\n+\treturn ret;\n+}\n+\n+int\n+cnxk_gpio_selftest(uint16_t dev_id)\n+{\n+\tstruct cnxk_gpiochip *gpiochip;\n+\tunsigned int queues, i, size;\n+\tchar buf[CNXK_GPIO_BUFSZ];\n+\tstruct rte_rawdev *rawdev;\n+\tstruct cnxk_gpio *gpio;\n+\tint ret;\n+\n+\trawdev = rte_rawdev_pmd_get_named_dev(\"cnxk_gpio\");\n+\tgpiochip = rawdev->dev_private;\n+\n+\tqueues = rte_rawdev_queue_count(dev_id);\n+\tif (queues == 0)\n+\t\treturn -ENODEV;\n+\n+\tret = rte_rawdev_start(dev_id);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfd = open(\"/dev/otx-gpio-ctr\", O_RDWR | O_SYNC);\n+\tif (fd < 0)\n+\t\treturn -errno;\n+\n+\tfor (i = 0; i < queues; i++) {\n+\t\tRTE_LOG(INFO, PMD, \"testing queue %d (gpio%d)\\n\", i,\n+\t\t\tgpiochip->base + i);\n+\n+\t\tret = rte_rawdev_queue_conf_get(dev_id, i, &size, sizeof(size));\n+\t\tif (ret) {\n+\t\t\tRTE_LOG(ERR, PMD,\n+\t\t\t\t\"failed to read queue configuration (%d)\\n\",\n+\t\t\t\tret);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (size != 1) {\n+\t\t\tRTE_LOG(ERR, PMD, \"wrong queue size received\\n\");\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tret = rte_rawdev_queue_setup(dev_id, i, NULL, 0);\n+\t\tif (ret) {\n+\t\t\tRTE_LOG(ERR, PMD, \"failed to setup queue (%d)\\n\", ret);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tgpio = gpiochip->gpios[i];\n+\t\tsnprintf(buf, sizeof(buf), CNXK_GPIO_PATH_FMT, gpio->num);\n+\t\tif (!cnxk_gpio_attr_exists(buf)) {\n+\t\t\tRTE_LOG(ERR, PMD, \"%s does not exist\\n\", buf);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tret = cnxk_gpio_test_input(dev_id, gpiochip->base, i);\n+\t\tif (ret)\n+\t\t\tgoto release;\n+\n+\t\tret = cnxk_gpio_test_irq(dev_id, i);\n+\t\tif (ret)\n+\t\t\tgoto release;\n+\n+\t\tret = cnxk_gpio_test_output(dev_id, gpiochip->base, i);\n+\t\tif (ret)\n+\t\t\tgoto release;\n+\n+release:\n+\t\tret = rte_rawdev_queue_release(dev_id, i);\n+\t\tif (ret) {\n+\t\t\tRTE_LOG(ERR, PMD, \"failed to release queue (%d)\\n\",\n+\t\t\t\tret);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (cnxk_gpio_attr_exists(buf)) {\n+\t\t\tRTE_LOG(ERR, PMD, \"%s still exists\\n\", buf);\n+\t\t\tcontinue;\n+\t\t}\n+\t}\n+\n+\tclose(fd);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/raw/cnxk_gpio/meson.build b/drivers/raw/cnxk_gpio/meson.build\nindex 9b55f029c7..a75a5b9084 100644\n--- a/drivers/raw/cnxk_gpio/meson.build\n+++ b/drivers/raw/cnxk_gpio/meson.build\n@@ -6,5 +6,6 @@ deps += ['bus_vdev', 'common_cnxk', 'rawdev', 'kvargs']\n sources = files(\n 'cnxk_gpio.c',\n 'cnxk_gpio_irq.c',\n+ 'cnxk_gpio_selftest.c',\n )\n headers = files('rte_pmd_cnxk_gpio.h')\n", "prefixes": [ "v3", "10/10" ] }