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GET /api/patches/105092/?format=api
{ "id": 105092, "url": "http://patches.dpdk.org/api/patches/105092/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213081732.2096334-10-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211213081732.2096334-10-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211213081732.2096334-10-tduszynski@marvell.com", "date": "2021-12-13T08:17:31", "name": "[v3,09/10] raw/cnxk_gpio: support custom irq handlers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ca656145e7392e9336b056cd5fc2fecc37ce9fa6", "submitter": { "id": 2215, "url": "http://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213081732.2096334-10-tduszynski@marvell.com/mbox/", "series": [ { "id": 20921, "url": "http://patches.dpdk.org/api/series/20921/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20921", "date": "2021-12-13T08:17:22", "name": "Add cnxk_gpio PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/20921/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105092/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/105092/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 51799A00BE;\n\tMon, 13 Dec 2021 09:19:25 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1BA87411C9;\n\tMon, 13 Dec 2021 09:18:38 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id D418D411AE\n for <dev@dpdk.org>; Mon, 13 Dec 2021 09:18:35 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BD1Z3CR027207;\n Mon, 13 Dec 2021 00:18:35 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cwvmys385-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 13 Dec 2021 00:18:34 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 13 Dec 2021 00:18:34 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 13 Dec 2021 00:18:33 -0800", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 7FA2E3F7045;\n Mon, 13 Dec 2021 00:18:32 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=2GsUaHA13oXR8LSXQblVbmLoyEAJ0/CSsnxrR9Gqd7k=;\n b=Wwr9Vocvb9XgO87wZgf6cf/tArE7XlDaXdQQpCcalj0+YRfsBQyz4cI+T53JqkESyEu7\n V+4M3PV/tB0qv4jW0kQyZRbVmzyVoc8dzpZXm9BoQAxQ73ySXQt3ZjUgYwyPxOPzkAE7\n Bbeq4L9WOXMNqQvuqC5IKbMCe6xIDF+46B1UjG35OHd3FmHBmVUf9y9aHe4VxbS//Ki0\n nBb+jRj8apHM6QiwqbdFtc+haiCDPzoNhK2n8C2oUnudDh9Y0XvTbx7EXWbtIzaKvIyg\n IK5Q8vAQ5CEhp0+4ZPHVLM/FzgicxYcItiOY2Zq0y571ytQTyEaEKko55XPxAzoljBkz zw==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <stephen@networkplumber.org>, Tomasz Duszynski\n <tduszynski@marvell.com>", "Subject": "[PATCH v3 09/10] raw/cnxk_gpio: support custom irq handlers", "Date": "Mon, 13 Dec 2021 09:17:31 +0100", "Message-ID": "<20211213081732.2096334-10-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211213081732.2096334-1-tduszynski@marvell.com>", "References": "<20211128154442.4029049-1-tduszynski@marvell.com>\n <20211213081732.2096334-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "gjBjDExJWt7k7nUmh4TjmxIJkG54KzUj", "X-Proofpoint-ORIG-GUID": "gjBjDExJWt7k7nUmh4TjmxIJkG54KzUj", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_03,2021-12-10_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for custom interrupt handlers. Custom interrupt\nhandlers bypass kernel completely and are meant for fast\nand low latency access to GPIO state.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\n---\n doc/guides/rawdevs/cnxk_gpio.rst | 21 +++\n drivers/raw/cnxk_gpio/cnxk_gpio.c | 37 ++++\n drivers/raw/cnxk_gpio/cnxk_gpio.h | 8 +\n drivers/raw/cnxk_gpio/cnxk_gpio_irq.c | 216 ++++++++++++++++++++++\n drivers/raw/cnxk_gpio/meson.build | 1 +\n drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h | 116 ++++++++++++\n 6 files changed, 399 insertions(+)\n create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio_irq.c", "diff": "diff --git a/doc/guides/rawdevs/cnxk_gpio.rst b/doc/guides/rawdevs/cnxk_gpio.rst\nindex f6c3c942c5..ad93ec0d44 100644\n--- a/doc/guides/rawdevs/cnxk_gpio.rst\n+++ b/doc/guides/rawdevs/cnxk_gpio.rst\n@@ -161,3 +161,24 @@ Payload contains an integer set to 0 or 1. The latter means inverted logic\n is turned on.\n \n Consider using ``rte_pmd_gpio_get_pin_active_low()`` wrapper.\n+\n+Request interrupt\n+~~~~~~~~~~~~~~~~~\n+\n+Message is used to install custom interrupt handler.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_REGISTER_IRQ``.\n+\n+Payload needs to be set to ``struct cnxk_gpio_irq`` which describes interrupt\n+being requested.\n+\n+Consider using ``rte_pmd_gpio_register_gpio()`` wrapper.\n+\n+Free interrupt\n+~~~~~~~~~~~~~~\n+\n+Message is used to remove installed interrupt handler.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_UNREGISTER_IRQ``.\n+\n+Consider using ``rte_pmd_gpio_unregister_gpio()`` wrapper.\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.c b/drivers/raw/cnxk_gpio/cnxk_gpio.c\nindex fa5b1359d0..f3fdd5a380 100644\n--- a/drivers/raw/cnxk_gpio/cnxk_gpio.c\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.c\n@@ -335,6 +335,28 @@ cnxk_gpio_name_to_dir(const char *name)\n \treturn cnxk_gpio_dir_name[i].dir;\n }\n \n+static int\n+cnxk_gpio_register_irq(struct cnxk_gpio *gpio, struct cnxk_gpio_irq *irq)\n+{\n+\tint ret;\n+\n+\tret = cnxk_gpio_irq_request(gpio->num - gpio->gpiochip->base, irq->cpu);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tgpio->handler = irq->handler;\n+\tgpio->data = irq->data;\n+\tgpio->cpu = irq->cpu;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_gpio_unregister_irq(struct cnxk_gpio *gpio)\n+{\n+\treturn cnxk_gpio_irq_free(gpio->num - gpio->gpiochip->base);\n+}\n+\n static int\n cnxk_gpio_process_buf(struct cnxk_gpio *gpio, struct rte_rawdev_buf *rbuf)\n {\n@@ -416,6 +438,13 @@ cnxk_gpio_process_buf(struct cnxk_gpio *gpio, struct rte_rawdev_buf *rbuf)\n \n \t\t*(int *)rsp = val;\n \t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_REGISTER_IRQ:\n+\t\tret = cnxk_gpio_register_irq(gpio,\n+\t\t\t\t\t (struct cnxk_gpio_irq *)msg->data);\n+\t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_UNREGISTER_IRQ:\n+\t\tret = cnxk_gpio_unregister_irq(gpio);\n+\t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n@@ -519,6 +548,10 @@ cnxk_gpio_probe(struct rte_vdev_device *dev)\n \tif (ret)\n \t\tgoto out;\n \n+\tret = cnxk_gpio_irq_init(gpiochip);\n+\tif (ret)\n+\t\tgoto out;\n+\n \t/* read gpio base */\n \tsnprintf(buf, sizeof(buf), \"%s/gpiochip%d/base\", CNXK_GPIO_CLASS_PATH,\n \t\t gpiochip->num);\n@@ -577,10 +610,14 @@ cnxk_gpio_remove(struct rte_vdev_device *dev)\n \t\tif (!gpio)\n \t\t\tcontinue;\n \n+\t\tif (gpio->handler)\n+\t\t\tcnxk_gpio_unregister_irq(gpio);\n+\n \t\tcnxk_gpio_queue_release(rawdev, gpio->num);\n \t}\n \n \trte_free(gpiochip->gpios);\n+\tcnxk_gpio_irq_fini();\n \trte_rawdev_pmd_release(rawdev);\n \n \treturn 0;\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.h b/drivers/raw/cnxk_gpio/cnxk_gpio.h\nindex 6b54ebe6e6..c052ca5735 100644\n--- a/drivers/raw/cnxk_gpio/cnxk_gpio.h\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.h\n@@ -11,6 +11,9 @@ struct cnxk_gpio {\n \tstruct cnxk_gpiochip *gpiochip;\n \tvoid *rsp;\n \tint num;\n+\tvoid (*handler)(int gpio, void *data);\n+\tvoid *data;\n+\tint cpu;\n };\n \n struct cnxk_gpiochip {\n@@ -20,4 +23,9 @@ struct cnxk_gpiochip {\n \tstruct cnxk_gpio **gpios;\n };\n \n+int cnxk_gpio_irq_init(struct cnxk_gpiochip *gpiochip);\n+void cnxk_gpio_irq_fini(void);\n+int cnxk_gpio_irq_request(int gpio, int cpu);\n+int cnxk_gpio_irq_free(int gpio);\n+\n #endif /* _CNXK_GPIO_H_ */\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio_irq.c b/drivers/raw/cnxk_gpio/cnxk_gpio_irq.c\nnew file mode 100644\nindex 0000000000..2fa8e69899\n--- /dev/null\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio_irq.c\n@@ -0,0 +1,216 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <fcntl.h>\n+#include <pthread.h>\n+#include <sys/ioctl.h>\n+#include <sys/mman.h>\n+#include <sys/queue.h>\n+#include <unistd.h>\n+\n+#include <rte_rawdev_pmd.h>\n+\n+#include <roc_api.h>\n+\n+#include \"cnxk_gpio.h\"\n+\n+#define OTX_IOC_MAGIC 0xF2\n+#define OTX_IOC_SET_GPIO_HANDLER \\\n+\t_IOW(OTX_IOC_MAGIC, 1, struct otx_gpio_usr_data)\n+#define OTX_IOC_CLR_GPIO_HANDLER \\\n+\t_IO(OTX_IOC_MAGIC, 2)\n+\n+struct otx_gpio_usr_data {\n+\tuint64_t isr_base;\n+\tuint64_t sp;\n+\tuint64_t cpu;\n+\tuint64_t gpio_num;\n+};\n+\n+struct cnxk_gpio_irq_stack {\n+\tLIST_ENTRY(cnxk_gpio_irq_stack) next;\n+\tvoid *sp_buffer;\n+\tint cpu;\n+\tint inuse;\n+};\n+\n+struct cnxk_gpio_irqchip {\n+\tint fd;\n+\t/* serialize access to this struct */\n+\tpthread_mutex_t lock;\n+\tLIST_HEAD(, cnxk_gpio_irq_stack) stacks;\n+\n+\tstruct cnxk_gpiochip *gpiochip;\n+};\n+\n+static struct cnxk_gpio_irqchip *irqchip;\n+\n+static void\n+cnxk_gpio_irq_stack_free(int cpu)\n+{\n+\tstruct cnxk_gpio_irq_stack *stack;\n+\n+\tLIST_FOREACH(stack, &irqchip->stacks, next) {\n+\t\tif (stack->cpu == cpu)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (!stack)\n+\t\treturn;\n+\n+\tif (stack->inuse)\n+\t\tstack->inuse--;\n+\n+\tif (stack->inuse == 0) {\n+\t\tLIST_REMOVE(stack, next);\n+\t\trte_free(stack->sp_buffer);\n+\t\trte_free(stack);\n+\t}\n+}\n+\n+static void *\n+cnxk_gpio_irq_stack_alloc(int cpu)\n+{\n+#define ARM_STACK_ALIGNMENT (2 * sizeof(void *))\n+#define IRQ_STACK_SIZE 0x200000\n+\n+\tstruct cnxk_gpio_irq_stack *stack;\n+\n+\tLIST_FOREACH(stack, &irqchip->stacks, next) {\n+\t\tif (stack->cpu == cpu)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (stack) {\n+\t\tstack->inuse++;\n+\t\treturn (char *)stack->sp_buffer + IRQ_STACK_SIZE;\n+\t}\n+\n+\tstack = rte_malloc(NULL, sizeof(*stack), 0);\n+\tif (!stack)\n+\t\treturn NULL;\n+\n+\tstack->sp_buffer =\n+\t\trte_zmalloc(NULL, IRQ_STACK_SIZE * 2, ARM_STACK_ALIGNMENT);\n+\tif (!stack->sp_buffer) {\n+\t\trte_free(stack);\n+\t\treturn NULL;\n+\t}\n+\n+\tstack->cpu = cpu;\n+\tstack->inuse = 1;\n+\tLIST_INSERT_HEAD(&irqchip->stacks, stack, next);\n+\n+\treturn (char *)stack->sp_buffer + IRQ_STACK_SIZE;\n+}\n+\n+static void\n+cnxk_gpio_irq_handler(int gpio_num)\n+{\n+\tstruct cnxk_gpiochip *gpiochip = irqchip->gpiochip;\n+\tstruct cnxk_gpio *gpio;\n+\n+\tif (gpio_num >= gpiochip->num_gpios)\n+\t\tgoto out;\n+\n+\tgpio = gpiochip->gpios[gpio_num];\n+\tif (likely(gpio->handler))\n+\t\tgpio->handler(gpio_num, gpio->data);\n+\n+out:\n+\troc_atf_ret();\n+}\n+\n+int\n+cnxk_gpio_irq_init(struct cnxk_gpiochip *gpiochip)\n+{\n+\tif (irqchip)\n+\t\treturn 0;\n+\n+\tirqchip = rte_zmalloc(NULL, sizeof(*irqchip), 0);\n+\tif (!irqchip)\n+\t\treturn -ENOMEM;\n+\n+\tirqchip->fd = open(\"/dev/otx-gpio-ctr\", O_RDWR | O_SYNC);\n+\tif (irqchip->fd < 0) {\n+\t\trte_free(irqchip);\n+\t\treturn -errno;\n+\t}\n+\n+\tpthread_mutex_init(&irqchip->lock, NULL);\n+\tLIST_INIT(&irqchip->stacks);\n+\tirqchip->gpiochip = gpiochip;\n+\n+\treturn 0;\n+}\n+\n+void\n+cnxk_gpio_irq_fini(void)\n+{\n+\tif (!irqchip)\n+\t\treturn;\n+\n+\tclose(irqchip->fd);\n+\trte_free(irqchip);\n+\tirqchip = NULL;\n+}\n+\n+int\n+cnxk_gpio_irq_request(int gpio, int cpu)\n+{\n+\tstruct otx_gpio_usr_data data;\n+\tvoid *sp;\n+\tint ret;\n+\n+\tpthread_mutex_lock(&irqchip->lock);\n+\n+\tsp = cnxk_gpio_irq_stack_alloc(cpu);\n+\tif (!sp) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out_unlock;\n+\t}\n+\n+\tdata.isr_base = (uint64_t)cnxk_gpio_irq_handler;\n+\tdata.sp = (uint64_t)sp;\n+\tdata.cpu = (uint64_t)cpu;\n+\tdata.gpio_num = (uint64_t)gpio;\n+\n+\tmlockall(MCL_CURRENT | MCL_FUTURE);\n+\tret = ioctl(irqchip->fd, OTX_IOC_SET_GPIO_HANDLER, &data);\n+\tif (ret) {\n+\t\tret = -errno;\n+\t\tgoto out_free_stack;\n+\t}\n+\n+\tpthread_mutex_unlock(&irqchip->lock);\n+\n+\treturn 0;\n+\n+out_free_stack:\n+\tcnxk_gpio_irq_stack_free(cpu);\n+out_unlock:\n+\tpthread_mutex_unlock(&irqchip->lock);\n+\n+\treturn ret;\n+}\n+\n+int\n+cnxk_gpio_irq_free(int gpio)\n+{\n+\tint ret;\n+\n+\tpthread_mutex_lock(&irqchip->lock);\n+\n+\tret = ioctl(irqchip->fd, OTX_IOC_CLR_GPIO_HANDLER, gpio);\n+\tif (ret) {\n+\t\tpthread_mutex_unlock(&irqchip->lock);\n+\t\treturn -errno;\n+\t}\n+\n+\tcnxk_gpio_irq_stack_free(irqchip->gpiochip->gpios[gpio]->cpu);\n+\n+\tpthread_mutex_unlock(&irqchip->lock);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/raw/cnxk_gpio/meson.build b/drivers/raw/cnxk_gpio/meson.build\nindex 3fbfdd838c..9b55f029c7 100644\n--- a/drivers/raw/cnxk_gpio/meson.build\n+++ b/drivers/raw/cnxk_gpio/meson.build\n@@ -5,5 +5,6 @@\n deps += ['bus_vdev', 'common_cnxk', 'rawdev', 'kvargs']\n sources = files(\n 'cnxk_gpio.c',\n+ 'cnxk_gpio_irq.c',\n )\n headers = files('rte_pmd_cnxk_gpio.h')\ndiff --git a/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h b/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\nindex 7c3dc225ca..e3096dc14f 100644\n--- a/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\n+++ b/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\n@@ -40,6 +40,10 @@ enum cnxk_gpio_msg_type {\n \tCNXK_GPIO_MSG_TYPE_GET_PIN_DIR,\n \t/** Type used to read inverted logic state */\n \tCNXK_GPIO_MSG_TYPE_GET_PIN_ACTIVE_LOW,\n+\t/** Type used to register interrupt handler */\n+\tCNXK_GPIO_MSG_TYPE_REGISTER_IRQ,\n+\t/** Type used to remove interrupt handler */\n+\tCNXK_GPIO_MSG_TYPE_UNREGISTER_IRQ,\n };\n \n /** Available edges */\n@@ -66,6 +70,25 @@ enum cnxk_gpio_pin_dir {\n \tCNXK_GPIO_PIN_DIR_LOW,\n };\n \n+/**\n+ * GPIO interrupt handler\n+ *\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param data\n+ * Cookie passed to interrupt handler\n+ */\n+typedef void (*cnxk_gpio_irq_handler_t)(int gpio, void *data);\n+\n+struct cnxk_gpio_irq {\n+\t/** Interrupt handler */\n+\tcnxk_gpio_irq_handler_t handler;\n+\t/** User data passed to irq handler */\n+\tvoid *data;\n+\t/** CPU which will run irq handler */\n+\tint cpu;\n+};\n+\n struct cnxk_gpio_msg {\n \t/** Message type */\n \tenum cnxk_gpio_msg_type type;\n@@ -306,6 +329,99 @@ rte_pmd_gpio_get_pin_active_low(uint16_t dev_id, int gpio, int *val)\n \treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, val, sizeof(*val));\n }\n \n+/**\n+ * Attach interrupt handler to GPIO\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param cpu\n+ * CPU which will be handling interrupt\n+ * @param handler\n+ * Interrupt handler to be executed\n+ * @param data\n+ * Data to be passed to interrupt handler\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_register_irq(uint16_t dev_id, int gpio, int cpu,\n+\t\t\t cnxk_gpio_irq_handler_t handler, void *data)\n+{\n+\tstruct cnxk_gpio_irq irq = {\n+\t\t.handler = handler,\n+\t\t.data = data,\n+\t\t.cpu = cpu,\n+\t};\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_REGISTER_IRQ,\n+\t\t.data = &irq,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, NULL, 0);\n+}\n+\n+/**\n+ * Detach interrupt handler from GPIO\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_unregister_irq(uint16_t dev_id, int gpio)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_UNREGISTER_IRQ,\n+\t\t.data = &gpio,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, NULL, 0);\n+}\n+\n+/**\n+ * Enable interrupt\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param edge\n+ * Edge that should trigger interrupt\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_enable_interrupt(uint16_t dev_id, int gpio,\n+\t\t\t enum cnxk_gpio_pin_edge edge)\n+{\n+\treturn rte_pmd_gpio_set_pin_edge(dev_id, gpio, edge);\n+}\n+\n+/**\n+ * Disable interrupt\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_disable_interrupt(uint16_t dev_id, int gpio)\n+{\n+\treturn rte_pmd_gpio_set_pin_edge(dev_id, gpio, CNXK_GPIO_PIN_EDGE_NONE);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "v3", "09/10" ] }