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GET /api/patches/105091/?format=api
{ "id": 105091, "url": "http://patches.dpdk.org/api/patches/105091/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213081732.2096334-9-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211213081732.2096334-9-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211213081732.2096334-9-tduszynski@marvell.com", "date": "2021-12-13T08:17:30", "name": "[v3,08/10] raw/cnxk_gpio: support standard GPIO operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "00bd6509c36ca8d53fac539edb5968e51113ca93", "submitter": { "id": 2215, "url": "http://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213081732.2096334-9-tduszynski@marvell.com/mbox/", "series": [ { "id": 20921, "url": "http://patches.dpdk.org/api/series/20921/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20921", "date": "2021-12-13T08:17:22", "name": "Add cnxk_gpio PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/20921/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105091/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/105091/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 64B12A00BE;\n\tMon, 13 Dec 2021 09:19:18 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 21836411AE;\n\tMon, 13 Dec 2021 09:18:37 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6AAB7411AB\n for <dev@dpdk.org>; Mon, 13 Dec 2021 09:18:35 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BD7ieBh027462;\n Mon, 13 Dec 2021 00:18:34 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cx21kg3bw-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 13 Dec 2021 00:18:34 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Dec 2021 00:18:32 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 13 Dec 2021 00:18:32 -0800", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 947E73F7045;\n Mon, 13 Dec 2021 00:18:30 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=9HTx+j9gv++dHX8+mYYIDXMbafD6V05bUDwhO2LCMYE=;\n b=S2YSJrBCzWrin9CKfu/KUduSwQUQHOx8+jG4QpCVjPr7u74EjIv/LZELvrGsI5i/hnvx\n 7yZGJEbxLjKeXVNj/yxjjP6/E3/ff8B8wyumlwZCH7D6b12eNSa1iSankwUEZ4/Y8sq2\n cXgSc2Ay/xxfGX36yLUpApyrNsRx6Qsdel5VYRC2/a4WK3gRjGDQrmnll36UxpsvaPeX\n jzvuC9wp5CvxOvx6yDzmHiC5/WcjbK8BpGARcyrXzThPi+gdO9faQoJnDLVtFFRseabf\n WIyx6reu23XLLCjXJ80gOrdAItq8kT10t/z1pJfamUlIQFwqrLp6Dtho9FjQJhTnk6MY 5Q==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <stephen@networkplumber.org>, Tomasz Duszynski\n <tduszynski@marvell.com>", "Subject": "[PATCH v3 08/10] raw/cnxk_gpio: support standard GPIO operations", "Date": "Mon, 13 Dec 2021 09:17:30 +0100", "Message-ID": "<20211213081732.2096334-9-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211213081732.2096334-1-tduszynski@marvell.com>", "References": "<20211128154442.4029049-1-tduszynski@marvell.com>\n <20211213081732.2096334-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "usbhVl242GKbDDz0Lxf7dV6t3_7unhIz", "X-Proofpoint-ORIG-GUID": "usbhVl242GKbDDz0Lxf7dV6t3_7unhIz", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_03,2021-12-10_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for standard GPIO operations i.e ones normally\nprovided by GPIO sysfs interface.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\n---\n doc/guides/rawdevs/cnxk_gpio.rst | 98 ++++++++\n drivers/raw/cnxk_gpio/cnxk_gpio.c | 146 +++++++++++\n drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h | 279 +++++++++++++++++++++-\n 3 files changed, 521 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/rawdevs/cnxk_gpio.rst b/doc/guides/rawdevs/cnxk_gpio.rst\nindex 868302d07f..f6c3c942c5 100644\n--- a/doc/guides/rawdevs/cnxk_gpio.rst\n+++ b/doc/guides/rawdevs/cnxk_gpio.rst\n@@ -63,3 +63,101 @@ call barely exports GPIO to userspace.\n To perform actual data transfer use standard ``rte_rawdev_enqueue_buffers()``\n and ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible\n responses hence dequeueing is not always necessary.\n+\n+CNXK GPIO PMD\n+-------------\n+\n+PMD accepts ``struct cnxk_gpio_msg`` messages which differ by type and payload.\n+Message types along with description are listed below. As for the usage examples\n+please refer to ``cnxk_gpio_selftest()``. There's a set of convenient wrappers\n+available, one for each existing command.\n+\n+Set GPIO value\n+~~~~~~~~~~~~~~\n+\n+Message is used to set output to low or high. This does not work for GPIOs\n+configured as input.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_SET_PIN_VALUE``.\n+\n+Payload must be an integer set to 0 (low) or 1 (high).\n+\n+Consider using ``rte_pmd_gpio_set_pin_value()`` wrapper.\n+\n+Set GPIO edge\n+~~~~~~~~~~~~~\n+\n+Message is used to set edge that triggers interrupt.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_SET_PIN_EDGE``.\n+\n+Payload must be `enum cnxk_gpio_pin_edge`.\n+\n+Consider using ``rte_pmd_gpio_set_pin_edge()`` wrapper.\n+\n+Set GPIO direction\n+~~~~~~~~~~~~~~~~~~\n+\n+Message is used to change GPIO direction to either input or output.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_SET_PIN_DIR``.\n+\n+Payload must be `enum cnxk_gpio_pin_dir`.\n+\n+Consider using ``rte_pmd_gpio_set_pin_dir()`` wrapper.\n+\n+Set GPIO active low\n+~~~~~~~~~~~~~~~~~~~\n+\n+Message is used to set whether pin is active low.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_SET_PIN_ACTIVE_LOW``.\n+\n+Payload must be an integer set to 0 or 1. The latter activates inversion.\n+\n+Consider using ``rte_pmd_gpio_set_pin_active_low()`` wrapper.\n+\n+Get GPIO value\n+~~~~~~~~~~~~~~\n+\n+Message is used to read GPIO value. Value can be 0 (low) or 1 (high).\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_GET_PIN_VALUE``.\n+\n+Payload contains integer set to either 0 or 1.\n+\n+Consider using ``rte_pmd_gpio_get_pin_value()`` wrapper.\n+\n+Get GPIO edge\n+~~~~~~~~~~~~~\n+\n+Message is used to read GPIO edge.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_GET_PIN_EDGE``.\n+\n+Payload contains `enum cnxk_gpio_pin_edge`.\n+\n+Consider using ``rte_pmd_gpio_get_pin_edge()`` wrapper.\n+\n+Get GPIO direction\n+~~~~~~~~~~~~~~~~~~\n+\n+Message is used to read GPIO direction.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_GET_PIN_DIR``.\n+\n+Payload contains `enum cnxk_gpio_pin_dir`.\n+\n+Consider using ``rte_pmd_gpio_get_pin_dir()`` wrapper.\n+\n+Get GPIO active low\n+~~~~~~~~~~~~~~~~~~~\n+\n+Message is used check whether inverted logic is active.\n+\n+Message must have type set to ``CNXK_GPIO_MSG_TYPE_GET_PIN_ACTIVE_LOW``.\n+\n+Payload contains an integer set to 0 or 1. The latter means inverted logic\n+is turned on.\n+\n+Consider using ``rte_pmd_gpio_get_pin_active_low()`` wrapper.\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.c b/drivers/raw/cnxk_gpio/cnxk_gpio.c\nindex 570d9abb17..fa5b1359d0 100644\n--- a/drivers/raw/cnxk_gpio/cnxk_gpio.c\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.c\n@@ -263,13 +263,159 @@ cnxk_gpio_queue_count(struct rte_rawdev *dev)\n \treturn gpiochip->num_gpios;\n }\n \n+static const struct {\n+\tenum cnxk_gpio_pin_edge edge;\n+\tconst char *name;\n+} cnxk_gpio_edge_name[] = {\n+\t{ CNXK_GPIO_PIN_EDGE_NONE, \"none\" },\n+\t{ CNXK_GPIO_PIN_EDGE_FALLING, \"falling\" },\n+\t{ CNXK_GPIO_PIN_EDGE_RISING, \"rising\" },\n+\t{ CNXK_GPIO_PIN_EDGE_BOTH, \"both\" },\n+};\n+\n+static const char *\n+cnxk_gpio_edge_to_name(enum cnxk_gpio_pin_edge edge)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < RTE_DIM(cnxk_gpio_edge_name); i++) {\n+\t\tif (cnxk_gpio_edge_name[i].edge == edge)\n+\t\t\treturn cnxk_gpio_edge_name[i].name;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static enum cnxk_gpio_pin_edge\n+cnxk_gpio_name_to_edge(const char *name)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < RTE_DIM(cnxk_gpio_edge_name); i++) {\n+\t\tif (!strcmp(cnxk_gpio_edge_name[i].name, name))\n+\t\t\tbreak;\n+\t}\n+\n+\treturn cnxk_gpio_edge_name[i].edge;\n+}\n+\n+static const struct {\n+\tenum cnxk_gpio_pin_dir dir;\n+\tconst char *name;\n+} cnxk_gpio_dir_name[] = {\n+\t{ CNXK_GPIO_PIN_DIR_IN, \"in\" },\n+\t{ CNXK_GPIO_PIN_DIR_OUT, \"out\" },\n+\t{ CNXK_GPIO_PIN_DIR_HIGH, \"high\" },\n+\t{ CNXK_GPIO_PIN_DIR_LOW, \"low\" },\n+};\n+\n+static const char *\n+cnxk_gpio_dir_to_name(enum cnxk_gpio_pin_dir dir)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < RTE_DIM(cnxk_gpio_dir_name); i++) {\n+\t\tif (cnxk_gpio_dir_name[i].dir == dir)\n+\t\t\treturn cnxk_gpio_dir_name[i].name;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static enum cnxk_gpio_pin_dir\n+cnxk_gpio_name_to_dir(const char *name)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < RTE_DIM(cnxk_gpio_dir_name); i++) {\n+\t\tif (!strcmp(cnxk_gpio_dir_name[i].name, name))\n+\t\t\tbreak;\n+\t}\n+\n+\treturn cnxk_gpio_dir_name[i].dir;\n+}\n+\n static int\n cnxk_gpio_process_buf(struct cnxk_gpio *gpio, struct rte_rawdev_buf *rbuf)\n {\n \tstruct cnxk_gpio_msg *msg = rbuf->buf_addr;\n+\tenum cnxk_gpio_pin_edge edge;\n+\tenum cnxk_gpio_pin_dir dir;\n+\tchar buf[CNXK_GPIO_BUFSZ];\n \tvoid *rsp = NULL;\n+\tint ret, val, n;\n+\n+\tn = snprintf(buf, sizeof(buf), \"%s/gpio%d\", CNXK_GPIO_CLASS_PATH,\n+\t\t gpio->num);\n \n \tswitch (msg->type) {\n+\tcase CNXK_GPIO_MSG_TYPE_SET_PIN_VALUE:\n+\t\tsnprintf(buf + n, sizeof(buf) - n, \"/value\");\n+\t\tret = cnxk_gpio_write_attr_int(buf, !!*(int *)msg->data);\n+\t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_SET_PIN_EDGE:\n+\t\tsnprintf(buf + n, sizeof(buf) - n, \"/edge\");\n+\t\tedge = *(enum cnxk_gpio_pin_edge *)msg->data;\n+\t\tret = cnxk_gpio_write_attr(buf, cnxk_gpio_edge_to_name(edge));\n+\t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_SET_PIN_DIR:\n+\t\tsnprintf(buf + n, sizeof(buf) - n, \"/direction\");\n+\t\tdir = *(enum cnxk_gpio_pin_dir *)msg->data;\n+\t\tret = cnxk_gpio_write_attr(buf, cnxk_gpio_dir_to_name(dir));\n+\t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_SET_PIN_ACTIVE_LOW:\n+\t\tsnprintf(buf + n, sizeof(buf) - n, \"/active_low\");\n+\t\tval = *(int *)msg->data;\n+\t\tret = cnxk_gpio_write_attr_int(buf, val);\n+\t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_GET_PIN_VALUE:\n+\t\tsnprintf(buf + n, sizeof(buf) - n, \"/value\");\n+\t\tret = cnxk_gpio_read_attr_int(buf, &val);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\trsp = rte_zmalloc(NULL, sizeof(int), 0);\n+\t\tif (!rsp)\n+\t\t\treturn -ENOMEM;\n+\n+\t\t*(int *)rsp = val;\n+\t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_GET_PIN_EDGE:\n+\t\tsnprintf(buf + n, sizeof(buf) - n, \"/edge\");\n+\t\tret = cnxk_gpio_read_attr(buf, buf);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\trsp = rte_zmalloc(NULL, sizeof(enum cnxk_gpio_pin_edge), 0);\n+\t\tif (!rsp)\n+\t\t\treturn -ENOMEM;\n+\n+\t\t*(enum cnxk_gpio_pin_edge *)rsp = cnxk_gpio_name_to_edge(buf);\n+\t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_GET_PIN_DIR:\n+\t\tsnprintf(buf + n, sizeof(buf) - n, \"/direction\");\n+\t\tret = cnxk_gpio_read_attr(buf, buf);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\trsp = rte_zmalloc(NULL, sizeof(enum cnxk_gpio_pin_dir), 0);\n+\t\tif (!rsp)\n+\t\t\treturn -ENOMEM;\n+\n+\t\t*(enum cnxk_gpio_pin_dir *)rsp = cnxk_gpio_name_to_dir(buf);\n+\t\tbreak;\n+\tcase CNXK_GPIO_MSG_TYPE_GET_PIN_ACTIVE_LOW:\n+\t\tsnprintf(buf + n, sizeof(buf) - n, \"/active_low\");\n+\t\tret = cnxk_gpio_read_attr_int(buf, &val);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\trsp = rte_zmalloc(NULL, sizeof(int), 0);\n+\t\tif (!rsp)\n+\t\t\treturn -ENOMEM;\n+\n+\t\t*(int *)rsp = val;\n+\t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\ndiff --git a/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h b/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\nindex c71065e10c..7c3dc225ca 100644\n--- a/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\n+++ b/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h\n@@ -5,6 +5,10 @@\n #ifndef _RTE_PMD_CNXK_GPIO_H_\n #define _RTE_PMD_CNXK_GPIO_H_\n \n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_rawdev.h>\n+\n /**\n * @file rte_pmd_cnxk_gpio.h\n *\n@@ -20,8 +24,46 @@ extern \"C\" {\n \n /** Available message types */\n enum cnxk_gpio_msg_type {\n-\t/** Invalid message type */\n-\tCNXK_GPIO_MSG_TYPE_INVALID,\n+\t/** Type used to set output value */\n+\tCNXK_GPIO_MSG_TYPE_SET_PIN_VALUE,\n+\t/** Type used to set edge */\n+\tCNXK_GPIO_MSG_TYPE_SET_PIN_EDGE,\n+\t/** Type used to set direction */\n+\tCNXK_GPIO_MSG_TYPE_SET_PIN_DIR,\n+\t/** Type used to set inverted logic */\n+\tCNXK_GPIO_MSG_TYPE_SET_PIN_ACTIVE_LOW,\n+\t/** Type used to read value */\n+\tCNXK_GPIO_MSG_TYPE_GET_PIN_VALUE,\n+\t/** Type used to read edge */\n+\tCNXK_GPIO_MSG_TYPE_GET_PIN_EDGE,\n+\t/** Type used to read direction */\n+\tCNXK_GPIO_MSG_TYPE_GET_PIN_DIR,\n+\t/** Type used to read inverted logic state */\n+\tCNXK_GPIO_MSG_TYPE_GET_PIN_ACTIVE_LOW,\n+};\n+\n+/** Available edges */\n+enum cnxk_gpio_pin_edge {\n+\t/** Set edge to none */\n+\tCNXK_GPIO_PIN_EDGE_NONE,\n+\t/** Set edge to falling */\n+\tCNXK_GPIO_PIN_EDGE_FALLING,\n+\t/** Set edge to rising */\n+\tCNXK_GPIO_PIN_EDGE_RISING,\n+\t/** Set edge to both rising and falling */\n+\tCNXK_GPIO_PIN_EDGE_BOTH,\n+};\n+\n+/** Available directions */\n+enum cnxk_gpio_pin_dir {\n+\t/** Set direction to input */\n+\tCNXK_GPIO_PIN_DIR_IN,\n+\t/** Set direction to output */\n+\tCNXK_GPIO_PIN_DIR_OUT,\n+\t/** Set direction to output and value to 1 */\n+\tCNXK_GPIO_PIN_DIR_HIGH,\n+\t/* Set direction to output and value to 0 */\n+\tCNXK_GPIO_PIN_DIR_LOW,\n };\n \n struct cnxk_gpio_msg {\n@@ -31,6 +73,239 @@ struct cnxk_gpio_msg {\n \tvoid *data;\n };\n \n+/** @internal helper routine for enqueuing/dequeuing messages */\n+static __rte_always_inline int\n+__rte_pmd_gpio_enq_deq(uint16_t dev_id, int gpio, void *req, void *rsp,\n+\t\t size_t rsp_size)\n+{\n+\tstruct rte_rawdev_buf *bufs[1];\n+\tstruct rte_rawdev_buf buf;\n+\tvoid *q;\n+\tint ret;\n+\n+\tq = (void *)(size_t)gpio;\n+\tbuf.buf_addr = req;\n+\tbufs[0] = &buf;\n+\n+\tret = rte_rawdev_enqueue_buffers(dev_id, bufs, RTE_DIM(bufs), q);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tif (ret != RTE_DIM(bufs))\n+\t\treturn -EIO;\n+\n+\tif (!rsp)\n+\t\treturn 0;\n+\n+\tret = rte_rawdev_dequeue_buffers(dev_id, bufs, RTE_DIM(bufs), q);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tif (ret != RTE_DIM(bufs))\n+\t\treturn -EIO;\n+\n+\trte_memcpy(rsp, buf.buf_addr, rsp_size);\n+\trte_free(buf.buf_addr);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Set output to specific value\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param val\n+ * Value output will be set to. 0 represents low state while\n+ * 1 high state\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_set_pin_value(uint16_t dev_id, int gpio, int val)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_SET_PIN_VALUE,\n+\t\t.data = &val,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, NULL, 0);\n+}\n+\n+/**\n+ * Select signal edge that triggers interrupt\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param edge\n+ * Signal edge that triggers interrupt\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_set_pin_edge(uint16_t dev_id, int gpio,\n+\t\t\t enum cnxk_gpio_pin_edge edge)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_SET_PIN_EDGE,\n+\t\t.data = &edge\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, NULL, 0);\n+}\n+\n+/**\n+ * Configure GPIO as input or output\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param dir\n+ * Direction of the GPIO\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_set_pin_dir(uint16_t dev_id, int gpio, enum cnxk_gpio_pin_dir dir)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_SET_PIN_DIR,\n+\t\t.data = &dir,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, NULL, 0);\n+}\n+\n+/**\n+ * Enable or disable inverted logic\n+ *\n+ * If GPIO is configured as output then writing 1 or 0 will result in setting\n+ * output to respectively low or high\n+ *\n+ * If GPIO is configured as input then logic inversion applies to edges. Both\n+ * current and future settings are affected\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param val\n+ * 0 to disable, 1 to enable inverted logic\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_set_pin_active_low(uint16_t dev_id, int gpio, int val)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_SET_PIN_ACTIVE_LOW,\n+\t\t.data = &val,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, NULL, 0);\n+}\n+\n+/**\n+ * Read GPIO value\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param val\n+ * Where to store read logical signal value i.e 0 or 1\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_get_pin_value(uint16_t dev_id, int gpio, int *val)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_GET_PIN_VALUE,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, val, sizeof(*val));\n+}\n+\n+/**\n+ * Read GPIO edge\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param edge\n+ * Where to store edge\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_get_pin_edge(uint16_t dev_id, int gpio,\n+\t\t\t enum cnxk_gpio_pin_edge *edge)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_GET_PIN_EDGE,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, edge, sizeof(*edge));\n+}\n+\n+/**\n+ * Read GPIO direction\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param dir\n+ * Where to store direction\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_get_pin_dir(uint16_t dev_id, int gpio, enum cnxk_gpio_pin_dir *dir)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_GET_PIN_DIR,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, dir, sizeof(*dir));\n+}\n+\n+/**\n+ * Read whether GPIO is active low\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param gpio\n+ * Zero-based GPIO number\n+ * @param val\n+ * Where to store active low state\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_gpio_get_pin_active_low(uint16_t dev_id, int gpio, int *val)\n+{\n+\tstruct cnxk_gpio_msg msg = {\n+\t\t.type = CNXK_GPIO_MSG_TYPE_GET_PIN_ACTIVE_LOW,\n+\t\t.data = &val,\n+\t};\n+\n+\treturn __rte_pmd_gpio_enq_deq(dev_id, gpio, &msg, val, sizeof(*val));\n+}\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "v3", "08/10" ] }