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GET /api/patches/103977/?format=api
{ "id": 103977, "url": "http://patches.dpdk.org/api/patches/103977/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211108185805.3887-8-eagostini@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211108185805.3887-8-eagostini@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211108185805.3887-8-eagostini@nvidia.com", "date": "2021-11-08T18:58:03", "name": "[v5,7/9] gpudev: add communication flag", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "944889f0e641b7149e74de3403ea9f2fc6dc58ac", "submitter": { "id": 1571, "url": "http://patches.dpdk.org/api/people/1571/?format=api", "name": "Elena Agostini", "email": "eagostini@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211108185805.3887-8-eagostini@nvidia.com/mbox/", "series": [ { "id": 20381, "url": "http://patches.dpdk.org/api/series/20381/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20381", "date": "2021-11-08T18:57:56", "name": "GPU library", "version": 5, "mbox": "http://patches.dpdk.org/series/20381/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103977/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/103977/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DE313A0C4D;\n\tMon, 8 Nov 2021 11:48:01 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5D30141157;\n\tMon, 8 Nov 2021 11:47:14 +0100 (CET)", "from NAM04-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam08on2073.outbound.protection.outlook.com [40.107.101.73])\n by mails.dpdk.org (Postfix) with ESMTP id 3F42941145\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "<eagostini@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Elena Agostini <eagostini@nvidia.com>", "Date": "Mon, 8 Nov 2021 18:58:03 +0000", "Message-ID": "<20211108185805.3887-8-eagostini@nvidia.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211108185805.3887-1-eagostini@nvidia.com>", "References": "<20210602203531.2288645-1-thomas@monjalon.net>\n <20211108185805.3887-1-eagostini@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "0c5cf90a-0028-4ef8-20b6-08d9a2a51cef", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB4301:", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB4301FEA47BC057D4F1DE4734CD919@MN2PR12MB4301.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:117;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n YYTpV2O/rtsL4R9u8e0B57FzXMOqwGyGrfIe3K+B8OCJu4krxmRHS3cCbM3gWKhkqc3mgcyM4Yw8QPvUYbEIFnKFjI4i+Kjxk4QCsC3926cVFXSEUCk+TN+cvtR4xJgFGRTKg4A5+2ySsHlffx9ntIjjthg6xjk/spz0jdMIq9jX31WVNuuZmEUkhA023g2/8Fsjt7xngV/nSC2FNEstm7HmzczMY3s8MDHG5PsywCo9cGm+BqjwFMxreFvX0g8oJxpXxhY5LSxUnKRQXC76FJUdOuuMC8JuYz62DeayXI9M9mpLh/Oi4MYUoT3fgsdkGjiv0sEam+mqmR7Pwkb0Plp3A5Cvld4FLGNCXZSte+42QJSSizVPfOhC7iQqTDpFS5Miu+fYxAhRFUOHfl2D2YRopXxpwoxV471g3MMvcntosEQTceBrXkV/SZM7brUSHdskm7Ck+HOAuXc4KVYhtwjAzwC8UL+c0A1WYHqZQt4I2qkuBGNZBWliU7uxEM/WFcAUfHhk4s9cA9KUZFcjYkskIjULCgvIzHUsSXqMTR68H2jG93UvREqk5Deqo7yo++wOVC+5jVh5rltOurDJn3VI0NcifgTgSvue1gevJV9R2+HTr7QVsecWxZ7Sk/ij2gZugfAWLSUjXc9RYU360ouoLChww03FEeByUhHxGk8y208/GlF6rqRduBQafgkVEFI2PoqkX1meKNBSFrdBVg==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(30864003)(6916009)(5660300002)(2876002)(1076003)(36756003)(36860700001)(107886003)(83380400001)(426003)(2906002)(2616005)(26005)(356005)(7636003)(55016002)(47076005)(6286002)(86362001)(336012)(508600001)(8936002)(4326008)(70586007)(186003)(316002)(8676002)(7696005)(16526019)(70206006)(82310400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Nov 2021 10:47:08.7353 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0c5cf90a-0028-4ef8-20b6-08d9a2a51cef", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT064.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4301", "Subject": "[dpdk-dev] [PATCH v5 7/9] gpudev: add communication flag", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Elena Agostini <eagostini@nvidia.com>\n\nIn heterogeneous computing system, processing is not only in the CPU.\nSome tasks can be delegated to devices working in parallel.\nWhen mixing network activity with task processing there may be the need\nto put in communication the CPU with the device in order to synchronize\noperations.\n\nThe purpose of this flag is to allow the CPU and the GPU to\nexchange ACKs. A possible use-case is described below.\n\nCPU:\n- Trigger some task on the GPU\n- Prepare some data\n- Signal to the GPU the data is ready updating the communication flag\n\nGPU:\n- Do some pre-processing\n- Wait for more data from the CPU polling on the communication flag\n- Consume the data prepared by the CPU\n\nSigned-off-by: Elena Agostini <eagostini@nvidia.com>\n---\n app/test-gpudev/main.c | 60 ++++++++++++++\n doc/guides/prog_guide/gpudev.rst | 13 +++\n doc/guides/rel_notes/release_21_11.rst | 1 +\n lib/gpudev/gpudev.c | 92 +++++++++++++++++++++\n lib/gpudev/rte_gpudev.h | 108 +++++++++++++++++++++++++\n lib/gpudev/version.map | 4 +\n 6 files changed, 278 insertions(+)", "diff": "diff --git a/app/test-gpudev/main.c b/app/test-gpudev/main.c\nindex e3aca2225a..516a01b927 100644\n--- a/app/test-gpudev/main.c\n+++ b/app/test-gpudev/main.c\n@@ -154,6 +154,61 @@ register_cpu_memory(uint16_t gpu_id)\n \treturn 0;\n }\n \n+static int\n+create_update_comm_flag(uint16_t gpu_id)\n+{\n+\tstruct rte_gpu_comm_flag devflag;\n+\tint ret = 0;\n+\tuint32_t set_val;\n+\tuint32_t get_val;\n+\n+\tprintf(\"\\n=======> TEST: Communication flag\\n\");\n+\n+\tret = rte_gpu_comm_create_flag(gpu_id, &devflag, RTE_GPU_COMM_FLAG_CPU);\n+\tif (ret < 0) {\n+\t\tfprintf(stderr, \"rte_gpu_comm_create_flag returned error %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\tset_val = 25;\n+\tret = rte_gpu_comm_set_flag(&devflag, set_val);\n+\tif (ret < 0) {\n+\t\tfprintf(stderr, \"rte_gpu_comm_set_flag returned error %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\tret = rte_gpu_comm_get_flag_value(&devflag, &get_val);\n+\tif (ret < 0) {\n+\t\tfprintf(stderr, \"rte_gpu_comm_get_flag_value returned error %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\tprintf(\"Communication flag value at 0x%p was set to %d and current value is %d\\n\", devflag.ptr, set_val, get_val);\n+\n+\tset_val = 38;\n+\tret = rte_gpu_comm_set_flag(&devflag, set_val);\n+\tif (ret < 0) {\n+\t\tfprintf(stderr, \"rte_gpu_comm_set_flag returned error %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\tret = rte_gpu_comm_get_flag_value(&devflag, &get_val);\n+\tif (ret < 0) {\n+\t\tfprintf(stderr, \"rte_gpu_comm_get_flag_value returned error %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\tprintf(\"Communication flag value at 0x%p was set to %d and current value is %d\\n\", devflag.ptr, set_val, get_val);\n+\n+\tret = rte_gpu_comm_destroy_flag(&devflag);\n+\tif (ret < 0) {\n+\t\tfprintf(stderr, \"rte_gpu_comm_destroy_flags returned error %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n int\n main(int argc, char **argv)\n {\n@@ -204,6 +259,11 @@ main(int argc, char **argv)\n \talloc_gpu_memory(gpu_id);\n \tregister_cpu_memory(gpu_id);\n \n+\t/**\n+\t * Communication items test\n+\t */\n+\tcreate_update_comm_flag(gpu_id);\n+\n \t/* clean up the EAL */\n \trte_eal_cleanup();\n \tprintf(\"Bye...\\n\");\ndiff --git a/doc/guides/prog_guide/gpudev.rst b/doc/guides/prog_guide/gpudev.rst\nindex eb5f0af817..e0db627aed 100644\n--- a/doc/guides/prog_guide/gpudev.rst\n+++ b/doc/guides/prog_guide/gpudev.rst\n@@ -32,6 +32,10 @@ This library provides a number of features:\n - Interoperability with device-specific library through generic handlers.\n - Allocate and free memory on the device.\n - Register CPU memory to make it visible from the device.\n+- Communication between the CPU and the device.\n+\n+The whole CPU - GPU communication is implemented\n+using CPU memory visible from the GPU.\n \n \n API Overview\n@@ -73,3 +77,12 @@ Some GPU drivers may need, under certain conditions,\n to enforce the coherency of external devices writes (e.g. NIC receiving packets)\n into the GPU memory.\n gpudev abstracts and exposes this capability.\n+\n+Communication Flag\n+~~~~~~~~~~~~~~~~~~\n+\n+Considering an application with some GPU task\n+that's waiting to receive a signal from the CPU\n+to move forward with the execution.\n+The communication flag allocates a CPU memory GPU-visible ``uint32_t`` flag\n+that can be used by the CPU to communicate with a GPU task.\ndiff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst\nindex a4d07bda9b..78b29d9a25 100644\n--- a/doc/guides/rel_notes/release_21_11.rst\n+++ b/doc/guides/rel_notes/release_21_11.rst\n@@ -105,6 +105,7 @@ New Features\n \n * Device information\n * Memory management\n+ * Communication flag\n \n * **Added new RSS offload types for IPv4/L4 checksum in RSS flow.**\n \ndiff --git a/lib/gpudev/gpudev.c b/lib/gpudev/gpudev.c\nindex 49526b335f..f887f3dd93 100644\n--- a/lib/gpudev/gpudev.c\n+++ b/lib/gpudev/gpudev.c\n@@ -643,3 +643,95 @@ rte_gpu_mbw(int16_t dev_id)\n \t}\n \treturn GPU_DRV_RET(dev->ops.mbw(dev));\n }\n+\n+int\n+rte_gpu_comm_create_flag(uint16_t dev_id, struct rte_gpu_comm_flag *devflag,\n+\t\tenum rte_gpu_comm_flag_type mtype)\n+{\n+\tsize_t flag_size;\n+\tint ret;\n+\n+\tif (devflag == NULL) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (mtype != RTE_GPU_COMM_FLAG_CPU) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tflag_size = sizeof(uint32_t);\n+\n+\tdevflag->ptr = rte_zmalloc(NULL, flag_size, 0);\n+\tif (devflag->ptr == NULL) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tret = rte_gpu_register(dev_id, flag_size, devflag->ptr);\n+\tif (ret < 0) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tdevflag->mtype = mtype;\n+\tdevflag->dev_id = dev_id;\n+\n+\treturn 0;\n+}\n+\n+int\n+rte_gpu_comm_destroy_flag(struct rte_gpu_comm_flag *devflag)\n+{\n+\tint ret;\n+\n+\tif (devflag == NULL) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tret = rte_gpu_unregister(devflag->dev_id, devflag->ptr);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -1;\n+\t}\n+\n+\trte_free(devflag->ptr);\n+\n+\treturn 0;\n+}\n+\n+int\n+rte_gpu_comm_set_flag(struct rte_gpu_comm_flag *devflag, uint32_t val)\n+{\n+\tif (devflag == NULL) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tif (devflag->mtype != RTE_GPU_COMM_FLAG_CPU) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tRTE_GPU_VOLATILE(*devflag->ptr) = val;\n+\n+\treturn 0;\n+}\n+\n+int\n+rte_gpu_comm_get_flag_value(struct rte_gpu_comm_flag *devflag, uint32_t *val)\n+{\n+\tif (devflag == NULL) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (devflag->mtype != RTE_GPU_COMM_FLAG_CPU) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\t*val = RTE_GPU_VOLATILE(*devflag->ptr);\n+\n+\treturn 0;\n+}\ndiff --git a/lib/gpudev/rte_gpudev.h b/lib/gpudev/rte_gpudev.h\nindex 650ebfd700..1466ac164b 100644\n--- a/lib/gpudev/rte_gpudev.h\n+++ b/lib/gpudev/rte_gpudev.h\n@@ -38,6 +38,9 @@ extern \"C\" {\n /** Catch-all callback data. */\n #define RTE_GPU_CALLBACK_ANY_DATA ((void *)-1)\n \n+/** Access variable as volatile. */\n+#define RTE_GPU_VOLATILE(x) (*(volatile typeof(x) *)&(x))\n+\n /** Store device info. */\n struct rte_gpu_info {\n \t/** Unique identifier name. */\n@@ -68,6 +71,22 @@ enum rte_gpu_event {\n typedef void (rte_gpu_callback_t)(int16_t dev_id,\n \t\tenum rte_gpu_event event, void *user_data);\n \n+/** Memory where communication flag is allocated. */\n+enum rte_gpu_comm_flag_type {\n+\t/** Allocate flag on CPU memory visible from device. */\n+\tRTE_GPU_COMM_FLAG_CPU = 0,\n+};\n+\n+/** Communication flag to coordinate CPU with the device. */\n+struct rte_gpu_comm_flag {\n+\t/** Device that will use the device flag. */\n+\tuint16_t dev_id;\n+\t/** Pointer to flag memory area. */\n+\tuint32_t *ptr;\n+\t/** Type of memory used to allocate the flag. */\n+\tenum rte_gpu_comm_flag_type mtype;\n+};\n+\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change without prior notice.\n@@ -405,6 +424,95 @@ int rte_gpu_unregister(int16_t dev_id, void *ptr);\n __rte_experimental\n int rte_gpu_mbw(int16_t dev_id);\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Create a communication flag that can be shared\n+ * between CPU threads and device workload to exchange some status info\n+ * (e.g. work is done, processing can start, etc..).\n+ *\n+ * @param dev_id\n+ * Reference device ID.\n+ * @param devflag\n+ * Pointer to the memory area of the devflag structure.\n+ * @param mtype\n+ * Type of memory to allocate the communication flag.\n+ *\n+ * @return\n+ * 0 on success, -rte_errno otherwise:\n+ * - ENODEV if invalid dev_id\n+ * - EINVAL if invalid inputs\n+ * - ENOTSUP if operation not supported by the driver\n+ * - ENOMEM if out of space\n+ * - EPERM if driver error\n+ */\n+__rte_experimental\n+int rte_gpu_comm_create_flag(uint16_t dev_id,\n+\t\tstruct rte_gpu_comm_flag *devflag,\n+\t\tenum rte_gpu_comm_flag_type mtype);\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Deallocate a communication flag.\n+ *\n+ * @param devflag\n+ * Pointer to the memory area of the devflag structure.\n+ *\n+ * @return\n+ * 0 on success, -rte_errno otherwise:\n+ * - ENODEV if invalid dev_id\n+ * - EINVAL if NULL devflag\n+ * - ENOTSUP if operation not supported by the driver\n+ * - EPERM if driver error\n+ */\n+__rte_experimental\n+int rte_gpu_comm_destroy_flag(struct rte_gpu_comm_flag *devflag);\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Set the value of a communication flag as the input value.\n+ * Flag memory area is treated as volatile.\n+ * The flag must have been allocated with RTE_GPU_COMM_FLAG_CPU.\n+ *\n+ * @param devflag\n+ * Pointer to the memory area of the devflag structure.\n+ * @param val\n+ * Value to set in the flag.\n+ *\n+ * @return\n+ * 0 on success, -rte_errno otherwise:\n+ * - EINVAL if invalid input params\n+ */\n+__rte_experimental\n+int rte_gpu_comm_set_flag(struct rte_gpu_comm_flag *devflag,\n+\t\tuint32_t val);\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Get the value of the communication flag.\n+ * Flag memory area is treated as volatile.\n+ * The flag must have been allocated with RTE_GPU_COMM_FLAG_CPU.\n+ *\n+ * @param devflag\n+ * Pointer to the memory area of the devflag structure.\n+ * @param val\n+ * Flag output value.\n+ *\n+ * @return\n+ * 0 on success, -rte_errno otherwise:\n+ * - EINVAL if invalid input params\n+ */\n+__rte_experimental\n+int rte_gpu_comm_get_flag_value(struct rte_gpu_comm_flag *devflag,\n+\t\tuint32_t *val);\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/gpudev/version.map b/lib/gpudev/version.map\nindex d72d470d8e..2fc039373a 100644\n--- a/lib/gpudev/version.map\n+++ b/lib/gpudev/version.map\n@@ -6,6 +6,10 @@ EXPERIMENTAL {\n \trte_gpu_callback_register;\n \trte_gpu_callback_unregister;\n \trte_gpu_close;\n+\trte_gpu_comm_create_flag;\n+\trte_gpu_comm_destroy_flag;\n+\trte_gpu_comm_get_flag_value;\n+\trte_gpu_comm_set_flag;\n \trte_gpu_count_avail;\n \trte_gpu_find_next;\n \trte_gpu_free;\n", "prefixes": [ "v5", "7/9" ] }