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GET /api/patches/103954/?format=api
{ "id": 103954, "url": "http://patches.dpdk.org/api/patches/103954/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211108090704.3585175-6-g.singh@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211108090704.3585175-6-g.singh@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211108090704.3585175-6-g.singh@nxp.com", "date": "2021-11-08T09:07:02", "name": "[v3,5/7] dma/dpaa: support DMA operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "462a2cfc6d1effbf29112fd8124a9ab0b1134c18", "submitter": { "id": 1068, "url": "http://patches.dpdk.org/api/people/1068/?format=api", "name": "Gagandeep Singh", "email": "g.singh@nxp.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211108090704.3585175-6-g.singh@nxp.com/mbox/", "series": [ { "id": 20374, "url": "http://patches.dpdk.org/api/series/20374/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20374", "date": "2021-11-08T09:06:57", "name": "Introduce DPAA DMA driver", "version": 3, "mbox": "http://patches.dpdk.org/series/20374/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103954/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/103954/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": 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b=p5PoOFBvSutY5b0tdahxusKYQZ28p0stHx4lLqqFA7SlNaXGQF1pI4BwAZLFjkmn8CVh2Ogy95acqLKuyDse6ZslyDOydkbp8ngKNlJvhCRQi2WN0vaAzUXJWCRdpZkI0nLeew3mFFaned1pp14ifX9dtKOqZhCOWtUruZ+XxGk=", "Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;", "From": "Gagandeep Singh <g.singh@nxp.com>", "To": "dev@dpdk.org", "Cc": "nipun.gupta@nxp.com, thomas@monjalon.net,\n Gagandeep Singh <g.singh@nxp.com>", "Date": "Mon, 8 Nov 2021 14:37:02 +0530", "Message-Id": "<20211108090704.3585175-6-g.singh@nxp.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211108090704.3585175-1-g.singh@nxp.com>", "References": "<20211101085143.2472241-2-g.singh@nxp.com>\n <20211108090704.3585175-1-g.singh@nxp.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SG2PR02CA0077.apcprd02.prod.outlook.com\n (2603:1096:4:90::17) To VI1PR04MB6960.eurprd04.prod.outlook.com\n (2603:10a6:803:12d::10)", "MIME-Version": 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d+E+Qb7/hGYfjukhj3V3fnJ7fApP4qR6piGofXg0pqOkDkUdy0rseJvbicxT/d5jMD3VuST0Y5UpLlvo1yfQAB53E1yqrvfNu/f4FJmB6Jm3AjGxsBd8mWgv0Jxs4vJTVZ0SVfUlkam0TY2bc1KyGmUGCQQmiSFVldL+0Yi771bHNSlFbBo5V86x6DaxC+kav609KvZDUZqBiC/lO7b80Zk5/0J1M1Dto946l3qm23A0+IU+KWtkGDEnngqqFAIWj0LtowCDNb8Bp04QBJksACLn2fqq/Taw4/n+n33GZ0rJe8lFca9E3xOniXHmDJe3UG/4dN5PYVLEFt4WML6KDeNRNjNHBQXHKKKQ0wXdllQvy4fSpgOKCDgIIRRlHwntujd/At4xcVRW243NO32kMBv7H64g4GQDmcgkHJhAsvIUWXsicySo6StxEurRxqqK7lk/1tGbMrj9fkY6JUxiLJNHWn2uztQBf7H300kxBMCeeWvuZgQxEEtl2NbBhYsdnJ7WxI/gLlwML6BJndXbdUq7XqsWjpDMXr1rkz4ypPpP0cKnU24XWMPCUqCvqdUPfs4ouQ5cnd7zvxUIYY92lq5nPw16dHflxLTUL8E4X2XEALGHFm5aWQAxGZWUpIaaZtbZGr+XvJHXDgCSee5qj41qRwSU0b95IGQyFdcujYhbtI163walXhQT6LN//d92kM7da33UJRHCLHBu9j6f8oG9jkc/YAJP3HEhgSyw798n57iN008omdjQNZTPNcdvrpyFznI4UL+rPiuDeIlxtZeV4znXoq2ytvzH9IqFZce9lpx4bXImGzFIJyU9B8M9uk3vA1hNdrI1pqYJb9RAUnqskurFPiSQUZsFhvmbnNllz5q5So3c30qN/dvl4sGEbbd+luVHYIBmefitlGEdHSLabQV6/nhngVFNyDMBXZvFm+Fesg7ML5m+iVyWpoWD6QPvYBenwKJB9GxLZCh2Wx0E7LpAlpuvDBdBLDc/9Vtk999UhsDkmo3UeaGYzPP4Z+WucDr053JLy7VGBziftjMmqUpEwXKlCaeDXNyo+O7VWzRK5I8zIWGV4utft26kV3TjeAfnTWYOKAgXhYtPWmA2jd1gOKaB/WYXU3T0pUGlN/DisdvIqr2ypF3gxprPOAKZk2ftZBQfsmvIjaRx9+/dC+8KFV7euzX74Yypuj/70TLCBguaV7/gM9SWepHTHuRq6nljWGAtoCIQmTl9IXQlhDYyieLf5PBCHo0m1KJwGOc5hIUgKKdU5D0Xayvg4ebv2zQWzTX9CScLZPv3U7UuayeOsJSWSCGO7d6HjwfUD9CAD9XfBWJmudZhWaYNw253x6kcYwgUIGHzbKtrxSBk5l8sN38Ckw6t2umkYJnoqI/BGYa/cDwFdLmXCMvTY9rwN6xiWN7sIBVAJNIHms0G/wj9bfYx4xTd6bUd1R33LVgOniw2gWSxwUBcTiB6/FBqAfCAhz2iQRoBkkJcWl4nt2XXMbdd2hAm0yHxBDuG7AeCuQHBA/dFDyJJCvWVsLQ/MBJhBrxm3z4w96JH9RqKhqyLnylNMaPnngQFqOY=", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 21c57886-dadb-4901-931e-08d9a2973552", "X-MS-Exchange-CrossTenant-AuthSource": "VI1PR04MB6960.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Nov 2021 09:07:37.1396 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n TwCV5MgmL/eePXIep3WA0/yC10+0TAsMBT//n8dNT62ZB1wD5ucQ+9E6NoojcNt0", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VE1PR04MB6495", "Subject": "[dpdk-dev] [PATCH v3 5/7] dma/dpaa: support DMA operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch support copy, submit, completed and\ncompleted status functionality of DMA driver.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/dma/dpaa/dpaa_qdma.c | 334 +++++++++++++++++++++++++++++++++++\n drivers/dma/dpaa/dpaa_qdma.h | 4 +\n 2 files changed, 338 insertions(+)", "diff": "diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c\nindex e59cd36872..ebe6211f08 100644\n--- a/drivers/dma/dpaa/dpaa_qdma.c\n+++ b/drivers/dma/dpaa/dpaa_qdma.c\n@@ -15,12 +15,50 @@ qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)\n \tccdf->addr_lo = rte_cpu_to_le_32(lower_32_bits(addr));\n }\n \n+static inline u64\n+qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf)\n+{\n+\treturn ccdf->cfg8b_w1 & 0xff;\n+}\n+\n+static inline int\n+qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf)\n+{\n+\treturn (rte_le_to_cpu_32(ccdf->cfg) & QDMA_CCDF_MASK)\n+\t\t>> QDMA_CCDF_OFFSET;\n+}\n+\n+static inline void\n+qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset)\n+{\n+\tccdf->cfg = rte_cpu_to_le_32(QDMA_CCDF_FOTMAT | offset);\n+}\n+\n+static inline int\n+qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf)\n+{\n+\treturn (rte_le_to_cpu_32(ccdf->status) & QDMA_CCDF_MASK)\n+\t\t>> QDMA_CCDF_STATUS;\n+}\n+\n+static inline void\n+qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status)\n+{\n+\tccdf->status = rte_cpu_to_le_32(QDMA_CCDF_SER | status);\n+}\n+\n static inline void\n qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)\n {\n \tcsgf->cfg = rte_cpu_to_le_32(len & QDMA_SG_LEN_MASK);\n }\n \n+static inline void\n+qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len)\n+{\n+\tcsgf->cfg = rte_cpu_to_le_32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK));\n+}\n+\n static inline int\n ilog2(int x)\n {\n@@ -47,6 +85,18 @@ qdma_writel(u32 val, void *addr)\n \tQDMA_OUT(addr, val);\n }\n \n+static u32\n+qdma_readl_be(void *addr)\n+{\n+\treturn QDMA_IN_BE(addr);\n+}\n+\n+static void\n+qdma_writel_be(u32 val, void *addr)\n+{\n+\tQDMA_OUT_BE(addr, val);\n+}\n+\n static void\n *dma_pool_alloc(int size, int aligned, dma_addr_t *phy_addr)\n {\n@@ -104,6 +154,32 @@ fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan)\n \tfsl_qdma->desc_allocated--;\n }\n \n+static void\n+fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,\n+\t\t\t\t dma_addr_t dst, dma_addr_t src, u32 len)\n+{\n+\tstruct fsl_qdma_format *csgf_src, *csgf_dest;\n+\n+\t/* Note: command table (fsl_comp->virt_addr) is getting filled\n+\t * directly in cmd descriptors of queues while enqueuing the descriptor\n+\t * please refer fsl_qdma_enqueue_desc\n+\t * frame list table (virt_addr) + 1) and source,\n+\t * destination descriptor table\n+\t * (fsl_comp->desc_virt_addr and fsl_comp->desc_virt_addr+1) move to\n+\t * the control path to fsl_qdma_pre_request_enqueue_comp_sd_desc\n+\t */\n+\tcsgf_src = (struct fsl_qdma_format *)fsl_comp->virt_addr + 2;\n+\tcsgf_dest = (struct fsl_qdma_format *)fsl_comp->virt_addr + 3;\n+\n+\t/* Status notification is enqueued to status queue. */\n+\tqdma_desc_addr_set64(csgf_src, src);\n+\tqdma_csgf_set_len(csgf_src, len);\n+\tqdma_desc_addr_set64(csgf_dest, dst);\n+\tqdma_csgf_set_len(csgf_dest, len);\n+\t/* This entry is the last entry. */\n+\tqdma_csgf_set_f(csgf_dest, len);\n+}\n+\n /*\n * Pre-request command descriptor and compound S/G for enqueue.\n */\n@@ -175,6 +251,26 @@ fsl_qdma_pre_request_enqueue_comp_sd_desc(\n \treturn -ENOMEM;\n }\n \n+/*\n+ * Request a command descriptor for enqueue.\n+ */\n+static struct fsl_qdma_comp *\n+fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan)\n+{\n+\tstruct fsl_qdma_queue *queue = fsl_chan->queue;\n+\tstruct fsl_qdma_comp *comp_temp;\n+\n+\tif (!list_empty(&queue->comp_free)) {\n+\t\tcomp_temp = list_first_entry(&queue->comp_free,\n+\t\t\t\t\t struct fsl_qdma_comp,\n+\t\t\t\t\t list);\n+\t\tlist_del(&comp_temp->list);\n+\t\treturn comp_temp;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n static struct fsl_qdma_queue\n *fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma)\n {\n@@ -324,6 +420,54 @@ fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)\n \treturn 0;\n }\n \n+static int\n+fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,\n+\t\t\t\t void *block, int id, const uint16_t nb_cpls,\n+\t\t\t\t uint16_t *last_idx,\n+\t\t\t\t enum rte_dma_status_code *status)\n+{\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;\n+\tstruct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];\n+\tstruct fsl_qdma_queue *temp_queue;\n+\tstruct fsl_qdma_format *status_addr;\n+\tstruct fsl_qdma_comp *fsl_comp = NULL;\n+\tu32 reg, i;\n+\tint count = 0;\n+\n+\twhile (count < nb_cpls) {\n+\t\treg = qdma_readl_be(block + FSL_QDMA_BSQSR);\n+\t\tif (reg & FSL_QDMA_BSQSR_QE_BE)\n+\t\t\treturn count;\n+\n+\t\tstatus_addr = fsl_status->virt_head;\n+\n+\t\ti = qdma_ccdf_get_queue(status_addr) +\n+\t\t\tid * fsl_qdma->n_queues;\n+\t\ttemp_queue = fsl_queue + i;\n+\t\tfsl_comp = list_first_entry(&temp_queue->comp_used,\n+\t\t\t\t\t struct fsl_qdma_comp,\n+\t\t\t\t\t list);\n+\t\tlist_del(&fsl_comp->list);\n+\n+\t\treg = qdma_readl_be(block + FSL_QDMA_BSQMR);\n+\t\treg |= FSL_QDMA_BSQMR_DI_BE;\n+\n+\t\tqdma_desc_addr_set64(status_addr, 0x0);\n+\t\tfsl_status->virt_head++;\n+\t\tif (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)\n+\t\t\tfsl_status->virt_head = fsl_status->cq;\n+\t\tqdma_writel_be(reg, block + FSL_QDMA_BSQMR);\n+\t\t*last_idx = fsl_comp->index;\n+\t\tif (status != NULL)\n+\t\t\tstatus[count] = RTE_DMA_STATUS_SUCCESSFUL;\n+\n+\t\tlist_add_tail(&fsl_comp->list, &temp_queue->comp_free);\n+\t\tcount++;\n+\n+\t}\n+\treturn count;\n+}\n+\n static int\n fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)\n {\n@@ -419,6 +563,66 @@ fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)\n \treturn 0;\n }\n \n+static void *\n+fsl_qdma_prep_memcpy(void *fsl_chan, dma_addr_t dst,\n+\t\t\t dma_addr_t src, size_t len,\n+\t\t\t void *call_back,\n+\t\t\t void *param)\n+{\n+\tstruct fsl_qdma_comp *fsl_comp;\n+\n+\tfsl_comp =\n+\tfsl_qdma_request_enqueue_desc((struct fsl_qdma_chan *)fsl_chan);\n+\tif (!fsl_comp)\n+\t\treturn NULL;\n+\n+\tfsl_comp->qchan = fsl_chan;\n+\tfsl_comp->call_back_func = call_back;\n+\tfsl_comp->params = param;\n+\n+\tfsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len);\n+\treturn (void *)fsl_comp;\n+}\n+\n+static int\n+fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan,\n+\t\t\t\t struct fsl_qdma_comp *fsl_comp,\n+\t\t\t\t uint64_t flags)\n+{\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_chan->queue;\n+\tvoid *block = fsl_queue->block_base;\n+\tstruct fsl_qdma_format *ccdf;\n+\tu32 reg;\n+\n+\t/* retrieve and store the register value in big endian\n+\t * to avoid bits swap\n+\t */\n+\treg = qdma_readl_be(block +\n+\t\t\t FSL_QDMA_BCQSR(fsl_queue->id));\n+\tif (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE))\n+\t\treturn -1;\n+\n+\t/* filling descriptor command table */\n+\tccdf = (struct fsl_qdma_format *)fsl_queue->virt_head;\n+\tqdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);\n+\tqdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(fsl_comp->virt_addr));\n+\tqdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(fsl_comp->virt_addr));\n+\tfsl_comp->index = fsl_queue->virt_head - fsl_queue->cq;\n+\tfsl_queue->virt_head++;\n+\n+\tif (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)\n+\t\tfsl_queue->virt_head = fsl_queue->cq;\n+\n+\tlist_add_tail(&fsl_comp->list, &fsl_queue->comp_used);\n+\n+\tif (flags == RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\treg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id));\n+\t\treg |= FSL_QDMA_BCQMR_EI_BE;\n+\t\tqdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id));\n+\t}\n+\treturn fsl_comp->index;\n+}\n+\n static int\n fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan)\n {\n@@ -535,6 +739,132 @@ dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev,\n \treturn dpaa_get_channel(fsl_qdma, vchan);\n }\n \n+static int\n+dpaa_qdma_submit(void *dev_private, uint16_t vchan)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;\n+\tstruct fsl_qdma_chan *fsl_chan =\n+\t\t&fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_chan->queue;\n+\tvoid *block = fsl_queue->block_base;\n+\tu32 reg;\n+\n+\twhile (fsl_queue->pending) {\n+\t\treg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id));\n+\t\treg |= FSL_QDMA_BCQMR_EI_BE;\n+\t\tqdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id));\n+\t\tfsl_queue->pending--;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+dpaa_qdma_enqueue(void *dev_private, uint16_t vchan,\n+\t\t rte_iova_t src, rte_iova_t dst,\n+\t\t uint32_t length, uint64_t flags)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;\n+\tstruct fsl_qdma_chan *fsl_chan =\n+\t\t&fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];\n+\tint ret;\n+\n+\tvoid *fsl_comp = NULL;\n+\n+\tfsl_comp = fsl_qdma_prep_memcpy(fsl_chan,\n+\t\t\t(dma_addr_t)dst, (dma_addr_t)src,\n+\t\t\tlength, NULL, NULL);\n+\tif (!fsl_comp) {\n+\t\tDPAA_QDMA_DP_DEBUG(\"fsl_comp is NULL\\n\");\n+\t\treturn -1;\n+\t}\n+\tret = fsl_qdma_enqueue_desc(fsl_chan, fsl_comp, flags);\n+\n+\treturn ret;\n+}\n+\n+static uint16_t\n+dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan,\n+\t\t\t const uint16_t nb_cpls, uint16_t *last_idx,\n+\t\t\t enum rte_dma_status_code *st)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;\n+\tint id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES);\n+\tvoid *block;\n+\tint intr;\n+\tvoid *status = fsl_qdma->status_base;\n+\n+\tintr = qdma_readl_be(status + FSL_QDMA_DEDR);\n+\tif (intr) {\n+\t\tDPAA_QDMA_ERR(\"DMA transaction error! %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW0R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW0R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW1R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW1R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW2R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW2R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW3R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW3R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFQIDR);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFQIDR %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECBR);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECBR %x\\n\", intr);\n+\t\tqdma_writel(0xffffffff,\n+\t\t\t status + FSL_QDMA_DEDR);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DEDR);\n+\t}\n+\n+\tblock = fsl_qdma->block_base +\n+\t\tFSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);\n+\n+\tintr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls,\n+\t\t\t\t\t\tlast_idx, st);\n+\n+\treturn intr;\n+}\n+\n+\n+static uint16_t\n+dpaa_qdma_dequeue(void *dev_private,\n+\t\t uint16_t vchan, const uint16_t nb_cpls,\n+\t\t uint16_t *last_idx, bool *has_error)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;\n+\tint id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES);\n+\tvoid *block;\n+\tint intr;\n+\tvoid *status = fsl_qdma->status_base;\n+\n+\tintr = qdma_readl_be(status + FSL_QDMA_DEDR);\n+\tif (intr) {\n+\t\tDPAA_QDMA_ERR(\"DMA transaction error! %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW0R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW0R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW1R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW1R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW2R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW2R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW3R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW3R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFQIDR);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFQIDR %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECBR);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECBR %x\\n\", intr);\n+\t\tqdma_writel(0xffffffff,\n+\t\t\t status + FSL_QDMA_DEDR);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DEDR);\n+\t\t*has_error = true;\n+\t}\n+\n+\tblock = fsl_qdma->block_base +\n+\t\tFSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);\n+\n+\tintr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls,\n+\t\t\t\t\t\tlast_idx, NULL);\n+\n+\treturn intr;\n+}\n+\n static struct rte_dma_dev_ops dpaa_qdma_ops = {\n \t.dev_info_get\t\t = dpaa_info_get,\n \t.dev_configure = dpaa_qdma_configure,\n@@ -652,6 +982,10 @@ dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv,\n \tdmadev->dev_ops = &dpaa_qdma_ops;\n \tdmadev->device = &dpaa_dev->device;\n \tdmadev->fp_obj->dev_private = dmadev->data->dev_private;\n+\tdmadev->fp_obj->copy = dpaa_qdma_enqueue;\n+\tdmadev->fp_obj->submit = dpaa_qdma_submit;\n+\tdmadev->fp_obj->completed = dpaa_qdma_dequeue;\n+\tdmadev->fp_obj->completed_status = dpaa_qdma_dequeue_status;\n \n \t/* Invoke PMD device initialization function */\n \tret = dpaa_qdma_init(dmadev);\ndiff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h\nindex f046167108..6d0ac58317 100644\n--- a/drivers/dma/dpaa/dpaa_qdma.h\n+++ b/drivers/dma/dpaa/dpaa_qdma.h\n@@ -7,6 +7,10 @@\n \n #include <rte_io.h>\n \n+#ifndef BIT\n+#define BIT(nr)\t\t(1UL << (nr))\n+#endif\n+\n #define CORE_NUMBER 4\n #define RETRIES\t5\n \n", "prefixes": [ "v3", "5/7" ] }