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{
    "id": 103951,
    "url": "http://patches.dpdk.org/api/patches/103951/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211108090704.3585175-3-g.singh@nxp.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
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        "commit_url_format": ""
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    "msgid": "<20211108090704.3585175-3-g.singh@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211108090704.3585175-3-g.singh@nxp.com",
    "date": "2021-11-08T09:06:59",
    "name": "[v3,2/7] dma/dpaa: add device probe and remove functionality",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "625816c92917923b69eb2f5b97ddb00f8f29b9bc",
    "submitter": {
        "id": 1068,
        "url": "http://patches.dpdk.org/api/people/1068/?format=api",
        "name": "Gagandeep Singh",
        "email": "g.singh@nxp.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211108090704.3585175-3-g.singh@nxp.com/mbox/",
    "series": [
        {
            "id": 20374,
            "url": "http://patches.dpdk.org/api/series/20374/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20374",
            "date": "2021-11-08T09:06:57",
            "name": "Introduce DPAA DMA driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/20374/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/103951/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/103951/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Gagandeep Singh <g.singh@nxp.com>",
        "To": "dev@dpdk.org",
        "Cc": "nipun.gupta@nxp.com, thomas@monjalon.net,\n Gagandeep Singh <g.singh@nxp.com>",
        "Date": "Mon,  8 Nov 2021 14:36:59 +0530",
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        "References": "<20211101085143.2472241-2-g.singh@nxp.com>\n <20211108090704.3585175-1-g.singh@nxp.com>",
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        "Subject": "[dpdk-dev] [PATCH v3 2/7] dma/dpaa: add device probe and remove\n functionality",
        "X-BeenThere": "dev@dpdk.org",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch add device initialisation functionality.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/dma/dpaa/dpaa_qdma.c | 456 ++++++++++++++++++++++++++++++++++-\n drivers/dma/dpaa/dpaa_qdma.h | 236 ++++++++++++++++++\n 2 files changed, 690 insertions(+), 2 deletions(-)\n create mode 100644 drivers/dma/dpaa/dpaa_qdma.h",
    "diff": "diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c\nindex 2ef3ee0c35..f958f78af5 100644\n--- a/drivers/dma/dpaa/dpaa_qdma.c\n+++ b/drivers/dma/dpaa/dpaa_qdma.c\n@@ -3,17 +3,469 @@\n  */\n \n #include <rte_dpaa_bus.h>\n+#include <rte_dmadev_pmd.h>\n+\n+#include \"dpaa_qdma.h\"\n+\n+static inline int\n+ilog2(int x)\n+{\n+\tint log = 0;\n+\n+\tx >>= 1;\n+\n+\twhile (x) {\n+\t\tlog++;\n+\t\tx >>= 1;\n+\t}\n+\treturn log;\n+}\n+\n+static u32\n+qdma_readl(void *addr)\n+{\n+\treturn QDMA_IN(addr);\n+}\n+\n+static void\n+qdma_writel(u32 val, void *addr)\n+{\n+\tQDMA_OUT(addr, val);\n+}\n+\n+static void\n+*dma_pool_alloc(int size, int aligned, dma_addr_t *phy_addr)\n+{\n+\tvoid *virt_addr;\n+\n+\tvirt_addr = rte_malloc(\"dma pool alloc\", size, aligned);\n+\tif (!virt_addr)\n+\t\treturn NULL;\n+\n+\t*phy_addr = rte_mem_virt2iova(virt_addr);\n+\n+\treturn virt_addr;\n+}\n+\n+static void\n+dma_pool_free(void *addr)\n+{\n+\trte_free(addr);\n+}\n+\n+static void\n+fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan)\n+{\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_chan->queue;\n+\tstruct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;\n+\tstruct fsl_qdma_comp *comp_temp, *_comp_temp;\n+\tint id;\n+\n+\tif (--fsl_queue->count)\n+\t\tgoto finally;\n+\n+\tid = (fsl_qdma->block_base - fsl_queue->block_base) /\n+\t      fsl_qdma->block_offset;\n+\n+\twhile (rte_atomic32_read(&wait_task[id]) == 1)\n+\t\trte_delay_us(QDMA_DELAY);\n+\n+\tlist_for_each_entry_safe(comp_temp, _comp_temp,\n+\t\t\t\t &fsl_queue->comp_used,\tlist) {\n+\t\tlist_del(&comp_temp->list);\n+\t\tdma_pool_free(comp_temp->virt_addr);\n+\t\tdma_pool_free(comp_temp->desc_virt_addr);\n+\t\trte_free(comp_temp);\n+\t}\n+\n+\tlist_for_each_entry_safe(comp_temp, _comp_temp,\n+\t\t\t\t &fsl_queue->comp_free, list) {\n+\t\tlist_del(&comp_temp->list);\n+\t\tdma_pool_free(comp_temp->virt_addr);\n+\t\tdma_pool_free(comp_temp->desc_virt_addr);\n+\t\trte_free(comp_temp);\n+\t}\n+\n+finally:\n+\tfsl_qdma->desc_allocated--;\n+}\n+\n+static struct fsl_qdma_queue\n+*fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma)\n+{\n+\tstruct fsl_qdma_queue *queue_head, *queue_temp;\n+\tint len, i, j;\n+\tint queue_num;\n+\tint blocks;\n+\tunsigned int queue_size[FSL_QDMA_QUEUE_MAX];\n+\n+\tqueue_num = fsl_qdma->n_queues;\n+\tblocks = fsl_qdma->num_blocks;\n+\n+\tlen = sizeof(*queue_head) * queue_num * blocks;\n+\tqueue_head = rte_zmalloc(\"qdma: queue head\", len, 0);\n+\tif (!queue_head)\n+\t\treturn NULL;\n+\n+\tfor (i = 0; i < FSL_QDMA_QUEUE_MAX; i++)\n+\t\tqueue_size[i] = QDMA_QUEUE_SIZE;\n+\n+\tfor (j = 0; j < blocks; j++) {\n+\t\tfor (i = 0; i < queue_num; i++) {\n+\t\t\tif (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||\n+\t\t\t    queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\tqueue_temp = queue_head + i + (j * queue_num);\n+\n+\t\t\tqueue_temp->cq =\n+\t\t\tdma_pool_alloc(sizeof(struct fsl_qdma_format) *\n+\t\t\t\t       queue_size[i],\n+\t\t\t\t       sizeof(struct fsl_qdma_format) *\n+\t\t\t\t       queue_size[i], &queue_temp->bus_addr);\n+\n+\t\t\tif (!queue_temp->cq)\n+\t\t\t\tgoto fail;\n+\n+\t\t\tmemset(queue_temp->cq, 0x0, queue_size[i] *\n+\t\t\t       sizeof(struct fsl_qdma_format));\n+\n+\t\t\tqueue_temp->block_base = fsl_qdma->block_base +\n+\t\t\t\tFSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);\n+\t\t\tqueue_temp->n_cq = queue_size[i];\n+\t\t\tqueue_temp->id = i;\n+\t\t\tqueue_temp->count = 0;\n+\t\t\tqueue_temp->pending = 0;\n+\t\t\tqueue_temp->virt_head = queue_temp->cq;\n+\n+\t\t}\n+\t}\n+\treturn queue_head;\n+\n+fail:\n+\tfor (j = 0; j < blocks; j++) {\n+\t\tfor (i = 0; i < queue_num; i++) {\n+\t\t\tqueue_temp = queue_head + i + (j * queue_num);\n+\t\t\tdma_pool_free(queue_temp->cq);\n+\t\t}\n+\t}\n+\trte_free(queue_head);\n+\n+\treturn NULL;\n+}\n+\n+static struct\n+fsl_qdma_queue *fsl_qdma_prep_status_queue(void)\n+{\n+\tstruct fsl_qdma_queue *status_head;\n+\tunsigned int status_size;\n+\n+\tstatus_size = QDMA_STATUS_SIZE;\n+\tif (status_size > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||\n+\t    status_size < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {\n+\t\treturn NULL;\n+\t}\n+\n+\tstatus_head = rte_zmalloc(\"qdma: status head\", sizeof(*status_head), 0);\n+\tif (!status_head)\n+\t\treturn NULL;\n+\n+\t/*\n+\t * Buffer for queue command\n+\t */\n+\tstatus_head->cq = dma_pool_alloc(sizeof(struct fsl_qdma_format) *\n+\t\t\t\t\t status_size,\n+\t\t\t\t\t sizeof(struct fsl_qdma_format) *\n+\t\t\t\t\t status_size,\n+\t\t\t\t\t &status_head->bus_addr);\n+\n+\tif (!status_head->cq) {\n+\t\trte_free(status_head);\n+\t\treturn NULL;\n+\t}\n+\n+\tmemset(status_head->cq, 0x0, status_size *\n+\t       sizeof(struct fsl_qdma_format));\n+\tstatus_head->n_cq = status_size;\n+\tstatus_head->virt_head = status_head->cq;\n+\n+\treturn status_head;\n+}\n+\n+static int\n+fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)\n+{\n+\tvoid *ctrl = fsl_qdma->ctrl_base;\n+\tvoid *block;\n+\tint i, count = RETRIES;\n+\tunsigned int j;\n+\tu32 reg;\n+\n+\t/* Disable the command queue and wait for idle state. */\n+\treg = qdma_readl(ctrl + FSL_QDMA_DMR);\n+\treg |= FSL_QDMA_DMR_DQD;\n+\tqdma_writel(reg, ctrl + FSL_QDMA_DMR);\n+\tfor (j = 0; j < fsl_qdma->num_blocks; j++) {\n+\t\tblock = fsl_qdma->block_base +\n+\t\t\tFSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);\n+\t\tfor (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)\n+\t\t\tqdma_writel(0, block + FSL_QDMA_BCQMR(i));\n+\t}\n+\twhile (true) {\n+\t\treg = qdma_readl(ctrl + FSL_QDMA_DSR);\n+\t\tif (!(reg & FSL_QDMA_DSR_DB))\n+\t\t\tbreak;\n+\t\tif (count-- < 0)\n+\t\t\treturn -EBUSY;\n+\t\trte_delay_us(100);\n+\t}\n+\n+\tfor (j = 0; j < fsl_qdma->num_blocks; j++) {\n+\t\tblock = fsl_qdma->block_base +\n+\t\t\tFSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);\n+\n+\t\t/* Disable status queue. */\n+\t\tqdma_writel(0, block + FSL_QDMA_BSQMR);\n+\n+\t\t/*\n+\t\t * clear the command queue interrupt detect register for\n+\t\t * all queues.\n+\t\t */\n+\t\tqdma_writel(0xffffffff, block + FSL_QDMA_BCQIDR(0));\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)\n+{\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;\n+\tstruct fsl_qdma_queue *temp;\n+\tvoid *ctrl = fsl_qdma->ctrl_base;\n+\tvoid *block;\n+\tu32 i, j;\n+\tu32 reg;\n+\tint ret, val;\n+\n+\t/* Try to halt the qDMA engine first. */\n+\tret = fsl_qdma_halt(fsl_qdma);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (j = 0; j < fsl_qdma->num_blocks; j++) {\n+\t\tblock = fsl_qdma->block_base +\n+\t\t\tFSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);\n+\t\tfor (i = 0; i < fsl_qdma->n_queues; i++) {\n+\t\t\ttemp = fsl_queue + i + (j * fsl_qdma->n_queues);\n+\t\t\t/*\n+\t\t\t * Initialize Command Queue registers to\n+\t\t\t * point to the first\n+\t\t\t * command descriptor in memory.\n+\t\t\t * Dequeue Pointer Address Registers\n+\t\t\t * Enqueue Pointer Address Registers\n+\t\t\t */\n+\n+\t\t\tqdma_writel(lower_32_bits(temp->bus_addr),\n+\t\t\t\t    block + FSL_QDMA_BCQDPA_SADDR(i));\n+\t\t\tqdma_writel(upper_32_bits(temp->bus_addr),\n+\t\t\t\t    block + FSL_QDMA_BCQEDPA_SADDR(i));\n+\t\t\tqdma_writel(lower_32_bits(temp->bus_addr),\n+\t\t\t\t    block + FSL_QDMA_BCQEPA_SADDR(i));\n+\t\t\tqdma_writel(upper_32_bits(temp->bus_addr),\n+\t\t\t\t    block + FSL_QDMA_BCQEEPA_SADDR(i));\n+\n+\t\t\t/* Initialize the queue mode. */\n+\t\t\treg = FSL_QDMA_BCQMR_EN;\n+\t\t\treg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq) - 4);\n+\t\t\treg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq) - 6);\n+\t\t\tqdma_writel(reg, block + FSL_QDMA_BCQMR(i));\n+\t\t}\n+\n+\t\t/*\n+\t\t * Workaround for erratum: ERR010812.\n+\t\t * We must enable XOFF to avoid the enqueue rejection occurs.\n+\t\t * Setting SQCCMR ENTER_WM to 0x20.\n+\t\t */\n+\n+\t\tqdma_writel(FSL_QDMA_SQCCMR_ENTER_WM,\n+\t\t\t    block + FSL_QDMA_SQCCMR);\n+\n+\t\t/*\n+\t\t * Initialize status queue registers to point to the first\n+\t\t * command descriptor in memory.\n+\t\t * Dequeue Pointer Address Registers\n+\t\t * Enqueue Pointer Address Registers\n+\t\t */\n+\n+\t\tqdma_writel(\n+\t\t\t    upper_32_bits(fsl_qdma->status[j]->bus_addr),\n+\t\t\t    block + FSL_QDMA_SQEEPAR);\n+\t\tqdma_writel(\n+\t\t\t    lower_32_bits(fsl_qdma->status[j]->bus_addr),\n+\t\t\t    block + FSL_QDMA_SQEPAR);\n+\t\tqdma_writel(\n+\t\t\t    upper_32_bits(fsl_qdma->status[j]->bus_addr),\n+\t\t\t    block + FSL_QDMA_SQEDPAR);\n+\t\tqdma_writel(\n+\t\t\t    lower_32_bits(fsl_qdma->status[j]->bus_addr),\n+\t\t\t    block + FSL_QDMA_SQDPAR);\n+\t\t/* Desiable status queue interrupt. */\n+\n+\t\tqdma_writel(0x0, block + FSL_QDMA_BCQIER(0));\n+\t\tqdma_writel(0x0, block + FSL_QDMA_BSQICR);\n+\t\tqdma_writel(0x0, block + FSL_QDMA_CQIER);\n+\n+\t\t/* Initialize the status queue mode. */\n+\t\treg = FSL_QDMA_BSQMR_EN;\n+\t\tval = ilog2(fsl_qdma->status[j]->n_cq) - 6;\n+\t\treg |= FSL_QDMA_BSQMR_CQ_SIZE(val);\n+\t\tqdma_writel(reg, block + FSL_QDMA_BSQMR);\n+\t}\n+\n+\treg = qdma_readl(ctrl + FSL_QDMA_DMR);\n+\treg &= ~FSL_QDMA_DMR_DQD;\n+\tqdma_writel(reg, ctrl + FSL_QDMA_DMR);\n+\n+\treturn 0;\n+}\n+\n+static void\n+dma_release(void *fsl_chan)\n+{\n+\t((struct fsl_qdma_chan *)fsl_chan)->free = true;\n+\tfsl_qdma_free_chan_resources((struct fsl_qdma_chan *)fsl_chan);\n+}\n+\n+static int\n+dpaa_qdma_init(struct rte_dma_dev *dmadev)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private;\n+\tstruct fsl_qdma_chan *fsl_chan;\n+\tuint64_t phys_addr;\n+\tunsigned int len;\n+\tint ccsr_qdma_fd;\n+\tint regs_size;\n+\tint ret;\n+\tu32 i;\n+\n+\tfsl_qdma->desc_allocated = 0;\n+\tfsl_qdma->n_chans = VIRT_CHANNELS;\n+\tfsl_qdma->n_queues = QDMA_QUEUES;\n+\tfsl_qdma->num_blocks = QDMA_BLOCKS;\n+\tfsl_qdma->block_offset = QDMA_BLOCK_OFFSET;\n+\n+\tlen = sizeof(*fsl_chan) * fsl_qdma->n_chans;\n+\tfsl_qdma->chans = rte_zmalloc(\"qdma: fsl chans\", len, 0);\n+\tif (!fsl_qdma->chans)\n+\t\treturn -1;\n+\n+\tlen = sizeof(struct fsl_qdma_queue *) * fsl_qdma->num_blocks;\n+\tfsl_qdma->status = rte_zmalloc(\"qdma: fsl status\", len, 0);\n+\tif (!fsl_qdma->status) {\n+\t\trte_free(fsl_qdma->chans);\n+\t\treturn -1;\n+\t}\n+\n+\tfor (i = 0; i < fsl_qdma->num_blocks; i++) {\n+\t\trte_atomic32_init(&wait_task[i]);\n+\t\tfsl_qdma->status[i] = fsl_qdma_prep_status_queue();\n+\t\tif (!fsl_qdma->status[i])\n+\t\t\tgoto err;\n+\t}\n+\n+\tccsr_qdma_fd = open(\"/dev/mem\", O_RDWR);\n+\tif (unlikely(ccsr_qdma_fd < 0))\n+\t\tgoto err;\n+\n+\tregs_size = fsl_qdma->block_offset * (fsl_qdma->num_blocks + 2);\n+\tphys_addr = QDMA_CCSR_BASE;\n+\tfsl_qdma->ctrl_base = mmap(NULL, regs_size, PROT_READ |\n+\t\t\t\t\t PROT_WRITE, MAP_SHARED,\n+\t\t\t\t\t ccsr_qdma_fd, phys_addr);\n+\n+\tclose(ccsr_qdma_fd);\n+\tif (fsl_qdma->ctrl_base == MAP_FAILED)\n+\t\tgoto err;\n+\n+\tfsl_qdma->status_base = fsl_qdma->ctrl_base + QDMA_BLOCK_OFFSET;\n+\tfsl_qdma->block_base = fsl_qdma->status_base + QDMA_BLOCK_OFFSET;\n+\n+\tfsl_qdma->queue = fsl_qdma_alloc_queue_resources(fsl_qdma);\n+\tif (!fsl_qdma->queue) {\n+\t\tmunmap(fsl_qdma->ctrl_base, regs_size);\n+\t\tgoto err;\n+\t}\n+\n+\tfor (i = 0; i < fsl_qdma->n_chans; i++) {\n+\t\tstruct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];\n+\n+\t\tfsl_chan->qdma = fsl_qdma;\n+\t\tfsl_chan->queue = fsl_qdma->queue + i % (fsl_qdma->n_queues *\n+\t\t\t\t\t\t\tfsl_qdma->num_blocks);\n+\t\tfsl_chan->free = true;\n+\t}\n+\n+\tret = fsl_qdma_reg_init(fsl_qdma);\n+\tif (ret) {\n+\t\tmunmap(fsl_qdma->ctrl_base, regs_size);\n+\t\tgoto err;\n+\t}\n+\n+\treturn 0;\n+\n+err:\n+\trte_free(fsl_qdma->chans);\n+\trte_free(fsl_qdma->status);\n+\n+\treturn -1;\n+}\n \n static int\n dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv,\n-\t\t__rte_unused struct rte_dpaa_device *dpaa_dev)\n+\t\tstruct rte_dpaa_device *dpaa_dev)\n {\n+\tstruct rte_dma_dev *dmadev;\n+\tint ret;\n+\n+\tdmadev = rte_dma_pmd_allocate(dpaa_dev->device.name,\n+\t\t\t\t      rte_socket_id(),\n+\t\t\t\t      sizeof(struct fsl_qdma_engine));\n+\tif (!dmadev)\n+\t\treturn -EINVAL;\n+\n+\tdpaa_dev->dmadev = dmadev;\n+\n+\t/* Invoke PMD device initialization function */\n+\tret = dpaa_qdma_init(dmadev);\n+\tif (ret) {\n+\t\t(void)rte_dma_pmd_release(dpaa_dev->device.name);\n+\t\treturn ret;\n+\t}\n+\n+\tdmadev->state = RTE_DMA_DEV_READY;\n \treturn 0;\n }\n \n static int\n-dpaa_qdma_remove(__rte_unused struct rte_dpaa_device *dpaa_dev)\n+dpaa_qdma_remove(struct rte_dpaa_device *dpaa_dev)\n {\n+\tstruct rte_dma_dev *dmadev = dpaa_dev->dmadev;\n+\tstruct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private;\n+\tint i = 0, max = QDMA_QUEUES * QDMA_BLOCKS;\n+\n+\tfor (i = 0; i < max; i++) {\n+\t\tstruct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];\n+\n+\t\tif (fsl_chan->free == false)\n+\t\t\tdma_release(fsl_chan);\n+\t}\n+\n+\trte_free(fsl_qdma->status);\n+\trte_free(fsl_qdma->chans);\n+\n+\t(void)rte_dma_pmd_release(dpaa_dev->device.name);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h\nnew file mode 100644\nindex 0000000000..c05620b740\n--- /dev/null\n+++ b/drivers/dma/dpaa/dpaa_qdma.h\n@@ -0,0 +1,236 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021 NXP\n+ */\n+\n+#ifndef _DPAA_QDMA_H_\n+#define _DPAA_QDMA_H_\n+\n+#include <rte_io.h>\n+\n+#define CORE_NUMBER 4\n+#define RETRIES\t5\n+\n+#define FSL_QDMA_DMR\t\t\t0x0\n+#define FSL_QDMA_DSR\t\t\t0x4\n+#define FSL_QDMA_DEIER\t\t\t0xe00\n+#define FSL_QDMA_DEDR\t\t\t0xe04\n+#define FSL_QDMA_DECFDW0R\t\t0xe10\n+#define FSL_QDMA_DECFDW1R\t\t0xe14\n+#define FSL_QDMA_DECFDW2R\t\t0xe18\n+#define FSL_QDMA_DECFDW3R\t\t0xe1c\n+#define FSL_QDMA_DECFQIDR\t\t0xe30\n+#define FSL_QDMA_DECBR\t\t\t0xe34\n+\n+#define FSL_QDMA_BCQMR(x)\t\t(0xc0 + 0x100 * (x))\n+#define FSL_QDMA_BCQSR(x)\t\t(0xc4 + 0x100 * (x))\n+#define FSL_QDMA_BCQEDPA_SADDR(x)\t(0xc8 + 0x100 * (x))\n+#define FSL_QDMA_BCQDPA_SADDR(x)\t(0xcc + 0x100 * (x))\n+#define FSL_QDMA_BCQEEPA_SADDR(x)\t(0xd0 + 0x100 * (x))\n+#define FSL_QDMA_BCQEPA_SADDR(x)\t(0xd4 + 0x100 * (x))\n+#define FSL_QDMA_BCQIER(x)\t\t(0xe0 + 0x100 * (x))\n+#define FSL_QDMA_BCQIDR(x)\t\t(0xe4 + 0x100 * (x))\n+\n+#define FSL_QDMA_SQEDPAR\t\t0x808\n+#define FSL_QDMA_SQDPAR\t\t\t0x80c\n+#define FSL_QDMA_SQEEPAR\t\t0x810\n+#define FSL_QDMA_SQEPAR\t\t\t0x814\n+#define FSL_QDMA_BSQMR\t\t\t0x800\n+#define FSL_QDMA_BSQSR\t\t\t0x804\n+#define FSL_QDMA_BSQICR\t\t\t0x828\n+#define FSL_QDMA_CQMR\t\t\t0xa00\n+#define FSL_QDMA_CQDSCR1\t\t0xa08\n+#define FSL_QDMA_CQDSCR2                0xa0c\n+#define FSL_QDMA_CQIER\t\t\t0xa10\n+#define FSL_QDMA_CQEDR\t\t\t0xa14\n+#define FSL_QDMA_SQCCMR\t\t\t0xa20\n+\n+#define FSL_QDMA_SQICR_ICEN\n+\n+#define FSL_QDMA_CQIDR_CQT\t\t0xff000000\n+#define FSL_QDMA_CQIDR_SQPE\t\t0x800000\n+#define FSL_QDMA_CQIDR_SQT\t\t0x8000\n+\n+#define FSL_QDMA_BCQIER_CQTIE\t\t0x8000\n+#define FSL_QDMA_BCQIER_CQPEIE\t\t0x800000\n+#define FSL_QDMA_BSQICR_ICEN\t\t0x80000000\n+#define FSL_QDMA_BSQICR_ICST(x)\t\t((x) << 16)\n+#define FSL_QDMA_CQIER_MEIE\t\t0x80000000\n+#define FSL_QDMA_CQIER_TEIE\t\t0x1\n+#define FSL_QDMA_SQCCMR_ENTER_WM\t0x200000\n+\n+#define FSL_QDMA_QUEUE_MAX\t\t8\n+\n+#define FSL_QDMA_BCQMR_EN\t\t0x80000000\n+#define FSL_QDMA_BCQMR_EI\t\t0x40000000\n+#define FSL_QDMA_BCQMR_EI_BE           0x40\n+#define FSL_QDMA_BCQMR_CD_THLD(x)\t((x) << 20)\n+#define FSL_QDMA_BCQMR_CQ_SIZE(x)\t((x) << 16)\n+\n+#define FSL_QDMA_BCQSR_QF\t\t0x10000\n+#define FSL_QDMA_BCQSR_XOFF\t\t0x1\n+#define FSL_QDMA_BCQSR_QF_XOFF_BE      0x1000100\n+\n+#define FSL_QDMA_BSQMR_EN\t\t0x80000000\n+#define FSL_QDMA_BSQMR_DI\t\t0x40000000\n+#define FSL_QDMA_BSQMR_DI_BE\t\t0x40\n+#define FSL_QDMA_BSQMR_CQ_SIZE(x)\t((x) << 16)\n+\n+#define FSL_QDMA_BSQSR_QE\t\t0x20000\n+#define FSL_QDMA_BSQSR_QE_BE\t\t0x200\n+#define FSL_QDMA_BSQSR_QF\t\t0x10000\n+\n+#define FSL_QDMA_DMR_DQD\t\t0x40000000\n+#define FSL_QDMA_DSR_DB\t\t\t0x80000000\n+\n+#define FSL_QDMA_COMMAND_BUFFER_SIZE\t64\n+#define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32\n+#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN\t64\n+#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX\t16384\n+#define FSL_QDMA_QUEUE_NUM_MAX\t\t8\n+\n+#define FSL_QDMA_CMD_RWTTYPE\t\t0x4\n+#define FSL_QDMA_CMD_LWC                0x2\n+\n+#define FSL_QDMA_CMD_RWTTYPE_OFFSET\t28\n+#define FSL_QDMA_CMD_NS_OFFSET\t\t27\n+#define FSL_QDMA_CMD_DQOS_OFFSET\t24\n+#define FSL_QDMA_CMD_WTHROTL_OFFSET\t20\n+#define FSL_QDMA_CMD_DSEN_OFFSET\t19\n+#define FSL_QDMA_CMD_LWC_OFFSET\t\t16\n+\n+#define QDMA_CCDF_STATUS\t\t20\n+#define QDMA_CCDF_OFFSET\t\t20\n+#define QDMA_CCDF_MASK\t\t\tGENMASK(28, 20)\n+#define QDMA_CCDF_FOTMAT\t\tBIT(29)\n+#define QDMA_CCDF_SER\t\t\tBIT(30)\n+\n+#define QDMA_SG_FIN\t\t\tBIT(30)\n+#define QDMA_SG_EXT\t\t\tBIT(31)\n+#define QDMA_SG_LEN_MASK\t\tGENMASK(29, 0)\n+\n+#define QDMA_BIG_ENDIAN\t\t\t1\n+#define COMP_TIMEOUT\t\t\t100000\n+#define COMMAND_QUEUE_OVERFLLOW\t\t10\n+\n+/* qdma engine attribute */\n+#define QDMA_QUEUE_SIZE 64\n+#define QDMA_STATUS_SIZE 64\n+#define QDMA_CCSR_BASE 0x8380000\n+#define VIRT_CHANNELS 32\n+#define QDMA_BLOCK_OFFSET 0x10000\n+#define QDMA_BLOCKS 4\n+#define QDMA_QUEUES 8\n+#define QDMA_DELAY 1000\n+\n+#ifdef QDMA_BIG_ENDIAN\n+#define QDMA_IN(addr)\t\tbe32_to_cpu(rte_read32(addr))\n+#define QDMA_OUT(addr, val)\trte_write32(be32_to_cpu(val), addr)\n+#define QDMA_IN_BE(addr)\trte_read32(addr)\n+#define QDMA_OUT_BE(addr, val)\trte_write32(val, addr)\n+#else\n+#define QDMA_IN(addr)\t\trte_read32(addr)\n+#define QDMA_OUT(addr, val)\trte_write32(val, addr)\n+#define QDMA_IN_BE(addr)\tbe32_to_cpu(rte_write32(addr))\n+#define QDMA_OUT_BE(addr, val)\trte_write32(be32_to_cpu(val), addr)\n+#endif\n+\n+#define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x)\t\t\t\\\n+\t(((fsl_qdma_engine)->block_offset) * (x))\n+\n+typedef void (*dma_call_back)(void *params);\n+\n+/* qDMA Command Descriptor Formats */\n+struct fsl_qdma_format {\n+\t__le32 status; /* ser, status */\n+\t__le32 cfg;\t/* format, offset */\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le32 addr_lo;\t/* low 32-bits of 40-bit address */\n+\t\t\tu8 addr_hi;\t/* high 8-bits of 40-bit address */\n+\t\t\tu8 __reserved1[2];\n+\t\t\tu8 cfg8b_w1; /* dd, queue */\n+\t\t};\n+\t\t__le64 data;\n+\t};\n+};\n+\n+/* qDMA Source Descriptor Format */\n+struct fsl_qdma_sdf {\n+\t__le32 rev3;\n+\t__le32 cfg; /* rev4, bit[0-11] - ssd, bit[12-23] sss */\n+\t__le32 rev5;\n+\t__le32 cmd;\n+};\n+\n+/* qDMA Destination Descriptor Format */\n+struct fsl_qdma_ddf {\n+\t__le32 rev1;\n+\t__le32 cfg; /* rev2, bit[0-11] - dsd, bit[12-23] - dss */\n+\t__le32 rev3;\n+\t__le32 cmd;\n+};\n+\n+enum dma_status {\n+\tDMA_COMPLETE,\n+\tDMA_IN_PROGRESS,\n+\tDMA_IN_PREPAR,\n+\tDMA_PAUSED,\n+\tDMA_ERROR,\n+};\n+\n+struct fsl_qdma_chan {\n+\tstruct fsl_qdma_engine\t*qdma;\n+\tstruct fsl_qdma_queue\t*queue;\n+\tbool\t\t\tfree;\n+\tstruct list_head\tlist;\n+};\n+\n+struct fsl_qdma_list {\n+\tstruct list_head\tdma_list;\n+};\n+\n+struct fsl_qdma_queue {\n+\tstruct fsl_qdma_format\t*virt_head;\n+\tstruct list_head\tcomp_used;\n+\tstruct list_head\tcomp_free;\n+\tdma_addr_t\t\tbus_addr;\n+\tu32                     n_cq;\n+\tu32\t\t\tid;\n+\tu32\t\t\tcount;\n+\tu32\t\t\tpending;\n+\tstruct fsl_qdma_format\t*cq;\n+\tvoid\t\t\t*block_base;\n+};\n+\n+struct fsl_qdma_comp {\n+\tdma_addr_t              bus_addr;\n+\tdma_addr_t              desc_bus_addr;\n+\tvoid\t\t\t*virt_addr;\n+\tint\t\t\tindex;\n+\tvoid\t\t\t*desc_virt_addr;\n+\tstruct fsl_qdma_chan\t*qchan;\n+\tdma_call_back\t\tcall_back_func;\n+\tvoid\t\t\t*params;\n+\tstruct list_head\tlist;\n+};\n+\n+struct fsl_qdma_engine {\n+\tint\t\t\tdesc_allocated;\n+\tvoid\t\t\t*ctrl_base;\n+\tvoid\t\t\t*status_base;\n+\tvoid\t\t\t*block_base;\n+\tu32\t\t\tn_chans;\n+\tu32\t\t\tn_queues;\n+\tint\t\t\terror_irq;\n+\tstruct fsl_qdma_queue\t*queue;\n+\tstruct fsl_qdma_queue\t**status;\n+\tstruct fsl_qdma_chan\t*chans;\n+\tu32\t\t\tnum_blocks;\n+\tu8\t\t\tfree_block_id;\n+\tu32\t\t\tvchan_map[4];\n+\tint\t\t\tblock_offset;\n+};\n+\n+static rte_atomic32_t wait_task[CORE_NUMBER];\n+\n+#endif /* _DPAA_QDMA_H_ */\n",
    "prefixes": [
        "v3",
        "2/7"
    ]
}