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{
    "id": 103804,
    "url": "http://patches.dpdk.org/api/patches/103804/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211104215846.58672-19-ajit.khaparde@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211104215846.58672-19-ajit.khaparde@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211104215846.58672-19-ajit.khaparde@broadcom.com",
    "date": "2021-11-04T21:58:42",
    "name": "[v5,18/22] net/bnxt: add TruFlow and AFM SRAM partitioning support",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "f71642bf52c61ad94c53b0bdf958795d30dfbff4",
    "submitter": {
        "id": 501,
        "url": "http://patches.dpdk.org/api/people/501/?format=api",
        "name": "Ajit Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211104215846.58672-19-ajit.khaparde@broadcom.com/mbox/",
    "series": [
        {
            "id": 20322,
            "url": "http://patches.dpdk.org/api/series/20322/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20322",
            "date": "2021-11-04T21:58:24",
            "name": "fixes and enhancements to Truflow",
            "version": 5,
            "mbox": "http://patches.dpdk.org/series/20322/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/103804/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/103804/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Jay Ding <jay.ding@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>,\n Randy Schacher <stuart.schacher@broadcom.com>,\n Farah Smith <farah.smith@broadcom.com>",
        "Date": "Thu,  4 Nov 2021 14:58:42 -0700",
        "Message-Id": "<20211104215846.58672-19-ajit.khaparde@broadcom.com>",
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        "References": "<20211103005251.25524-1-ajit.khaparde@broadcom.com>\n <20211104215846.58672-1-ajit.khaparde@broadcom.com>",
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        "Subject": "[dpdk-dev] [PATCH v5 18/22] net/bnxt: add TruFlow and AFM SRAM\n partitioning support",
        "X-BeenThere": "dev@dpdk.org",
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    },
    "content": "From: Jay Ding <jay.ding@broadcom.com>\n\nImplement set/get_sram_policy which support both rx/tx\ndirection truflow type the specific SRAM bank.\n\nSigned-off-by: Jay Ding <jay.ding@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Farah Smith <farah.smith@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/tf_core/tf_core.c       |  82 ++++++\n drivers/net/bnxt/tf_core/tf_core.h       |  66 ++++-\n drivers/net/bnxt/tf_core/tf_device.c     |   7 +-\n drivers/net/bnxt/tf_core/tf_device.h     |  34 ++-\n drivers/net/bnxt/tf_core/tf_device_p4.c  |   8 +-\n drivers/net/bnxt/tf_core/tf_device_p58.c | 311 ++++++++++++++++++++++-\n drivers/net/bnxt/tf_core/tf_device_p58.h | 118 +--------\n drivers/net/bnxt/tf_core/tf_tbl.c        |   2 +-\n 8 files changed, 503 insertions(+), 125 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c\nindex 346d220c87..90ff93946b 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.c\n+++ b/drivers/net/bnxt/tf_core/tf_core.c\n@@ -1917,3 +1917,85 @@ int tf_query_sram_resources(struct tf *tfp,\n \n \treturn 0;\n }\n+\n+int tf_set_sram_policy(struct tf *tfp,\n+\t\t       struct tf_set_sram_policy_parms *parms)\n+{\n+\tint rc = 0;\n+\tstruct tf_dev_info dev;\n+\n+\tTF_CHECK_PARMS2(tfp, parms);\n+\n+\t/* This function can be called before open session, filter\n+\t * out any non-supported device types on the Core side.\n+\t */\n+\tif (parms->device_type != TF_DEVICE_TYPE_THOR) {\n+\t\tTFP_DRV_LOG(ERR,\n+\t\t\t    \"Unsupported device type %d\\n\",\n+\t\t\t    parms->device_type);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\ttf_dev_bind_ops(parms->device_type, &dev);\n+\n+\tif (dev.ops->tf_dev_set_sram_policy == NULL) {\n+\t\trc = -EOPNOTSUPP;\n+\t\tTFP_DRV_LOG(ERR,\n+\t\t\t    \"%s: Operation not supported, rc:%s\\n\",\n+\t\t\t    tf_dir_2_str(parms->dir),\n+\t\t\t    strerror(-rc));\n+\t\treturn rc;\n+\t}\n+\n+\trc = dev.ops->tf_dev_set_sram_policy(parms->dir, parms->bank_id);\n+\tif (rc) {\n+\t\tTFP_DRV_LOG(ERR,\n+\t\t\t    \"%s: SRAM policy set failed, rc:%s\\n\",\n+\t\t\t    tf_dir_2_str(parms->dir),\n+\t\t\t    strerror(-rc));\n+\t\treturn rc;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int tf_get_sram_policy(struct tf *tfp,\n+\t\t       struct tf_get_sram_policy_parms *parms)\n+{\n+\tint rc = 0;\n+\tstruct tf_dev_info dev;\n+\n+\tTF_CHECK_PARMS2(tfp, parms);\n+\n+\t/* This function can be called before open session, filter\n+\t * out any non-supported device types on the Core side.\n+\t */\n+\tif (parms->device_type != TF_DEVICE_TYPE_THOR) {\n+\t\tTFP_DRV_LOG(ERR,\n+\t\t\t    \"Unsupported device type %d\\n\",\n+\t\t\t    parms->device_type);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\ttf_dev_bind_ops(parms->device_type, &dev);\n+\n+\tif (dev.ops->tf_dev_get_sram_policy == NULL) {\n+\t\trc = -EOPNOTSUPP;\n+\t\tTFP_DRV_LOG(ERR,\n+\t\t\t    \"%s: Operation not supported, rc:%s\\n\",\n+\t\t\t    tf_dir_2_str(parms->dir),\n+\t\t\t    strerror(-rc));\n+\t\treturn rc;\n+\t}\n+\n+\trc = dev.ops->tf_dev_get_sram_policy(parms->dir, parms->bank_id);\n+\tif (rc) {\n+\t\tTFP_DRV_LOG(ERR,\n+\t\t\t    \"%s: SRAM policy get failed, rc:%s\\n\",\n+\t\t\t    tf_dir_2_str(parms->dir),\n+\t\t\t    strerror(-rc));\n+\t\treturn rc;\n+\t}\n+\n+\treturn rc;\n+}\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h\nindex 078fd278a1..b2886355fa 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.h\n+++ b/drivers/net/bnxt/tf_core/tf_core.h\n@@ -2455,7 +2455,7 @@ int tf_get_version(struct tf *tfp,\n  */\n struct tf_query_sram_resources_parms {\n \t/**\n-\t * [in] device type\n+\t * [in] Device type\n \t *\n \t * Device type for the session.\n \t */\n@@ -2501,4 +2501,68 @@ struct tf_query_sram_resources_parms {\n int tf_query_sram_resources(struct tf *tfp,\n \t\t\t    struct tf_query_sram_resources_parms *parms);\n \n+/**\n+ * tf_set_sram_policy parameter definition\n+ */\n+struct tf_set_sram_policy_parms {\n+\t/**\n+\t * [in] Device type\n+\t *\n+\t * Device type for the session.\n+\t */\n+\tenum tf_device_type device_type;\n+\n+\t/**\n+\t * [in] Receive or transmit direction\n+\t */\n+\tenum tf_dir dir;\n+\n+\t/**\n+\t * [in] Array of Bank id for each truflow tbl type\n+\t */\n+\tuint8_t *bank_id;\n+};\n+\n+/**\n+ * Set SRAM policy\n+ *\n+ * Used to assign SRAM bank index to all truflow table type.\n+ *\n+ * Returns success or failure code.\n+ */\n+int tf_set_sram_policy(struct tf *tfp,\n+\t\t       struct tf_set_sram_policy_parms *parms);\n+\n+/**\n+ * tf_get_sram_policy parameter definition\n+ */\n+struct tf_get_sram_policy_parms {\n+\t/**\n+\t * [in] Device type\n+\t *\n+\t * Device type for the session.\n+\t */\n+\tenum tf_device_type device_type;\n+\n+\t/**\n+\t * [in] Receive or transmit direction\n+\t */\n+\tenum tf_dir dir;\n+\n+\t/**\n+\t * [out] Array of Bank id for each truflow tbl type\n+\t */\n+\tuint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1];\n+};\n+\n+/**\n+ * Get SRAM policy\n+ *\n+ * Used to get the assigned bank of table types.\n+ *\n+ * Returns success or failure code.\n+ */\n+int tf_get_sram_policy(struct tf *tfp,\n+\t\t       struct tf_get_sram_policy_parms *parms);\n+\n #endif /* _TF_CORE_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c\nindex 25a7166bbb..40db546604 100644\n--- a/drivers/net/bnxt/tf_core/tf_device.c\n+++ b/drivers/net/bnxt/tf_core/tf_device.c\n@@ -415,11 +415,14 @@ tf_dev_bind_p58(struct tf *tfp,\n \t}\n \n \trsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX,\n-\t\t\t\t\t   tf_tbl_p58,\n+\t\t\t\t\t   tf_tbl_p58[TF_DIR_RX],\n+\t\t\t\t\t   (uint16_t *)resources->tbl_cnt);\n+\trsv_cnt += tf_dev_reservation_check(TF_TBL_TYPE_MAX,\n+\t\t\t\t\t   tf_tbl_p58[TF_DIR_TX],\n \t\t\t\t\t   (uint16_t *)resources->tbl_cnt);\n \tif (rsv_cnt) {\n \t\ttbl_cfg.num_elements = TF_TBL_TYPE_MAX;\n-\t\ttbl_cfg.cfg = tf_tbl_p58;\n+\t\ttbl_cfg.cfg = tf_tbl_p58[TF_DIR_RX];\n \t\ttbl_cfg.resources = resources;\n \t\trc = tf_tbl_bind(tfp, &tbl_cfg);\n \t\tif (rc) {\ndiff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h\nindex 9360eb1358..3d5de988c4 100644\n--- a/drivers/net/bnxt/tf_core/tf_device.h\n+++ b/drivers/net/bnxt/tf_core/tf_device.h\n@@ -1083,7 +1083,7 @@ struct tf_dev_ops {\n \t\t\t\t     uint32_t *em_caps);\n \n \t/**\n-\t * Device specific function that retrieve the sram resource\n+\t * Device specific function that retrieves the sram resource\n \t *\n \t * [in] query\n \t *   Point to resources query result\n@@ -1101,6 +1101,38 @@ struct tf_dev_ops {\n \tint (*tf_dev_get_sram_resources)(void *query,\n \t\t\t\t\t uint32_t *sram_bank_caps,\n \t\t\t\t\t bool *dynamic_sram_capable);\n+\n+\t/**\n+\t * Device specific function that sets the sram policy\n+\t *\n+\t * [in] dir\n+\t *   Receive or transmit direction\n+\t *\n+\t * [in] band_id\n+\t *   SRAM bank id\n+\t *\n+\t * Returns\n+\t *   - (0) if successful.\n+\t *   - (-EINVAL) on failure.\n+\t */\n+\tint (*tf_dev_set_sram_policy)(enum tf_dir dir,\n+\t\t\t\t      uint8_t *bank_id);\n+\n+\t/**\n+\t * Device specific function that gets the sram policy\n+\t *\n+\t * [in] dir\n+\t *   Receive or transmit direction\n+\t *\n+\t * [in] band_id\n+\t *   pointer to SRAM bank id\n+\t *\n+\t * Returns\n+\t *   - (0) if successful.\n+\t *   - (-EINVAL) on failure.\n+\t */\n+\tint (*tf_dev_get_sram_policy)(enum tf_dir dir,\n+\t\t\t\t      uint8_t *bank_id);\n };\n \n /**\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c\nindex cf0e919f9f..244bd08914 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p4.c\n+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c\n@@ -383,7 +383,9 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {\n \t.tf_dev_get_mailbox = tf_dev_p4_get_mailbox,\n \t.tf_dev_word_align = NULL,\n \t.tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps,\n-\t.tf_dev_get_sram_resources = NULL\n+\t.tf_dev_get_sram_resources = NULL,\n+\t.tf_dev_set_sram_policy = NULL,\n+\t.tf_dev_get_sram_policy = NULL,\n };\n \n /**\n@@ -447,5 +449,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = {\n \t.tf_dev_word_align = tf_dev_p4_word_align,\n \t.tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash,\n \t.tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps,\n-\t.tf_dev_get_sram_resources = NULL\n+\t.tf_dev_get_sram_resources = NULL,\n+\t.tf_dev_set_sram_policy = NULL,\n+\t.tf_dev_get_sram_policy = NULL,\n };\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c\nindex 4687fa65dd..3c1c3a2de1 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p58.c\n+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c\n@@ -48,6 +48,235 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {\n \t[CFA_RESOURCE_TYPE_P58_METER_DROP_CNT]     = \"meter_dc\",\n };\n \n+struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {\n+\t[TF_DIR_RX][TF_TBL_TYPE_EM_FKB] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_WC_FKB] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_METER_INST] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_METER_DROP_CNT] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_METADATA] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,\n+\t\t0, 0\n+\t},\n+\t/* Policy - ARs in bank 1 */\n+\t[TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,\n+\t\t.slices          = 4,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,\n+\t\t.slices          = 8,\n+\t},\n+\t/* Policy - Encaps in bank 2 */\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 8,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 4,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 2,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 1,\n+\t},\n+\t/* Policy - Modify in bank 2 with Encaps */\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_8B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 8,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 4,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 2,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 1,\n+\t},\n+\t/* Policy - SP in bank 0 */\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n+\t\t.slices          = 8,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n+\t\t.slices          = 4,\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n+\t\t.slices          = 2,\n+\t},\n+\t/* Policy - Stats in bank 3 */\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,\n+\t\t.slices          = 8,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_WC_FKB] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_METER_INST] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_METER_DROP_CNT] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_METADATA] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,\n+\t\t0, 0\n+\t},\n+\t/* Policy - ARs in bank 1 */\n+\t[TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,\n+\t\t.slices          = 4,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,\n+\t\t.slices          = 8,\n+\t},\n+\t/* Policy - Encaps in bank 2 */\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 8,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 4,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 2,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 1,\n+\t},\n+\t/* Policy - Modify in bank 2 with Encaps */\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_8B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 8,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 4,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 2,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\t\t.slices          = 1,\n+\t},\n+\t/* Policy - SP in bank 0 */\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n+\t\t.slices\t         = 8,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n+\t\t.slices\t         = 4,\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n+\t\t.parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n+\t\t.slices\t         = 2,\n+\t},\n+\t/* Policy - Stats in bank 3 */\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {\n+\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n+\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,\n+\t\t.slices          = 8,\n+\t},\n+};\n+\n /**\n  * Device specific function that retrieves the MAX number of HCAPI\n  * types the device supports.\n@@ -444,6 +673,80 @@ static int tf_dev_p58_get_sram_resources(void *q,\n \treturn 0;\n }\n \n+int sram_bank_hcapi_type[] = {\n+\tCFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n+\tCFA_RESOURCE_TYPE_P58_SRAM_BANK_1,\n+\tCFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n+\tCFA_RESOURCE_TYPE_P58_SRAM_BANK_3\n+};\n+\n+/**\n+ * Device specific function that set the sram policy\n+ *\n+ * [in] dir\n+ *   Receive or transmit direction\n+ *\n+ * [in] band_id\n+ *   SRAM bank id\n+ *\n+ * Returns\n+ *   - (0) if successful.\n+ *   - (-EINVAL) on failure.\n+ */\n+static int tf_dev_p58_set_sram_policy(enum tf_dir dir,\n+\t\t\t\t      uint8_t *bank_id)\n+{\n+\tstruct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir];\n+\tuint8_t type;\n+\tuint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF };\n+\n+\tfor (type = TF_TBL_TYPE_FULL_ACT_RECORD;\n+\t\t\ttype < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) {\n+\t\tif (bank_id[type] > 3)\n+\t\t\treturn -EINVAL;\n+\n+\t\trm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]];\n+\t\tif (parent[bank_id[type]] == 0xFF) {\n+\t\t\tparent[bank_id[type]] = type;\n+\t\t\trm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT;\n+\t\t\trm_cfg[type].parent_subtype = 0;\n+\t\t\tif (rm_cfg[type].slices == 0)\n+\t\t\t\trm_cfg[type].slices = 1;\n+\t\t} else {\n+\t\t\trm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD;\n+\t\t\trm_cfg[type].parent_subtype = parent[bank_id[type]];\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Device specific function that get the sram policy\n+ *\n+ * [in] dir\n+ *   Receive or transmit direction\n+ *\n+ * [out] band_id\n+ *   pointer to SRAM bank id\n+ *\n+ * Returns\n+ *   - (0) if successful.\n+ *   - (-EINVAL) on failure.\n+ */\n+static int tf_dev_p58_get_sram_policy(enum tf_dir dir,\n+\t\t\t\t      uint8_t *bank_id)\n+{\n+\tstruct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir];\n+\tuint8_t type;\n+\n+\tfor (type = TF_TBL_TYPE_FULL_ACT_RECORD;\n+\t\t\ttype < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++)\n+\t\tbank_id[type] = rm_cfg[type].hcapi_type - CFA_RESOURCE_TYPE_P58_SRAM_BANK_0;\n+\n+\treturn 0;\n+}\n+\n /**\n  * Truflow P58 device specific functions\n  */\n@@ -495,7 +798,9 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {\n \t.tf_dev_get_mailbox = tf_dev_p58_get_mailbox,\n \t.tf_dev_word_align = NULL,\n \t.tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps,\n-\t.tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources\n+\t.tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources,\n+\t.tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy,\n+\t.tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy,\n };\n \n /**\n@@ -560,5 +865,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = {\n \t.tf_dev_word_align = tf_dev_p58_word_align,\n \t.tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash,\n \t.tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps,\n-\t.tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources\n+\t.tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources,\n+\t.tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy,\n+\t.tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy,\n };\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h\nindex f6e66936f3..61c856b767 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p58.h\n+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h\n@@ -12,6 +12,8 @@\n #include \"tf_if_tbl.h\"\n #include \"tf_global_cfg.h\"\n \n+extern struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX];\n+\n struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = {\n \t[TF_IDENT_TYPE_L2_CTXT_HIGH] = {\n \t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH,\n@@ -58,122 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {\n \t},\n };\n \n-struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {\n-\t[TF_TBL_TYPE_EM_FKB] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_WC_FKB] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_METER_PROF] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_METER_INST] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_METER_DROP_CNT] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_MIRROR_CONFIG] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_METADATA] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,\n-\t\t0, 0\n-\t},\n-\t/* Policy - ARs in bank 1 */\n-\t[TF_TBL_TYPE_FULL_ACT_RECORD] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,\n-\t\t.slices          = 4,\n-\t},\n-\t[TF_TBL_TYPE_COMPACT_ACT_RECORD] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,\n-\t\t.slices          = 8,\n-\t},\n-\t/* Policy - Encaps in bank 2 */\n-\t[TF_TBL_TYPE_ACT_ENCAP_8B] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n-\t\t.slices          = 8,\n-\t},\n-\t[TF_TBL_TYPE_ACT_ENCAP_16B] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n-\t\t.slices          = 4,\n-\t},\n-\t[TF_TBL_TYPE_ACT_ENCAP_32B] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n-\t\t.slices          = 2,\n-\t},\n-\t[TF_TBL_TYPE_ACT_ENCAP_64B] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n-\t\t.slices          = 1,\n-\t},\n-\t/* Policy - Modify in bank 2 with Encaps */\n-\t[TF_TBL_TYPE_ACT_MODIFY_8B] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n-\t\t.slices          = 8,\n-\t},\n-\t[TF_TBL_TYPE_ACT_MODIFY_16B] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n-\t\t.slices          = 4,\n-\t},\n-\t[TF_TBL_TYPE_ACT_MODIFY_32B] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n-\t\t.slices          = 2,\n-\t},\n-\t[TF_TBL_TYPE_ACT_MODIFY_64B] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,\n-\t\t.slices          = 1,\n-\t},\n-\t/* Policy - SP in bank 0 */\n-\t[TF_TBL_TYPE_ACT_SP_SMAC] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n-\t\t.slices          = 8,\n-\t},\n-\t[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n-\t\t.slices          = 4,\n-\t},\n-\t[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,\n-\t\t.parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,\n-\t\t.slices          = 2,\n-\t},\n-\t/* Policy - Stats in bank 3 */\n-\t[TF_TBL_TYPE_ACT_STATS_64] = {\n-\t\t.cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,\n-\t\t.hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,\n-\t\t.slices          = 8,\n-\t},\n-};\n-\n struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = {\n \t[TF_EM_TBL_TYPE_EM_RECORD] = {\n \t\tTF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC,\ndiff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c\nindex 12eca36491..3fb22b52ac 100644\n--- a/drivers/net/bnxt/tf_core/tf_tbl.c\n+++ b/drivers/net/bnxt/tf_core/tf_tbl.c\n@@ -58,10 +58,10 @@ tf_tbl_bind(struct tf *tfp,\n \tdb_cfg.num_elements = parms->num_elements;\n \tdb_cfg.module = TF_MODULE_TYPE_TABLE;\n \tdb_cfg.num_elements = parms->num_elements;\n-\tdb_cfg.cfg = parms->cfg;\n \n \tfor (d = 0; d < TF_DIR_MAX; d++) {\n \t\tdb_cfg.dir = d;\n+\t\tdb_cfg.cfg = &parms->cfg[d ? TF_TBL_TYPE_MAX : 0];\n \t\tdb_cfg.alloc_cnt = parms->resources->tbl_cnt[d].cnt;\n \t\tdb_cfg.rm_db = (void *)&tbl_db->tbl_db[d];\n \t\tif (tf_session_is_shared_session(tfs) &&\n",
    "prefixes": [
        "v5",
        "18/22"
    ]
}