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GET /api/patches/103782/?format=api
{ "id": 103782, "url": "http://patches.dpdk.org/api/patches/103782/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211104175904.60696-2-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211104175904.60696-2-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211104175904.60696-2-bingz@nvidia.com", "date": "2021-11-04T17:59:03", "name": "[v4,1/2] net/mlx5: add support for Rx queue delay drop", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4a440464b0368ebf092358836faf742e98be5a01", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211104175904.60696-2-bingz@nvidia.com/mbox/", "series": [ { "id": 20319, "url": "http://patches.dpdk.org/api/series/20319/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20319", "date": "2021-11-04T17:59:02", "name": "Add delay drop support for Rx queue", "version": 4, "mbox": "http://patches.dpdk.org/series/20319/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103782/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/103782/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 11B1AA0C57;\n\tThu, 4 Nov 2021 18:59:36 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5235642771;\n\tThu, 4 Nov 2021 18:59:34 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2047.outbound.protection.outlook.com [40.107.220.47])\n by mails.dpdk.org (Postfix) with ESMTP id 1D89142766\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=quarantine pct=100) action=none\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Q1uQUdj9ywda9C4+YndJcu0OHggR0KhwM9v/phGEDKk=;\n b=qrTM9Rb9tWeYXDyE4OFBQWJowKJrgd8eqAv4gJnSRIjJKTym7+GV3iU155AyM4PWSqb4Vzvwk8kL8XF52JjYsqNlpnxd2mlx0yWNGN0HJcEVwfmqOD3tuCd5dy3Tm3zR69S7cuz6kXExLPiKVMtMKEqbgeDrH2279YFbBlhL+qtVw7IjI0QA24CiO7+zU8LIMHidi3PBsynMnlsQz6GqGuVbEN5GOj9ScQ6SEVDkIKSVlw9l0Mnzf2ex86ISJNn9ZnkD6Ke6eMpSFtP9/z03OhSyXqv2Aq7ZUWIIT02KCFX0U3TmyG0ci/9hiP6mfHf/WbFZirY6qhc0oq6QwiauSw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <thomas@monjalon.net>,\n <orika@nvidia.com>", "Date": "Thu, 4 Nov 2021 19:59:03 +0200", "Message-ID": "<20211104175904.60696-2-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20211104175904.60696-1-bingz@nvidia.com>", "References": "<20211104112644.17278-1-bingz@nvidia.com>\n <20211104175904.60696-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "8156f2f8-be80-43ac-584f-08d99fbcd9a5", "X-MS-TrafficTypeDiagnostic": "CH2PR12MB3928:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <CH2PR12MB392881A9D87DB67C1AB74134D08D9@CH2PR12MB3928.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6790;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n NuBTwVGXqKXhQ20z64nGO5D+2j3hAqERVZFtvInPqR9gK8A/ITdu6yl2WIDtaIobADanYoOlZMiBkwBFidZUMh/2PjwhCCUMYN/CwGPUlNSZfH1zL0kZK5HrjRsQ6z45PnuW4qKpJ/VIJDuIbsulhSRsYoBV2zL/zBe2EBtDbVIDTcOe7gIkXmyaFu3PXDBNQjEdcTAs4tPkhRNqX50YTEwYzQspivLWC7+Oba+IQ04uloo4ifVO5gCOyY4qRijAWYvG0HPXWec90QJNn6DnZkQQchwSLjp42EwtdvaDNLUstJkbUnZHzlTDnlrc9ykLtuo2tWkDTBEApgBU816ntuUi2itOfhth2NdKF/3jhcmY7ppMM0outX3RY9LEtUKU8ct+eOwPDEBCKYlOry8Socki/nwMPK7uP34x7YECjJu5wege81VTBX7W9vEtpP7e4FIU6uYPQK3M1WuLWt+NuLurAQ3/uNqSp4yPJRkkVSTgJHZu3s5/mpNBvtghmR/FpJa7TC5YqeBkb0H1YvYe0CYD2/Y0fKBJrR7OyUz1XJjubhs9HKw9YEYXrI90t7k8oc0jnxMZuzokLH/+Ox6/dEQdnObJrRo6QBCdS8cHcvJbFKAONUpYyWW3ZLbn1Do/7espl5fzu/hu72nFrQigWWQYqIYPwhDSJqMjAhZBmEZOKgiCjnKKD6Q1w2ixyABlqPe7qCMbX+vJx3XSD9VWi6aTHTzsQOWEhCmFfahqfq0=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(110136005)(316002)(7636003)(54906003)(4326008)(356005)(55016002)(2906002)(36756003)(6636002)(8676002)(5660300002)(1076003)(70586007)(70206006)(16526019)(83380400001)(107886003)(336012)(86362001)(426003)(26005)(82310400003)(36860700001)(8936002)(508600001)(7696005)(186003)(6666004)(6286002)(2616005)(47076005)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Nov 2021 17:59:30.1587 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8156f2f8-be80-43ac-584f-08d99fbcd9a5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT010.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB3928", "Subject": "[dpdk-dev] [PATCH v4 1/2] net/mlx5: add support for Rx queue delay\n drop", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "For the Ethernet RQs, if there all receiving descriptors are\nexhausted, the packets being received will be dropped. This behavior\nprevents slow or malicious software entities at the host from\naffecting the network. While for hairpin cases, even if there is no\nsoftware involved during the packet forwarding from Rx to Tx side,\nsome hiccup in the hardware or back pressure from Tx side may still\ncause the descriptors to be exhausted. In certain scenarios it may be\npreferred to configure the device to avoid such packet drops,\nassuming the posting of descriptors will resume shortly.\n\nTo support this, a new devarg \"delay_drop_en\" is introduced, by\ndefault, the delay drop is enabled for hairpin Rx queues and\ndisabled for standard Rx queues. This value is used as a bit mask:\n - bit 0: enablement of standard Rx queue\n - bit 1: enablement of hairpin Rx queue\nAnd this attribute will be applied to all Rx queues of a device.\n\nThe \"rq_delay_drop\" capability in the HCA_CAP is checked before\ncreating any queue. If the hardware capabilities do not support\nthis delay drop, all the Rx queues will still be created without\nthis attribute, and the devarg setting will be ignored even if it\nis specified explicitly.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 1 +\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/net/mlx5/linux/mlx5_os.c | 11 +++++++++++\n drivers/net/mlx5/mlx5.c | 7 +++++++\n drivers/net/mlx5/mlx5.h | 9 +++++++++\n drivers/net/mlx5/mlx5_devx.c | 5 +++++\n drivers/net/mlx5/mlx5_rx.h | 1 +\n 7 files changed, 35 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 4ab3070da0..3748e54b22 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -964,6 +964,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t general_obj_types) &\n \t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);\n+\tattr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);\n \tif (attr->qos.sup) {\n \t\thcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,\n \t\t\t\tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 86ee4f7b78..50d3264b46 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -178,6 +178,7 @@ struct mlx5_hca_attr {\n \tuint32_t swp_csum:1;\n \tuint32_t swp_lso:1;\n \tuint32_t lro_max_msg_sz_mode:2;\n+\tuint32_t rq_delay_drop:1;\n \tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n \tuint16_t lro_min_mss_size;\n \tuint32_t flex_parser_protocols;\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex e0304b685e..de880ee4c9 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1508,6 +1508,15 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tgoto error;\n #endif\n \t}\n+\tif (config->std_delay_drop || config->hp_delay_drop) {\n+\t\tif (!config->hca_attr.rq_delay_drop) {\n+\t\t\tconfig->std_delay_drop = 0;\n+\t\t\tconfig->hp_delay_drop = 0;\n+\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\"dev_port-%u: Rxq delay drop is not supported\",\n+\t\t\t\tpriv->dev_port);\n+\t\t}\n+\t}\n \tif (sh->devx) {\n \t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n \n@@ -2077,6 +2086,8 @@ mlx5_os_config_default(struct mlx5_dev_config *config)\n \tconfig->decap_en = 1;\n \tconfig->log_hp_size = MLX5_ARG_UNSET;\n \tconfig->allow_duplicate_pattern = 1;\n+\tconfig->std_delay_drop = 0;\n+\tconfig->hp_delay_drop = 0;\n }\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 8614b8ffdd..a961cce430 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -183,6 +183,9 @@\n /* Device parameter to configure implicit registration of mempool memory. */\n #define MLX5_MR_MEMPOOL_REG_EN \"mr_mempool_reg_en\"\n \n+/* Device parameter to configure the delay drop when creating Rxqs. */\n+#define MLX5_DELAY_DROP_EN \"delay_drop_en\"\n+\n /* Shared memory between primary and secondary processes. */\n struct mlx5_shared_data *mlx5_shared_data;\n \n@@ -2091,6 +2094,9 @@ mlx5_args_check(const char *key, const char *val, void *opaque)\n \t\tconfig->decap_en = !!tmp;\n \t} else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {\n \t\tconfig->allow_duplicate_pattern = !!tmp;\n+\t} else if (strcmp(MLX5_DELAY_DROP_EN, key) == 0) {\n+\t\tconfig->std_delay_drop = tmp & MLX5_DELAY_DROP_STANDARD;\n+\t\tconfig->hp_delay_drop = tmp & MLX5_DELAY_DROP_HAIRPIN;\n \t} else {\n \t\tDRV_LOG(WARNING, \"%s: unknown parameter\", key);\n \t\trte_errno = EINVAL;\n@@ -2153,6 +2159,7 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)\n \t\tMLX5_DECAP_EN,\n \t\tMLX5_ALLOW_DUPLICATE_PATTERN,\n \t\tMLX5_MR_MEMPOOL_REG_EN,\n+\t\tMLX5_DELAY_DROP_EN,\n \t\tNULL,\n \t};\n \tstruct rte_kvargs *kvlist;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 51f4578838..b2022f3300 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -99,6 +99,13 @@ enum mlx5_flow_type {\n \tMLX5_FLOW_TYPE_MAXI,\n };\n \n+/* The mode of delay drop for Rx queues. */\n+enum mlx5_delay_drop_mode {\n+\tMLX5_DELAY_DROP_NONE = 0, /* All disabled. */\n+\tMLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */\n+\tMLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */\n+};\n+\n /* Hlist and list callback context. */\n struct mlx5_flow_cb_ctx {\n \tstruct rte_eth_dev *dev;\n@@ -264,6 +271,8 @@ struct mlx5_dev_config {\n \tunsigned int dv_miss_info:1; /* restore packet after partial hw miss */\n \tunsigned int allow_duplicate_pattern:1;\n \t/* Allow/Prevent the duplicate rules pattern. */\n+\tunsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */\n+\tunsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */\n \tstruct {\n \t\tunsigned int enabled:1; /* Whether MPRQ is enabled. */\n \t\tunsigned int stride_num_n; /* Number of strides. */\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex a9f9f4af70..e46f79124d 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -277,6 +277,7 @@ mlx5_rxq_create_devx_rq_resources(struct mlx5_rxq_priv *rxq)\n \t\t\t\t\t\tMLX5_WQ_END_PAD_MODE_NONE;\n \trq_attr.wq_attr.pd = cdev->pdn;\n \trq_attr.counter_set_id = priv->counter_set_id;\n+\trq_attr.delay_drop_en = rxq_data->delay_drop;\n \trq_attr.user_index = rte_cpu_to_be_16(priv->dev_data->port_id);\n \tif (rxq_data->shared) /* Create RMP based RQ. */\n \t\trxq->devx_rq.rmp = &rxq_ctrl->obj->devx_rmp;\n@@ -439,6 +440,8 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq)\n \t\t\tattr.wq_attr.log_hairpin_data_sz -\n \t\t\tMLX5_HAIRPIN_QUEUE_STRIDE;\n \tattr.counter_set_id = priv->counter_set_id;\n+\trxq_ctrl->rxq.delay_drop = priv->config.hp_delay_drop;\n+\tattr.delay_drop_en = priv->config.hp_delay_drop;\n \ttmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr,\n \t\t\t\t\t rxq_ctrl->socket);\n \tif (!tmpl->rq) {\n@@ -496,6 +499,7 @@ mlx5_rxq_devx_obj_new(struct mlx5_rxq_priv *rxq)\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n \t}\n+\trxq_data->delay_drop = priv->config.std_delay_drop;\n \t/* Create RQ using DevX API. */\n \tret = mlx5_rxq_create_devx_rq_resources(rxq);\n \tif (ret) {\n@@ -941,6 +945,7 @@ mlx5_rxq_devx_obj_drop_create(struct rte_eth_dev *dev)\n \t\t\tdev->data->port_id);\n \t\tgoto error;\n \t}\n+\trxq_ctrl->rxq.delay_drop = 0;\n \t/* Create RQ using DevX API. */\n \tret = mlx5_rxq_create_devx_rq_resources(rxq);\n \tif (ret != 0) {\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex eda6eca8de..3b797e577a 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -97,6 +97,7 @@ struct mlx5_rxq_data {\n \tunsigned int dynf_meta:1; /* Dynamic metadata is configured. */\n \tunsigned int mcqe_format:3; /* CQE compression format. */\n \tunsigned int shared:1; /* Shared RXQ. */\n+\tunsigned int delay_drop:1; /* Enable delay drop. */\n \tvolatile uint32_t *rq_db;\n \tvolatile uint32_t *cq_db;\n \tuint16_t port_id;\n", "prefixes": [ "v4", "1/2" ] }