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{
    "id": 103724,
    "url": "http://patches.dpdk.org/api/patches/103724/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211104103457.20264-8-kai.ji@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211104103457.20264-8-kai.ji@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211104103457.20264-8-kai.ji@intel.com",
    "date": "2021-11-04T10:34:55",
    "name": "[v8,7/9] crypto/qat: unified device private data structure",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "551cff5e6da944a08dea29c1f02c0484324479d4",
    "submitter": {
        "id": 2202,
        "url": "http://patches.dpdk.org/api/people/2202/?format=api",
        "name": "Ji, Kai",
        "email": "kai.ji@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211104103457.20264-8-kai.ji@intel.com/mbox/",
    "series": [
        {
            "id": 20302,
            "url": "http://patches.dpdk.org/api/series/20302/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20302",
            "date": "2021-11-04T10:34:48",
            "name": "drivers/qat: isolate implementations of qat generations",
            "version": 8,
            "mbox": "http://patches.dpdk.org/series/20302/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/103724/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/103724/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5397DA0548;\n\tThu,  4 Nov 2021 11:35:59 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 87E60426D6;\n\tThu,  4 Nov 2021 11:35:17 +0100 (CET)",
            "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id BEF4C426E9\n for <dev@dpdk.org>; Thu,  4 Nov 2021 11:35:15 +0100 (CET)",
            "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 04 Nov 2021 03:35:15 -0700",
            "from silpixa00400272.ir.intel.com (HELO\n silpixa00400272.ger.corp.intel.com) ([10.237.223.111])\n by fmsmga008.fm.intel.com with ESMTP; 04 Nov 2021 03:35:13 -0700"
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10157\"; a=\"212426619\"",
            "E=Sophos;i=\"5.87,208,1631602800\"; d=\"scan'208\";a=\"212426619\"",
            "E=Sophos;i=\"5.87,208,1631602800\"; d=\"scan'208\";a=\"542020267\""
        ],
        "X-ExtLoop1": "1",
        "From": "Kai Ji <kai.ji@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "gakhil@marvell.com, Fan Zhang <roy.fan.zhang@intel.com>,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>, Kai Ji <kai.ji@intel.com>",
        "Date": "Thu,  4 Nov 2021 10:34:55 +0000",
        "Message-Id": "<20211104103457.20264-8-kai.ji@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20211104103457.20264-1-kai.ji@intel.com>",
        "References": "<20211027155055.32264-1-kai.ji@intel.com>\n <20211104103457.20264-1-kai.ji@intel.com>",
        "Subject": "[dpdk-dev] [dpdk-dev v8 7/9] crypto/qat: unified device private\n data structure",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Fan Zhang <roy.fan.zhang@intel.com>\n\nThis patch unifies the QAT symmetric and asymmetric device\nprivate data structures and functions.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\nSigned-off-by: Kai Ji <kai.ji@intel.com>\nAcked-by: Ciara Power <ciara.power@intel.com>\n---\n drivers/common/qat/meson.build       |   2 +-\n drivers/common/qat/qat_common.c      |  15 ++\n drivers/common/qat/qat_common.h      |   3 +\n drivers/common/qat/qat_device.h      |   7 +-\n drivers/crypto/qat/qat_asym_pmd.c    | 216 ++++-------------------\n drivers/crypto/qat/qat_asym_pmd.h    |  29 +---\n drivers/crypto/qat/qat_crypto.c      | 176 +++++++++++++++++++\n drivers/crypto/qat/qat_crypto.h      |  78 +++++++++\n drivers/crypto/qat/qat_sym_pmd.c     | 250 +++++----------------------\n drivers/crypto/qat/qat_sym_pmd.h     |  21 +--\n drivers/crypto/qat/qat_sym_session.c |  15 +-\n 11 files changed, 365 insertions(+), 447 deletions(-)\n create mode 100644 drivers/crypto/qat/qat_crypto.c\n create mode 100644 drivers/crypto/qat/qat_crypto.h\n\n--\n2.17.1",
    "diff": "diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex 8a1c6d64e8..29fd0168ea 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -71,7 +71,7 @@ endif\n\n if qat_crypto\n     foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',\n-            'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c']\n+            'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c']\n         sources += files(join_paths(qat_crypto_relpath, f))\n     endforeach\n     deps += ['security']\ndiff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c\nindex 5343a1451e..59e7e02622 100644\n--- a/drivers/common/qat/qat_common.c\n+++ b/drivers/common/qat/qat_common.c\n@@ -6,6 +6,21 @@\n #include \"qat_device.h\"\n #include \"qat_logs.h\"\n\n+const char *\n+qat_service_get_str(enum qat_service_type type)\n+{\n+\tswitch (type) {\n+\tcase QAT_SERVICE_SYMMETRIC:\n+\t\treturn \"sym\";\n+\tcase QAT_SERVICE_ASYMMETRIC:\n+\t\treturn \"asym\";\n+\tcase QAT_SERVICE_COMPRESSION:\n+\t\treturn \"comp\";\n+\tdefault:\n+\t\treturn \"invalid\";\n+\t}\n+}\n+\n int\n qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset,\n \t\tvoid *list_in, uint32_t data_len,\ndiff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h\nindex a7632e31f8..9411a79301 100644\n--- a/drivers/common/qat/qat_common.h\n+++ b/drivers/common/qat/qat_common.h\n@@ -91,4 +91,7 @@ void\n qat_stats_reset(struct qat_pci_device *dev,\n \t\tenum qat_service_type service);\n\n+const char *\n+qat_service_get_str(enum qat_service_type type);\n+\n #endif /* _QAT_COMMON_H_ */\ndiff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h\nindex e7c7e9af95..85fae7b7c7 100644\n--- a/drivers/common/qat/qat_device.h\n+++ b/drivers/common/qat/qat_device.h\n@@ -76,8 +76,7 @@ struct qat_device_info {\n\n extern struct qat_device_info qat_pci_devs[];\n\n-struct qat_sym_dev_private;\n-struct qat_asym_dev_private;\n+struct qat_cryptodev_private;\n struct qat_comp_dev_private;\n\n /*\n@@ -106,14 +105,14 @@ struct qat_pci_device {\n \t/**< links to qps set up for each service, index same as on API */\n\n \t/* Data relating to symmetric crypto service */\n-\tstruct qat_sym_dev_private *sym_dev;\n+\tstruct qat_cryptodev_private *sym_dev;\n \t/**< link back to cryptodev private data */\n\n \tint qat_sym_driver_id;\n \t/**< Symmetric driver id used by this device */\n\n \t/* Data relating to asymmetric crypto service */\n-\tstruct qat_asym_dev_private *asym_dev;\n+\tstruct qat_cryptodev_private *asym_dev;\n \t/**< link back to cryptodev private data */\n\n \tint qat_asym_driver_id;\ndiff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c\nindex 0944d27a4d..042f39ddcc 100644\n--- a/drivers/crypto/qat/qat_asym_pmd.c\n+++ b/drivers/crypto/qat/qat_asym_pmd.c\n@@ -6,6 +6,7 @@\n\n #include \"qat_logs.h\"\n\n+#include \"qat_crypto.h\"\n #include \"qat_asym.h\"\n #include \"qat_asym_pmd.h\"\n #include \"qat_sym_capabilities.h\"\n@@ -18,190 +19,45 @@ static const struct rte_cryptodev_capabilities qat_gen1_asym_capabilities[] = {\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n\n-static int qat_asym_qp_release(struct rte_cryptodev *dev,\n-\t\t\t       uint16_t queue_pair_id);\n-\n-static int qat_asym_dev_config(__rte_unused struct rte_cryptodev *dev,\n-\t\t\t       __rte_unused struct rte_cryptodev_config *config)\n-{\n-\treturn 0;\n-}\n-\n-static int qat_asym_dev_start(__rte_unused struct rte_cryptodev *dev)\n-{\n-\treturn 0;\n-}\n-\n-static void qat_asym_dev_stop(__rte_unused struct rte_cryptodev *dev)\n-{\n-\n-}\n-\n-static int qat_asym_dev_close(struct rte_cryptodev *dev)\n-{\n-\tint i, ret;\n-\n-\tfor (i = 0; i < dev->data->nb_queue_pairs; i++) {\n-\t\tret = qat_asym_qp_release(dev, i);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void qat_asym_dev_info_get(struct rte_cryptodev *dev,\n-\t\t\t\t  struct rte_cryptodev_info *info)\n-{\n-\tstruct qat_asym_dev_private *internals = dev->data->dev_private;\n-\tstruct qat_pci_device *qat_dev = internals->qat_dev;\n-\n-\tif (info != NULL) {\n-\t\tinfo->max_nb_queue_pairs = qat_qps_per_service(qat_dev,\n-\t\t\t\t\t\t\tQAT_SERVICE_ASYMMETRIC);\n-\t\tinfo->feature_flags = dev->feature_flags;\n-\t\tinfo->capabilities = internals->qat_dev_capabilities;\n-\t\tinfo->driver_id = qat_asym_driver_id;\n-\t\t/* No limit of number of sessions */\n-\t\tinfo->sym.max_nb_sessions = 0;\n-\t}\n-}\n-\n-static void qat_asym_stats_get(struct rte_cryptodev *dev,\n-\t\t\t       struct rte_cryptodev_stats *stats)\n-{\n-\tstruct qat_common_stats qat_stats = {0};\n-\tstruct qat_asym_dev_private *qat_priv;\n-\n-\tif (stats == NULL || dev == NULL) {\n-\t\tQAT_LOG(ERR, \"invalid ptr: stats %p, dev %p\", stats, dev);\n-\t\treturn;\n-\t}\n-\tqat_priv = dev->data->dev_private;\n-\n-\tqat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_ASYMMETRIC);\n-\tstats->enqueued_count = qat_stats.enqueued_count;\n-\tstats->dequeued_count = qat_stats.dequeued_count;\n-\tstats->enqueue_err_count = qat_stats.enqueue_err_count;\n-\tstats->dequeue_err_count = qat_stats.dequeue_err_count;\n-}\n-\n-static void qat_asym_stats_reset(struct rte_cryptodev *dev)\n+void\n+qat_asym_init_op_cookie(void *op_cookie)\n {\n-\tstruct qat_asym_dev_private *qat_priv;\n+\tint j;\n+\tstruct qat_asym_op_cookie *cookie = op_cookie;\n\n-\tif (dev == NULL) {\n-\t\tQAT_LOG(ERR, \"invalid asymmetric cryptodev ptr %p\", dev);\n-\t\treturn;\n-\t}\n-\tqat_priv = dev->data->dev_private;\n+\tcookie->input_addr = rte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_asym_op_cookie,\n+\t\t\t\t\tinput_params_ptrs);\n\n-\tqat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_ASYMMETRIC);\n-}\n-\n-static int qat_asym_qp_release(struct rte_cryptodev *dev,\n-\t\t\t       uint16_t queue_pair_id)\n-{\n-\tstruct qat_asym_dev_private *qat_private = dev->data->dev_private;\n-\tenum qat_device_gen qat_dev_gen = qat_private->qat_dev->qat_dev_gen;\n-\n-\tQAT_LOG(DEBUG, \"Release asym qp %u on device %d\",\n-\t\t\t\tqueue_pair_id, dev->data->dev_id);\n-\n-\tqat_private->qat_dev->qps_in_use[QAT_SERVICE_ASYMMETRIC][queue_pair_id]\n-\t\t\t\t\t\t= NULL;\n-\n-\treturn qat_qp_release(qat_dev_gen, (struct qat_qp **)\n-\t\t\t&(dev->data->queue_pairs[queue_pair_id]));\n-}\n+\tcookie->output_addr = rte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_asym_op_cookie,\n+\t\t\t\t\toutput_params_ptrs);\n\n-static int qat_asym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n-\t\t\t     const struct rte_cryptodev_qp_conf *qp_conf,\n-\t\t\t     int socket_id)\n-{\n-\tstruct qat_qp_config qat_qp_conf;\n-\tstruct qat_qp *qp;\n-\tint ret = 0;\n-\tuint32_t i;\n-\n-\tstruct qat_qp **qp_addr =\n-\t\t\t(struct qat_qp **)&(dev->data->queue_pairs[qp_id]);\n-\tstruct qat_asym_dev_private *qat_private = dev->data->dev_private;\n-\tstruct qat_pci_device *qat_dev = qat_private->qat_dev;\n-\tconst struct qat_qp_hw_data *asym_hw_qps =\n-\t\t\tqat_gen_config[qat_private->qat_dev->qat_dev_gen]\n-\t\t\t\t      .qp_hw_data[QAT_SERVICE_ASYMMETRIC];\n-\tconst struct qat_qp_hw_data *qp_hw_data = asym_hw_qps + qp_id;\n-\n-\t/* If qp is already in use free ring memory and qp metadata. */\n-\tif (*qp_addr != NULL) {\n-\t\tret = qat_asym_qp_release(dev, qp_id);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t}\n-\tif (qp_id >= qat_qps_per_service(qat_dev, QAT_SERVICE_ASYMMETRIC)) {\n-\t\tQAT_LOG(ERR, \"qp_id %u invalid for this device\", qp_id);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tqat_qp_conf.hw = qp_hw_data;\n-\tqat_qp_conf.cookie_size = sizeof(struct qat_asym_op_cookie);\n-\tqat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;\n-\tqat_qp_conf.socket_id = socket_id;\n-\tqat_qp_conf.service_str = \"asym\";\n-\n-\tret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);\n-\tif (ret != 0)\n-\t\treturn ret;\n-\n-\t/* store a link to the qp in the qat_pci_device */\n-\tqat_private->qat_dev->qps_in_use[QAT_SERVICE_ASYMMETRIC][qp_id]\n-\t\t\t\t\t\t\t= *qp_addr;\n-\n-\tqp = (struct qat_qp *)*qp_addr;\n-\tqp->min_enq_burst_threshold = qat_private->min_enq_burst_threshold;\n-\n-\tfor (i = 0; i < qp->nb_descriptors; i++) {\n-\t\tint j;\n-\n-\t\tstruct qat_asym_op_cookie __rte_unused *cookie =\n-\t\t\t\tqp->op_cookies[i];\n-\t\tcookie->input_addr = rte_mempool_virt2iova(cookie) +\n+\tfor (j = 0; j < 8; j++) {\n+\t\tcookie->input_params_ptrs[j] =\n+\t\t\t\trte_mempool_virt2iova(cookie) +\n \t\t\t\toffsetof(struct qat_asym_op_cookie,\n-\t\t\t\t\t\tinput_params_ptrs);\n-\n-\t\tcookie->output_addr = rte_mempool_virt2iova(cookie) +\n+\t\t\t\t\t\tinput_array[j]);\n+\t\tcookie->output_params_ptrs[j] =\n+\t\t\t\trte_mempool_virt2iova(cookie) +\n \t\t\t\toffsetof(struct qat_asym_op_cookie,\n-\t\t\t\t\t\toutput_params_ptrs);\n-\n-\t\tfor (j = 0; j < 8; j++) {\n-\t\t\tcookie->input_params_ptrs[j] =\n-\t\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\t\toffsetof(struct qat_asym_op_cookie,\n-\t\t\t\t\t\t\tinput_array[j]);\n-\t\t\tcookie->output_params_ptrs[j] =\n-\t\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\t\toffsetof(struct qat_asym_op_cookie,\n-\t\t\t\t\t\t\toutput_array[j]);\n-\t\t}\n+\t\t\t\t\t\toutput_array[j]);\n \t}\n-\n-\treturn ret;\n }\n\n-struct rte_cryptodev_ops crypto_qat_ops = {\n+static struct rte_cryptodev_ops crypto_qat_ops = {\n\n \t/* Device related operations */\n-\t.dev_configure\t\t= qat_asym_dev_config,\n-\t.dev_start\t\t= qat_asym_dev_start,\n-\t.dev_stop\t\t= qat_asym_dev_stop,\n-\t.dev_close\t\t= qat_asym_dev_close,\n-\t.dev_infos_get\t\t= qat_asym_dev_info_get,\n+\t.dev_configure\t\t= qat_cryptodev_config,\n+\t.dev_start\t\t= qat_cryptodev_start,\n+\t.dev_stop\t\t= qat_cryptodev_stop,\n+\t.dev_close\t\t= qat_cryptodev_close,\n+\t.dev_infos_get\t\t= qat_cryptodev_info_get,\n\n-\t.stats_get\t\t= qat_asym_stats_get,\n-\t.stats_reset\t\t= qat_asym_stats_reset,\n-\t.queue_pair_setup\t= qat_asym_qp_setup,\n-\t.queue_pair_release\t= qat_asym_qp_release,\n+\t.stats_get\t\t= qat_cryptodev_stats_get,\n+\t.stats_reset\t\t= qat_cryptodev_stats_reset,\n+\t.queue_pair_setup\t= qat_cryptodev_qp_setup,\n+\t.queue_pair_release\t= qat_cryptodev_qp_release,\n\n \t/* Crypto related operations */\n \t.asym_session_get_size\t= qat_asym_session_get_private_size,\n@@ -241,15 +97,14 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,\n \tstruct qat_device_info *qat_dev_instance =\n \t\t\t&qat_pci_devs[qat_pci_dev->qat_dev_id];\n \tstruct rte_cryptodev_pmd_init_params init_params = {\n-\t\t\t.name = \"\",\n-\t\t\t.socket_id =\n-\t\t\t\tqat_dev_instance->pci_dev->device.numa_node,\n-\t\t\t.private_data_size = sizeof(struct qat_asym_dev_private)\n+\t\t.name = \"\",\n+\t\t.socket_id = qat_dev_instance->pci_dev->device.numa_node,\n+\t\t.private_data_size = sizeof(struct qat_cryptodev_private)\n \t};\n \tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n \tchar capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];\n \tstruct rte_cryptodev *cryptodev;\n-\tstruct qat_asym_dev_private *internals;\n+\tstruct qat_cryptodev_private *internals;\n\n \tif (qat_pci_dev->qat_dev_gen == QAT_GEN4) {\n \t\tQAT_LOG(ERR, \"Asymmetric crypto PMD not supported on QAT 4xxx\");\n@@ -310,8 +165,9 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,\n\n \tinternals = cryptodev->data->dev_private;\n \tinternals->qat_dev = qat_pci_dev;\n-\tinternals->asym_dev_id = cryptodev->data->dev_id;\n+\tinternals->dev_id = cryptodev->data->dev_id;\n \tinternals->qat_dev_capabilities = qat_gen1_asym_capabilities;\n+\tinternals->service_type = QAT_SERVICE_ASYMMETRIC;\n\n \tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n \tif (internals->capa_mz == NULL) {\n@@ -347,7 +203,7 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,\n \trte_cryptodev_pmd_probing_finish(cryptodev);\n\n \tQAT_LOG(DEBUG, \"Created QAT ASYM device %s as cryptodev instance %d\",\n-\t\t\tcryptodev->data->name, internals->asym_dev_id);\n+\t\t\tcryptodev->data->name, internals->dev_id);\n \treturn 0;\n }\n\n@@ -365,7 +221,7 @@ qat_asym_dev_destroy(struct qat_pci_device *qat_pci_dev)\n\n \t/* free crypto device */\n \tcryptodev = rte_cryptodev_pmd_get_dev(\n-\t\t\tqat_pci_dev->asym_dev->asym_dev_id);\n+\t\t\tqat_pci_dev->asym_dev->dev_id);\n \trte_cryptodev_pmd_destroy(cryptodev);\n \tqat_pci_devs[qat_pci_dev->qat_dev_id].asym_rte_dev.name = NULL;\n \tqat_pci_dev->asym_dev = NULL;\ndiff --git a/drivers/crypto/qat/qat_asym_pmd.h b/drivers/crypto/qat/qat_asym_pmd.h\nindex 3b5abddec8..c493796511 100644\n--- a/drivers/crypto/qat/qat_asym_pmd.h\n+++ b/drivers/crypto/qat/qat_asym_pmd.h\n@@ -15,21 +15,8 @@\n\n extern uint8_t qat_asym_driver_id;\n\n-/** private data structure for a QAT device.\n- * This QAT device is a device offering only asymmetric crypto service,\n- * there can be one of these on each qat_pci_device (VF).\n- */\n-struct qat_asym_dev_private {\n-\tstruct qat_pci_device *qat_dev;\n-\t/**< The qat pci device hosting the service */\n-\tuint8_t asym_dev_id;\n-\t/**< Device instance for this rte_cryptodev */\n-\tconst struct rte_cryptodev_capabilities *qat_dev_capabilities;\n-\t/* QAT device asymmetric crypto capabilities */\n-\tconst struct rte_memzone *capa_mz;\n-\t/* Shared memzone for storing capabilities */\n-\tuint16_t min_enq_burst_threshold;\n-};\n+void\n+qat_asym_init_op_cookie(void *op_cookie);\n\n uint16_t\n qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n@@ -39,16 +26,4 @@ uint16_t\n qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\t\t      uint16_t nb_ops);\n\n-int qat_asym_session_configure(struct rte_cryptodev *dev,\n-\t\tstruct rte_crypto_asym_xform *xform,\n-\t\tstruct rte_cryptodev_asym_session *sess,\n-\t\tstruct rte_mempool *mempool);\n-\n-int\n-qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,\n-\t\tstruct qat_dev_cmd_param *qat_dev_cmd_param);\n-\n-int\n-qat_asym_dev_destroy(struct qat_pci_device *qat_pci_dev);\n-\n #endif /* _QAT_ASYM_PMD_H_ */\ndiff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c\nnew file mode 100644\nindex 0000000000..84c26a8062\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_crypto.c\n@@ -0,0 +1,176 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#include \"qat_device.h\"\n+#include \"qat_qp.h\"\n+#include \"qat_crypto.h\"\n+#include \"qat_sym.h\"\n+#include \"qat_asym.h\"\n+\n+int\n+qat_cryptodev_config(__rte_unused struct rte_cryptodev *dev,\n+\t\t__rte_unused struct rte_cryptodev_config *config)\n+{\n+\treturn 0;\n+}\n+\n+int\n+qat_cryptodev_start(__rte_unused struct rte_cryptodev *dev)\n+{\n+\treturn 0;\n+}\n+\n+void\n+qat_cryptodev_stop(__rte_unused struct rte_cryptodev *dev)\n+{\n+}\n+\n+int\n+qat_cryptodev_close(struct rte_cryptodev *dev)\n+{\n+\tint i, ret;\n+\n+\tfor (i = 0; i < dev->data->nb_queue_pairs; i++) {\n+\t\tret = dev->dev_ops->queue_pair_release(dev, i);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void\n+qat_cryptodev_info_get(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_info *info)\n+{\n+\tstruct qat_cryptodev_private *qat_private = dev->data->dev_private;\n+\tstruct qat_pci_device *qat_dev = qat_private->qat_dev;\n+\tenum qat_service_type service_type = qat_private->service_type;\n+\n+\tif (info != NULL) {\n+\t\tinfo->max_nb_queue_pairs =\n+\t\t\tqat_qps_per_service(qat_dev, service_type);\n+\t\tinfo->feature_flags = dev->feature_flags;\n+\t\tinfo->capabilities = qat_private->qat_dev_capabilities;\n+\t\tif (service_type == QAT_SERVICE_ASYMMETRIC)\n+\t\t\tinfo->driver_id = qat_asym_driver_id;\n+\n+\t\tif (service_type == QAT_SERVICE_SYMMETRIC)\n+\t\t\tinfo->driver_id = qat_sym_driver_id;\n+\t\t/* No limit of number of sessions */\n+\t\tinfo->sym.max_nb_sessions = 0;\n+\t}\n+}\n+\n+void\n+qat_cryptodev_stats_get(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_stats *stats)\n+{\n+\tstruct qat_common_stats qat_stats = {0};\n+\tstruct qat_cryptodev_private *qat_priv;\n+\n+\tif (stats == NULL || dev == NULL) {\n+\t\tQAT_LOG(ERR, \"invalid ptr: stats %p, dev %p\", stats, dev);\n+\t\treturn;\n+\t}\n+\tqat_priv = dev->data->dev_private;\n+\n+\tqat_stats_get(qat_priv->qat_dev, &qat_stats, qat_priv->service_type);\n+\tstats->enqueued_count = qat_stats.enqueued_count;\n+\tstats->dequeued_count = qat_stats.dequeued_count;\n+\tstats->enqueue_err_count = qat_stats.enqueue_err_count;\n+\tstats->dequeue_err_count = qat_stats.dequeue_err_count;\n+}\n+\n+void\n+qat_cryptodev_stats_reset(struct rte_cryptodev *dev)\n+{\n+\tstruct qat_cryptodev_private *qat_priv;\n+\n+\tif (dev == NULL) {\n+\t\tQAT_LOG(ERR, \"invalid cryptodev ptr %p\", dev);\n+\t\treturn;\n+\t}\n+\tqat_priv = dev->data->dev_private;\n+\n+\tqat_stats_reset(qat_priv->qat_dev, qat_priv->service_type);\n+\n+}\n+\n+int\n+qat_cryptodev_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)\n+{\n+\tstruct qat_cryptodev_private *qat_private = dev->data->dev_private;\n+\tstruct qat_pci_device *qat_dev = qat_private->qat_dev;\n+\tenum qat_device_gen qat_dev_gen = qat_dev->qat_dev_gen;\n+\tenum qat_service_type service_type = qat_private->service_type;\n+\n+\tQAT_LOG(DEBUG, \"Release %s qp %u on device %d\",\n+\t\t\tqat_service_get_str(service_type),\n+\t\t\tqueue_pair_id, dev->data->dev_id);\n+\n+\tqat_private->qat_dev->qps_in_use[service_type][queue_pair_id] = NULL;\n+\n+\treturn qat_qp_release(qat_dev_gen, (struct qat_qp **)\n+\t\t\t&(dev->data->queue_pairs[queue_pair_id]));\n+}\n+\n+int\n+qat_cryptodev_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tconst struct rte_cryptodev_qp_conf *qp_conf, int socket_id)\n+{\n+\tstruct qat_qp **qp_addr =\n+\t\t\t(struct qat_qp **)&(dev->data->queue_pairs[qp_id]);\n+\tstruct qat_cryptodev_private *qat_private = dev->data->dev_private;\n+\tstruct qat_pci_device *qat_dev = qat_private->qat_dev;\n+\tenum qat_service_type service_type = qat_private->service_type;\n+\tstruct qat_qp_config qat_qp_conf = {0};\n+\tstruct qat_qp *qp;\n+\tint ret = 0;\n+\tuint32_t i;\n+\n+\t/* If qp is already in use free ring memory and qp metadata. */\n+\tif (*qp_addr != NULL) {\n+\t\tret = dev->dev_ops->queue_pair_release(dev, qp_id);\n+\t\tif (ret < 0)\n+\t\t\treturn -EBUSY;\n+\t}\n+\tif (qp_id >= qat_qps_per_service(qat_dev, service_type)) {\n+\t\tQAT_LOG(ERR, \"qp_id %u invalid for this device\", qp_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tqat_qp_conf.hw = qat_qp_get_hw_data(qat_dev, service_type,\n+\t\t\tqp_id);\n+\tif (qat_qp_conf.hw == NULL) {\n+\t\tQAT_LOG(ERR, \"qp_id %u invalid for this device\", qp_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tqat_qp_conf.cookie_size = service_type == QAT_SERVICE_SYMMETRIC ?\n+\t\t\tsizeof(struct qat_sym_op_cookie) :\n+\t\t\tsizeof(struct qat_asym_op_cookie);\n+\tqat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;\n+\tqat_qp_conf.socket_id = socket_id;\n+\tqat_qp_conf.service_str = qat_service_get_str(service_type);\n+\n+\tret = qat_qp_setup(qat_dev, qp_addr, qp_id, &qat_qp_conf);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\t/* store a link to the qp in the qat_pci_device */\n+\tqat_dev->qps_in_use[service_type][qp_id] = *qp_addr;\n+\n+\tqp = (struct qat_qp *)*qp_addr;\n+\tqp->min_enq_burst_threshold = qat_private->min_enq_burst_threshold;\n+\n+\tfor (i = 0; i < qp->nb_descriptors; i++) {\n+\t\tif (service_type == QAT_SERVICE_SYMMETRIC)\n+\t\t\tqat_sym_init_op_cookie(qp->op_cookies[i]);\n+\t\telse\n+\t\t\tqat_asym_init_op_cookie(qp->op_cookies[i]);\n+\t}\n+\n+\treturn ret;\n+}\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nnew file mode 100644\nindex 0000000000..3803fef19d\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -0,0 +1,78 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+ #ifndef _QAT_CRYPTO_H_\n+ #define _QAT_CRYPTO_H_\n+\n+#include <rte_cryptodev.h>\n+#ifdef RTE_LIB_SECURITY\n+#include <rte_security.h>\n+#endif\n+\n+#include \"qat_device.h\"\n+\n+extern uint8_t qat_sym_driver_id;\n+extern uint8_t qat_asym_driver_id;\n+\n+/** helper macro to set cryptodev capability range **/\n+#define CAP_RNG(n, l, r, i) .n = {.min = l, .max = r, .increment = i}\n+\n+#define CAP_RNG_ZERO(n) .n = {.min = 0, .max = 0, .increment = 0}\n+/** helper macro to set cryptodev capability value **/\n+#define CAP_SET(n, v) .n = v\n+\n+/** private data structure for a QAT device.\n+ * there can be one of these on each qat_pci_device (VF).\n+ */\n+struct qat_cryptodev_private {\n+\tstruct qat_pci_device *qat_dev;\n+\t/**< The qat pci device hosting the service */\n+\tuint8_t dev_id;\n+\t/**< Device instance for this rte_cryptodev */\n+\tconst struct rte_cryptodev_capabilities *qat_dev_capabilities;\n+\t/* QAT device symmetric crypto capabilities */\n+\tconst struct rte_memzone *capa_mz;\n+\t/* Shared memzone for storing capabilities */\n+\tuint16_t min_enq_burst_threshold;\n+\tuint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */\n+\tenum qat_service_type service_type;\n+};\n+\n+struct qat_capabilities_info {\n+\tstruct rte_cryptodev_capabilities *data;\n+\tuint64_t size;\n+};\n+\n+int\n+qat_cryptodev_config(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_config *config);\n+\n+int\n+qat_cryptodev_start(struct rte_cryptodev *dev);\n+\n+void\n+qat_cryptodev_stop(struct rte_cryptodev *dev);\n+\n+int\n+qat_cryptodev_close(struct rte_cryptodev *dev);\n+\n+void\n+qat_cryptodev_info_get(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_info *info);\n+\n+void\n+qat_cryptodev_stats_get(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_stats *stats);\n+\n+void\n+qat_cryptodev_stats_reset(struct rte_cryptodev *dev);\n+\n+int\n+qat_cryptodev_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tconst struct rte_cryptodev_qp_conf *qp_conf, int socket_id);\n+\n+int\n+qat_cryptodev_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id);\n+\n+#endif\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex 5b8ee4bee6..dec877cfab 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -13,6 +13,7 @@\n #endif\n\n #include \"qat_logs.h\"\n+#include \"qat_crypto.h\"\n #include \"qat_sym.h\"\n #include \"qat_sym_session.h\"\n #include \"qat_sym_pmd.h\"\n@@ -59,213 +60,19 @@ static const struct rte_security_capability qat_security_capabilities[] = {\n };\n #endif\n\n-static int qat_sym_qp_release(struct rte_cryptodev *dev,\n-\tuint16_t queue_pair_id);\n-\n-static int qat_sym_dev_config(__rte_unused struct rte_cryptodev *dev,\n-\t\t__rte_unused struct rte_cryptodev_config *config)\n-{\n-\treturn 0;\n-}\n-\n-static int qat_sym_dev_start(__rte_unused struct rte_cryptodev *dev)\n-{\n-\treturn 0;\n-}\n-\n-static void qat_sym_dev_stop(__rte_unused struct rte_cryptodev *dev)\n-{\n-\treturn;\n-}\n-\n-static int qat_sym_dev_close(struct rte_cryptodev *dev)\n-{\n-\tint i, ret;\n-\n-\tfor (i = 0; i < dev->data->nb_queue_pairs; i++) {\n-\t\tret = qat_sym_qp_release(dev, i);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void qat_sym_dev_info_get(struct rte_cryptodev *dev,\n-\t\t\tstruct rte_cryptodev_info *info)\n-{\n-\tstruct qat_sym_dev_private *internals = dev->data->dev_private;\n-\tstruct qat_pci_device *qat_dev = internals->qat_dev;\n-\n-\tif (info != NULL) {\n-\t\tinfo->max_nb_queue_pairs =\n-\t\t\tqat_qps_per_service(qat_dev, QAT_SERVICE_SYMMETRIC);\n-\t\tinfo->feature_flags = dev->feature_flags;\n-\t\tinfo->capabilities = internals->qat_dev_capabilities;\n-\t\tinfo->driver_id = qat_sym_driver_id;\n-\t\t/* No limit of number of sessions */\n-\t\tinfo->sym.max_nb_sessions = 0;\n-\t}\n-}\n-\n-static void qat_sym_stats_get(struct rte_cryptodev *dev,\n-\t\tstruct rte_cryptodev_stats *stats)\n-{\n-\tstruct qat_common_stats qat_stats = {0};\n-\tstruct qat_sym_dev_private *qat_priv;\n-\n-\tif (stats == NULL || dev == NULL) {\n-\t\tQAT_LOG(ERR, \"invalid ptr: stats %p, dev %p\", stats, dev);\n-\t\treturn;\n-\t}\n-\tqat_priv = dev->data->dev_private;\n-\n-\tqat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_SYMMETRIC);\n-\tstats->enqueued_count = qat_stats.enqueued_count;\n-\tstats->dequeued_count = qat_stats.dequeued_count;\n-\tstats->enqueue_err_count = qat_stats.enqueue_err_count;\n-\tstats->dequeue_err_count = qat_stats.dequeue_err_count;\n-}\n-\n-static void qat_sym_stats_reset(struct rte_cryptodev *dev)\n-{\n-\tstruct qat_sym_dev_private *qat_priv;\n-\n-\tif (dev == NULL) {\n-\t\tQAT_LOG(ERR, \"invalid cryptodev ptr %p\", dev);\n-\t\treturn;\n-\t}\n-\tqat_priv = dev->data->dev_private;\n-\n-\tqat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_SYMMETRIC);\n-\n-}\n-\n-static int qat_sym_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)\n-{\n-\tstruct qat_sym_dev_private *qat_private = dev->data->dev_private;\n-\tenum qat_device_gen qat_dev_gen = qat_private->qat_dev->qat_dev_gen;\n-\n-\tQAT_LOG(DEBUG, \"Release sym qp %u on device %d\",\n-\t\t\t\tqueue_pair_id, dev->data->dev_id);\n-\n-\tqat_private->qat_dev->qps_in_use[QAT_SERVICE_SYMMETRIC][queue_pair_id]\n-\t\t\t\t\t\t= NULL;\n-\n-\treturn qat_qp_release(qat_dev_gen, (struct qat_qp **)\n-\t\t\t&(dev->data->queue_pairs[queue_pair_id]));\n-}\n-\n-static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n-\tconst struct rte_cryptodev_qp_conf *qp_conf,\n-\tint socket_id)\n-{\n-\tstruct qat_qp *qp;\n-\tint ret = 0;\n-\tuint32_t i;\n-\tstruct qat_qp_config qat_qp_conf;\n-\tstruct qat_qp **qp_addr =\n-\t\t\t(struct qat_qp **)&(dev->data->queue_pairs[qp_id]);\n-\tstruct qat_sym_dev_private *qat_private = dev->data->dev_private;\n-\tstruct qat_pci_device *qat_dev = qat_private->qat_dev;\n-\n-\t/* If qp is already in use free ring memory and qp metadata. */\n-\tif (*qp_addr != NULL) {\n-\t\tret = qat_sym_qp_release(dev, qp_id);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t}\n-\tif (qp_id >= qat_qps_per_service(qat_dev, QAT_SERVICE_SYMMETRIC)) {\n-\t\tQAT_LOG(ERR, \"qp_id %u invalid for this device\", qp_id);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tqat_qp_conf.hw = qat_qp_get_hw_data(qat_dev, QAT_SERVICE_SYMMETRIC,\n-\t\t\tqp_id);\n-\tif (qat_qp_conf.hw == NULL) {\n-\t\tQAT_LOG(ERR, \"qp_id %u invalid for this device\", qp_id);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tqat_qp_conf.cookie_size = sizeof(struct qat_sym_op_cookie);\n-\tqat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;\n-\tqat_qp_conf.socket_id = socket_id;\n-\tqat_qp_conf.service_str = \"sym\";\n-\n-\tret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);\n-\tif (ret != 0)\n-\t\treturn ret;\n-\n-\t/* store a link to the qp in the qat_pci_device */\n-\tqat_private->qat_dev->qps_in_use[QAT_SERVICE_SYMMETRIC][qp_id]\n-\t\t\t\t\t\t\t= *qp_addr;\n-\n-\tqp = (struct qat_qp *)*qp_addr;\n-\tqp->min_enq_burst_threshold = qat_private->min_enq_burst_threshold;\n-\n-\tfor (i = 0; i < qp->nb_descriptors; i++) {\n-\n-\t\tstruct qat_sym_op_cookie *cookie =\n-\t\t\t\tqp->op_cookies[i];\n-\n-\t\tcookie->qat_sgl_src_phys_addr =\n-\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\toffsetof(struct qat_sym_op_cookie,\n-\t\t\t\tqat_sgl_src);\n-\n-\t\tcookie->qat_sgl_dst_phys_addr =\n-\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\toffsetof(struct qat_sym_op_cookie,\n-\t\t\t\tqat_sgl_dst);\n-\n-\t\tcookie->opt.spc_gmac.cd_phys_addr =\n-\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\toffsetof(struct qat_sym_op_cookie,\n-\t\t\t\topt.spc_gmac.cd_cipher);\n-\n-\t}\n-\n-\t/* Get fw version from QAT (GEN2), skip if we've got it already */\n-\tif (qp->qat_dev_gen == QAT_GEN2 && !(qat_private->internal_capabilities\n-\t\t\t& QAT_SYM_CAP_VALID)) {\n-\t\tret = qat_cq_get_fw_version(qp);\n-\n-\t\tif (ret < 0) {\n-\t\t\tqat_sym_qp_release(dev, qp_id);\n-\t\t\treturn ret;\n-\t\t}\n-\n-\t\tif (ret != 0)\n-\t\t\tQAT_LOG(DEBUG, \"QAT firmware version: %d.%d.%d\",\n-\t\t\t\t\t(ret >> 24) & 0xff,\n-\t\t\t\t\t(ret >> 16) & 0xff,\n-\t\t\t\t\t(ret >> 8) & 0xff);\n-\t\telse\n-\t\t\tQAT_LOG(DEBUG, \"unknown QAT firmware version\");\n-\n-\t\t/* set capabilities based on the fw version */\n-\t\tqat_private->internal_capabilities = QAT_SYM_CAP_VALID |\n-\t\t\t\t((ret >= MIXED_CRYPTO_MIN_FW_VER) ?\n-\t\t\t\t\t\tQAT_SYM_CAP_MIXED_CRYPTO : 0);\n-\t\tret = 0;\n-\t}\n-\n-\treturn ret;\n-}\n-\n static struct rte_cryptodev_ops crypto_qat_ops = {\n\n \t\t/* Device related operations */\n-\t\t.dev_configure\t\t= qat_sym_dev_config,\n-\t\t.dev_start\t\t= qat_sym_dev_start,\n-\t\t.dev_stop\t\t= qat_sym_dev_stop,\n-\t\t.dev_close\t\t= qat_sym_dev_close,\n-\t\t.dev_infos_get\t\t= qat_sym_dev_info_get,\n+\t\t.dev_configure\t\t= qat_cryptodev_config,\n+\t\t.dev_start\t\t= qat_cryptodev_start,\n+\t\t.dev_stop\t\t= qat_cryptodev_stop,\n+\t\t.dev_close\t\t= qat_cryptodev_close,\n+\t\t.dev_infos_get\t\t= qat_cryptodev_info_get,\n\n-\t\t.stats_get\t\t= qat_sym_stats_get,\n-\t\t.stats_reset\t\t= qat_sym_stats_reset,\n-\t\t.queue_pair_setup\t= qat_sym_qp_setup,\n-\t\t.queue_pair_release\t= qat_sym_qp_release,\n+\t\t.stats_get\t\t= qat_cryptodev_stats_get,\n+\t\t.stats_reset\t\t= qat_cryptodev_stats_reset,\n+\t\t.queue_pair_setup\t= qat_cryptodev_qp_setup,\n+\t\t.queue_pair_release\t= qat_cryptodev_qp_release,\n\n \t\t/* Crypto related operations */\n \t\t.sym_session_get_size\t= qat_sym_session_get_private_size,\n@@ -295,6 +102,27 @@ static struct rte_security_ops security_qat_ops = {\n };\n #endif\n\n+void\n+qat_sym_init_op_cookie(void *op_cookie)\n+{\n+\tstruct qat_sym_op_cookie *cookie = op_cookie;\n+\n+\tcookie->qat_sgl_src_phys_addr =\n+\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_sym_op_cookie,\n+\t\t\tqat_sgl_src);\n+\n+\tcookie->qat_sgl_dst_phys_addr =\n+\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_sym_op_cookie,\n+\t\t\tqat_sgl_dst);\n+\n+\tcookie->opt.spc_gmac.cd_phys_addr =\n+\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\toffsetof(struct qat_sym_op_cookie,\n+\t\t\topt.spc_gmac.cd_cipher);\n+}\n+\n static uint16_t\n qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\tuint16_t nb_ops)\n@@ -330,15 +158,14 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,\n \t\t\t&qat_pci_devs[qat_pci_dev->qat_dev_id];\n\n \tstruct rte_cryptodev_pmd_init_params init_params = {\n-\t\t\t.name = \"\",\n-\t\t\t.socket_id =\n-\t\t\t\tqat_dev_instance->pci_dev->device.numa_node,\n-\t\t\t.private_data_size = sizeof(struct qat_sym_dev_private)\n+\t\t.name = \"\",\n+\t\t.socket_id = qat_dev_instance->pci_dev->device.numa_node,\n+\t\t.private_data_size = sizeof(struct qat_cryptodev_private)\n \t};\n \tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n \tchar capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];\n \tstruct rte_cryptodev *cryptodev;\n-\tstruct qat_sym_dev_private *internals;\n+\tstruct qat_cryptodev_private *internals;\n \tconst struct rte_cryptodev_capabilities *capabilities;\n \tuint64_t capa_size;\n\n@@ -424,8 +251,9 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,\n\n \tinternals = cryptodev->data->dev_private;\n \tinternals->qat_dev = qat_pci_dev;\n+\tinternals->service_type = QAT_SERVICE_SYMMETRIC;\n\n-\tinternals->sym_dev_id = cryptodev->data->dev_id;\n+\tinternals->dev_id = cryptodev->data->dev_id;\n \tswitch (qat_pci_dev->qat_dev_gen) {\n \tcase QAT_GEN1:\n \t\tcapabilities = qat_gen1_sym_capabilities;\n@@ -480,7 +308,7 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,\n\n \tqat_pci_dev->sym_dev = internals;\n \tQAT_LOG(DEBUG, \"Created QAT SYM device %s as cryptodev instance %d\",\n-\t\t\tcryptodev->data->name, internals->sym_dev_id);\n+\t\t\tcryptodev->data->name, internals->dev_id);\n\n \trte_cryptodev_pmd_probing_finish(cryptodev);\n\n@@ -511,7 +339,7 @@ qat_sym_dev_destroy(struct qat_pci_device *qat_pci_dev)\n \t\trte_memzone_free(qat_pci_dev->sym_dev->capa_mz);\n\n \t/* free crypto device */\n-\tcryptodev = rte_cryptodev_pmd_get_dev(qat_pci_dev->sym_dev->sym_dev_id);\n+\tcryptodev = rte_cryptodev_pmd_get_dev(qat_pci_dev->sym_dev->dev_id);\n #ifdef RTE_LIB_SECURITY\n \trte_free(cryptodev->security_ctx);\n \tcryptodev->security_ctx = NULL;\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h\nindex e0992cbe27..d49b732ca0 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.h\n+++ b/drivers/crypto/qat/qat_sym_pmd.h\n@@ -14,6 +14,7 @@\n #endif\n\n #include \"qat_sym_capabilities.h\"\n+#include \"qat_crypto.h\"\n #include \"qat_device.h\"\n\n /** Intel(R) QAT Symmetric Crypto PMD driver name */\n@@ -25,23 +26,6 @@\n\n extern uint8_t qat_sym_driver_id;\n\n-/** private data structure for a QAT device.\n- * This QAT device is a device offering only symmetric crypto service,\n- * there can be one of these on each qat_pci_device (VF).\n- */\n-struct qat_sym_dev_private {\n-\tstruct qat_pci_device *qat_dev;\n-\t/**< The qat pci device hosting the service */\n-\tuint8_t sym_dev_id;\n-\t/**< Device instance for this rte_cryptodev */\n-\tconst struct rte_cryptodev_capabilities *qat_dev_capabilities;\n-\t/* QAT device symmetric crypto capabilities */\n-\tconst struct rte_memzone *capa_mz;\n-\t/* Shared memzone for storing capabilities */\n-\tuint16_t min_enq_burst_threshold;\n-\tuint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */\n-};\n-\n int\n qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,\n \t\tstruct qat_dev_cmd_param *qat_dev_cmd_param);\n@@ -49,5 +33,8 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,\n int\n qat_sym_dev_destroy(struct qat_pci_device *qat_pci_dev);\n\n+void\n+qat_sym_init_op_cookie(void *op_cookie);\n+\n #endif\n #endif /* _QAT_SYM_PMD_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 3f2f6736fc..8ca475ca8b 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -131,7 +131,7 @@ bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,\n\n static int\n qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,\n-\t\tstruct qat_sym_dev_private *internals)\n+\t\tstruct qat_cryptodev_private *internals)\n {\n \tint i = 0;\n \tconst struct rte_cryptodev_capabilities *capability;\n@@ -152,7 +152,7 @@ qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,\n\n static int\n qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,\n-\t\tstruct qat_sym_dev_private *internals)\n+\t\tstruct qat_cryptodev_private *internals)\n {\n \tint i = 0;\n \tconst struct rte_cryptodev_capabilities *capability;\n@@ -267,7 +267,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \t\tstruct rte_crypto_sym_xform *xform,\n \t\tstruct qat_sym_session *session)\n {\n-\tstruct qat_sym_dev_private *internals = dev->data->dev_private;\n+\tstruct qat_cryptodev_private *internals = dev->data->dev_private;\n \tstruct rte_crypto_cipher_xform *cipher_xform = NULL;\n \tenum qat_device_gen qat_dev_gen =\n \t\t\t\tinternals->qat_dev->qat_dev_gen;\n@@ -532,7 +532,8 @@ static void\n qat_sym_session_handle_mixed(const struct rte_cryptodev *dev,\n \t\tstruct qat_sym_session *session)\n {\n-\tconst struct qat_sym_dev_private *qat_private = dev->data->dev_private;\n+\tconst struct qat_cryptodev_private *qat_private =\n+\t\t\tdev->data->dev_private;\n \tenum qat_device_gen min_dev_gen = (qat_private->internal_capabilities &\n \t\t\tQAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3;\n\n@@ -564,7 +565,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\tstruct rte_crypto_sym_xform *xform, void *session_private)\n {\n \tstruct qat_sym_session *session = session_private;\n-\tstruct qat_sym_dev_private *internals = dev->data->dev_private;\n+\tstruct qat_cryptodev_private *internals = dev->data->dev_private;\n \tenum qat_device_gen qat_dev_gen = internals->qat_dev->qat_dev_gen;\n \tint ret;\n \tint qat_cmd_id;\n@@ -707,7 +708,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\t\tstruct qat_sym_session *session)\n {\n \tstruct rte_crypto_auth_xform *auth_xform = qat_get_auth_xform(xform);\n-\tstruct qat_sym_dev_private *internals = dev->data->dev_private;\n+\tstruct qat_cryptodev_private *internals = dev->data->dev_private;\n \tconst uint8_t *key_data = auth_xform->key.data;\n \tuint8_t key_length = auth_xform->key.length;\n \tenum qat_device_gen qat_dev_gen =\n@@ -875,7 +876,7 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n {\n \tstruct rte_crypto_aead_xform *aead_xform = &xform->aead;\n \tenum rte_crypto_auth_operation crypto_operation;\n-\tstruct qat_sym_dev_private *internals =\n+\tstruct qat_cryptodev_private *internals =\n \t\t\tdev->data->dev_private;\n \tenum qat_device_gen qat_dev_gen =\n \t\t\tinternals->qat_dev->qat_dev_gen;\n",
    "prefixes": [
        "v8",
        "7/9"
    ]
}