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GET /api/patches/103722/?format=api
{ "id": 103722, "url": "http://patches.dpdk.org/api/patches/103722/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211104103457.20264-6-kai.ji@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211104103457.20264-6-kai.ji@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211104103457.20264-6-kai.ji@intel.com", "date": "2021-11-04T10:34:53", "name": "[v8,5/9] compress/qat: define gen specific structs and functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "907dea0408104241352e034d3e03b750d7915333", "submitter": { "id": 2202, "url": "http://patches.dpdk.org/api/people/2202/?format=api", "name": "Ji, Kai", "email": "kai.ji@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211104103457.20264-6-kai.ji@intel.com/mbox/", "series": [ { "id": 20302, "url": "http://patches.dpdk.org/api/series/20302/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20302", "date": "2021-11-04T10:34:48", "name": "drivers/qat: isolate implementations of qat generations", "version": 8, "mbox": "http://patches.dpdk.org/series/20302/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103722/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/103722/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DFC27A0548;\n\tThu, 4 Nov 2021 11:35:41 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 409AD426DC;\n\tThu, 4 Nov 2021 11:35:14 +0100 (CET)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id A667541C26\n for <dev@dpdk.org>; Thu, 4 Nov 2021 11:35:11 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 04 Nov 2021 03:35:11 -0700", "from silpixa00400272.ir.intel.com (HELO\n silpixa00400272.ger.corp.intel.com) ([10.237.223.111])\n by fmsmga008.fm.intel.com with ESMTP; 04 Nov 2021 03:35:09 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10157\"; a=\"212426615\"", "E=Sophos;i=\"5.87,208,1631602800\"; d=\"scan'208\";a=\"212426615\"", "E=Sophos;i=\"5.87,208,1631602800\"; d=\"scan'208\";a=\"542020256\"" ], "X-ExtLoop1": "1", "From": "Kai Ji <kai.ji@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com, Fan Zhang <roy.fan.zhang@intel.com>,\n Adam Dybkowski <adamx.dybkowski@intel.com>,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>, Kai Ji <kai.ji@intel.com>", "Date": "Thu, 4 Nov 2021 10:34:53 +0000", "Message-Id": "<20211104103457.20264-6-kai.ji@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211104103457.20264-1-kai.ji@intel.com>", "References": "<20211027155055.32264-1-kai.ji@intel.com>\n <20211104103457.20264-1-kai.ji@intel.com>", "Subject": "[dpdk-dev] [dpdk-dev v8 5/9] compress/qat: define gen specific\n structs and functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Fan Zhang <roy.fan.zhang@intel.com>\n\nThis patch adds the compression data structure and function\nprototypes for different QAT generations.\n\nSigned-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\nSigned-off-by: Kai Ji <kai.ji@intel.com>\nAcked-by: Ciara Power <ciara.power@intel.com>\n---\n .../common/qat/qat_adf/icp_qat_hw_gen4_comp.h | 195 ++++++++++++\n .../qat/qat_adf/icp_qat_hw_gen4_comp_defs.h | 299 ++++++++++++++++++\n drivers/common/qat/qat_common.h | 4 +-\n drivers/common/qat/qat_device.h | 7 -\n drivers/compress/qat/qat_comp.c | 101 +++---\n drivers/compress/qat/qat_comp.h | 8 +-\n drivers/compress/qat/qat_comp_pmd.c | 159 ++++------\n drivers/compress/qat/qat_comp_pmd.h | 76 +++++\n 8 files changed, 675 insertions(+), 174 deletions(-)\n create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h\n create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h\n\n--\n2.17.1", "diff": "diff --git a/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h\nnew file mode 100644\nindex 0000000000..ec69dc7105\n--- /dev/null\n+++ b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h\n@@ -0,0 +1,195 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#ifndef _ICP_QAT_HW_GEN4_COMP_H_\n+#define _ICP_QAT_HW_GEN4_COMP_H_\n+\n+#include \"icp_qat_fw.h\"\n+#include \"icp_qat_hw_gen4_comp_defs.h\"\n+\n+struct icp_qat_hw_comp_20_config_csr_lower {\n+\ticp_qat_hw_comp_20_extended_delay_match_mode_t edmm;\n+\ticp_qat_hw_comp_20_hw_comp_format_t algo;\n+\ticp_qat_hw_comp_20_search_depth_t sd;\n+\ticp_qat_hw_comp_20_hbs_control_t hbs;\n+\ticp_qat_hw_comp_20_abd_t abd;\n+\ticp_qat_hw_comp_20_lllbd_ctrl_t lllbd;\n+\ticp_qat_hw_comp_20_min_match_control_t mmctrl;\n+\ticp_qat_hw_comp_20_skip_hash_collision_t hash_col;\n+\ticp_qat_hw_comp_20_skip_hash_update_t hash_update;\n+\ticp_qat_hw_comp_20_byte_skip_t skip_ctrl;\n+};\n+\n+static inline uint32_t ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(\n+\t\tstruct icp_qat_hw_comp_20_config_csr_lower csr)\n+{\n+\tuint32_t val32 = 0;\n+\n+\tQAT_FIELD_SET(val32, csr.algo,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.sd,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.edmm,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.hbs,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.lllbd,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.mmctrl,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.hash_col,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.hash_update,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.skip_ctrl,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.abd,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.lllbd,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);\n+\n+\treturn rte_bswap32(val32);\n+}\n+\n+struct icp_qat_hw_comp_20_config_csr_upper {\n+\ticp_qat_hw_comp_20_scb_control_t scb_ctrl;\n+\ticp_qat_hw_comp_20_rmb_control_t rmb_ctrl;\n+\ticp_qat_hw_comp_20_som_control_t som_ctrl;\n+\ticp_qat_hw_comp_20_skip_hash_rd_control_t skip_hash_ctrl;\n+\ticp_qat_hw_comp_20_scb_unload_control_t scb_unload_ctrl;\n+\ticp_qat_hw_comp_20_disable_token_fusion_control_t\n+\t\t\tdisable_token_fusion_ctrl;\n+\ticp_qat_hw_comp_20_lbms_t lbms;\n+\ticp_qat_hw_comp_20_scb_mode_reset_mask_t scb_mode_reset;\n+\tuint16_t lazy;\n+\tuint16_t nice;\n+};\n+\n+static inline uint32_t ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(\n+\t\tstruct icp_qat_hw_comp_20_config_csr_upper csr)\n+{\n+\tuint32_t val32 = 0;\n+\n+\tQAT_FIELD_SET(val32, csr.scb_ctrl,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.rmb_ctrl,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.som_ctrl,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.skip_hash_ctrl,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.scb_unload_ctrl,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.disable_token_fusion_ctrl,\n+\tICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS,\n+\tICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.lbms,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.scb_mode_reset,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.lazy,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.nice,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS,\n+\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK);\n+\n+\treturn rte_bswap32(val32);\n+}\n+\n+struct icp_qat_hw_decomp_20_config_csr_lower {\n+\ticp_qat_hw_decomp_20_hbs_control_t hbs;\n+\ticp_qat_hw_decomp_20_lbms_t lbms;\n+\ticp_qat_hw_decomp_20_hw_comp_format_t algo;\n+\ticp_qat_hw_decomp_20_min_match_control_t mmctrl;\n+\ticp_qat_hw_decomp_20_lz4_block_checksum_present_t lbc;\n+};\n+\n+static inline uint32_t ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(\n+\t\tstruct icp_qat_hw_decomp_20_config_csr_lower csr)\n+{\n+\tuint32_t val32 = 0;\n+\n+\tQAT_FIELD_SET(val32, csr.hbs,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.lbms,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.algo,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.mmctrl,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.lbc,\n+\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS,\n+\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK);\n+\n+\treturn rte_bswap32(val32);\n+}\n+\n+struct icp_qat_hw_decomp_20_config_csr_upper {\n+\ticp_qat_hw_decomp_20_speculative_decoder_control_t sdc;\n+\ticp_qat_hw_decomp_20_mini_cam_control_t mcc;\n+};\n+\n+static inline uint32_t ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(\n+\t\tstruct icp_qat_hw_decomp_20_config_csr_upper csr)\n+{\n+\tuint32_t val32 = 0;\n+\n+\tQAT_FIELD_SET(val32, csr.sdc,\n+\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS,\n+\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK);\n+\n+\tQAT_FIELD_SET(val32, csr.mcc,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS,\n+\t\tICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK);\n+\n+\treturn rte_bswap32(val32);\n+}\n+\n+#endif /* _ICP_QAT_HW_GEN4_COMP_H_ */\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h\nnew file mode 100644\nindex 0000000000..ad02d06b12\n--- /dev/null\n+++ b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h\n@@ -0,0 +1,299 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#ifndef _ICP_QAT_HW_GEN4_COMP_DEFS_H\n+#define _ICP_QAT_HW_GEN4_COMP_DEFS_H\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS\t31\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK\t\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_SCB_CONTROL_ENABLE = 0x0,\n+\tICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE = 0x1,\n+} icp_qat_hw_comp_20_scb_control_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS\t30\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK\t\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL = 0x0,\n+\tICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_FC_ONLY = 0x1,\n+} icp_qat_hw_comp_20_rmb_control_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS\t28\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK\t\t0x3\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE = 0x0,\n+\tICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE = 0x1,\n+\tICP_QAT_HW_COMP_20_SOM_CONTROL_INPUT_CRC = 0x2,\n+\tICP_QAT_HW_COMP_20_SOM_CONTROL_RESERVED_MODE = 0x3,\n+} icp_qat_hw_comp_20_som_control_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS\t27\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK\t\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0,\n+\tICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,\n+} icp_qat_hw_comp_20_skip_hash_rd_control_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS\t26\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD = 0x0,\n+\tICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_NO_UNLOAD = 0x1,\n+} icp_qat_hw_comp_20_scb_unload_control_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS 21\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK 0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE = 0x0,\n+\tICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_DISABLE = 0x1,\n+} icp_qat_hw_comp_20_disable_token_fusion_control_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_DEFAULT_VAL \\\n+\t\tICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS\t19\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK\t\t0x3\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_LBMS_LBMS_64KB = 0x0,\n+\tICP_QAT_HW_COMP_20_LBMS_LBMS_256KB = 0x1,\n+\tICP_QAT_HW_COMP_20_LBMS_LBMS_1MB = 0x2,\n+\tICP_QAT_HW_COMP_20_LBMS_LBMS_4MB = 0x3,\n+} icp_qat_hw_comp_20_lbms_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_LBMS_LBMS_64KB\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS\t18\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK\t\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS = 0x0,\n+\tICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS_AND_HISTORY = 0x1,\n+} icp_qat_hw_comp_20_scb_mode_reset_mask_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS\t9\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK\t0x1ff\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL 258\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS\t0\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK\t0x1ff\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL 259\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS\t14\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK\t\t0x7\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0,\n+} icp_qat_hw_comp_20_hbs_control_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS\t13\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK\t\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_ABD_ABD_ENABLED = 0x0,\n+\tICP_QAT_HW_COMP_20_ABD_ABD_DISABLED = 0x1,\n+} icp_qat_hw_comp_20_abd_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_ABD_ABD_ENABLED\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS\t12\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED = 0x0,\n+\tICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_DISABLED = 0x1,\n+} icp_qat_hw_comp_20_lllbd_ctrl_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS\t8\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK\t\t0xf\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1 = 0x1,\n+\tICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6 = 0x3,\n+\tICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9 = 0x4,\n+} icp_qat_hw_comp_20_search_depth_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS\t5\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK\t0x7\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77 = 0x0,\n+\tICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE = 0x1,\n+\tICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4 = 0x2,\n+\tICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4S = 0x3,\n+} icp_qat_hw_comp_20_hw_comp_format_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS\t4\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_3B = 0x0,\n+\tICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_4B = 0x1,\n+} icp_qat_hw_comp_20_min_match_control_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_3B\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS\t3\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK\t\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW = 0x0,\n+\tICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1,\n+} icp_qat_hw_comp_20_skip_hash_collision_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS\t2\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW = 0x0,\n+\tICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1,\n+} icp_qat_hw_comp_20_skip_hash_update_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS\t1\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN = 0x0,\n+\tICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL = 0x1,\n+} icp_qat_hw_comp_20_byte_skip_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS\t0\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED = 0x0,\n+\tICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED = 0x1,\n+} icp_qat_hw_comp_20_extended_delay_match_mode_t;\n+\n+#define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_DEFAULT_VAL \\\n+\t\tICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS 31\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK 0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE = 0x0,\n+\tICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_DISABLE = 0x1,\n+} icp_qat_hw_decomp_20_speculative_decoder_control_t;\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_DEFAULT_VAL\\\n+\t\tICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS\t30\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_ENABLE = 0x0,\n+\tICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_DISABLE = 0x1,\n+} icp_qat_hw_decomp_20_mini_cam_control_t;\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_ENABLE\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS\t14\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK\t0x7\n+\n+typedef enum {\n+\tICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0,\n+} icp_qat_hw_decomp_20_hbs_control_t;\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS\t8\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK\t0x3\n+\n+typedef enum {\n+\tICP_QAT_HW_DECOMP_20_LBMS_LBMS_64KB = 0x0,\n+\tICP_QAT_HW_DECOMP_20_LBMS_LBMS_256KB = 0x1,\n+\tICP_QAT_HW_DECOMP_20_LBMS_LBMS_1MB = 0x2,\n+\tICP_QAT_HW_DECOMP_20_LBMS_LBMS_4MB = 0x3,\n+} icp_qat_hw_decomp_20_lbms_t;\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_DECOMP_20_LBMS_LBMS_64KB\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS\t5\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK\t0x7\n+\n+typedef enum {\n+\tICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE = 0x1,\n+\tICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4 = 0x2,\n+\tICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4S = 0x3,\n+} icp_qat_hw_decomp_20_hw_comp_format_t;\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS\t4\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK\t\t0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_3B = 0x0,\n+\tICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_4B = 0x1,\n+} icp_qat_hw_decomp_20_min_match_control_t;\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL\t\\\n+\t\tICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_3B\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS 3\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK 0x1\n+\n+typedef enum {\n+\tICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_ABSENT = 0x0,\n+\tICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_PRESENT = 0x1,\n+} icp_qat_hw_decomp_20_lz4_block_checksum_present_t;\n+\n+#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_DEFAULT_VAL \\\n+\tICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_ABSENT\n+\n+#endif /* _ICP_QAT_HW_GEN4_COMP_DEFS_H */\ndiff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h\nindex 1889ec4e88..a7632e31f8 100644\n--- a/drivers/common/qat/qat_common.h\n+++ b/drivers/common/qat/qat_common.h\n@@ -13,9 +13,9 @@\n #define QAT_64_BTYE_ALIGN_MASK (~0x3f)\n\n /* Intel(R) QuickAssist Technology device generation is enumerated\n- * from one according to the generation of the device\n+ * from one according to the generation of the device.\n+ * QAT_GEN* is used as the index to find all devices\n */\n-\n enum qat_device_gen {\n \tQAT_GEN1,\n \tQAT_GEN2,\ndiff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h\nindex 8233cc045d..e7c7e9af95 100644\n--- a/drivers/common/qat/qat_device.h\n+++ b/drivers/common/qat/qat_device.h\n@@ -49,12 +49,6 @@ struct qat_dev_cmd_param {\n \tuint16_t val;\n };\n\n-enum qat_comp_num_im_buffers {\n-\tQAT_NUM_INTERM_BUFS_GEN1 = 12,\n-\tQAT_NUM_INTERM_BUFS_GEN2 = 20,\n-\tQAT_NUM_INTERM_BUFS_GEN3 = 64\n-};\n-\n struct qat_device_info {\n \tconst struct rte_memzone *mz;\n \t/**< mz to store the qat_pci_device so it can be\n@@ -137,7 +131,6 @@ struct qat_pci_device {\n struct qat_gen_hw_data {\n \tenum qat_device_gen dev_gen;\n \tconst struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];\n-\tenum qat_comp_num_im_buffers comp_num_im_bufs_required;\n \tstruct qat_pf2vf_dev *pf2vf_dev;\n };\n\ndiff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c\nindex 7ac25a3b4c..e8f57c3cc4 100644\n--- a/drivers/compress/qat/qat_comp.c\n+++ b/drivers/compress/qat/qat_comp.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2018-2019 Intel Corporation\n+ * Copyright(c) 2018-2021 Intel Corporation\n */\n\n #include <rte_mempool.h>\n@@ -332,7 +332,8 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg,\n \treturn 0;\n }\n\n-static inline uint32_t adf_modulo(uint32_t data, uint32_t modulo_mask)\n+static inline uint32_t\n+adf_modulo(uint32_t data, uint32_t modulo_mask)\n {\n \treturn data & modulo_mask;\n }\n@@ -793,8 +794,9 @@ qat_comp_stream_size(void)\n \treturn RTE_ALIGN_CEIL(sizeof(struct qat_comp_stream), 8);\n }\n\n-static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,\n-\t\t\t\t enum qat_comp_request_type request)\n+static void\n+qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,\n+\t enum qat_comp_request_type request)\n {\n \tif (request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS)\n \t\theader->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;\n@@ -811,16 +813,17 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,\n \t QAT_COMN_CD_FLD_TYPE_16BYTE_DATA, QAT_COMN_PTR_TYPE_FLAT);\n }\n\n-static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,\n-\t\t\tconst struct rte_memzone *interm_buff_mz,\n-\t\t\tconst struct rte_comp_xform *xform,\n-\t\t\tconst struct qat_comp_stream *stream,\n-\t\t\tenum rte_comp_op_type op_type)\n+static int\n+qat_comp_create_templates(struct qat_comp_xform *qat_xform,\n+\t\t\t const struct rte_memzone *interm_buff_mz,\n+\t\t\t const struct rte_comp_xform *xform,\n+\t\t\t const struct qat_comp_stream *stream,\n+\t\t\t enum rte_comp_op_type op_type,\n+\t\t\t enum qat_device_gen qat_dev_gen)\n {\n \tstruct icp_qat_fw_comp_req *comp_req;\n-\tint comp_level, algo;\n \tuint32_t req_par_flags;\n-\tint direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;\n+\tint res;\n\n \tif (unlikely(qat_xform == NULL)) {\n \t\tQAT_LOG(ERR, \"Session was not created for this device\");\n@@ -839,46 +842,17 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,\n \t\t}\n \t}\n\n-\tif (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {\n-\t\tdirection = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;\n-\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;\n+\tif (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS)\n \t\treq_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(\n \t\t\t\tICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,\n \t\t\t\tICP_QAT_FW_COMP_BFINAL,\n \t\t\t\tICP_QAT_FW_COMP_CNV,\n \t\t\t\tICP_QAT_FW_COMP_CNV_RECOVERY);\n-\t} else {\n-\t\tif (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)\n-\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;\n-\t\telse if (xform->compress.level == 1)\n-\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;\n-\t\telse if (xform->compress.level == 2)\n-\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;\n-\t\telse if (xform->compress.level == 3)\n-\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;\n-\t\telse if (xform->compress.level >= 4 &&\n-\t\t\t xform->compress.level <= 9)\n-\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;\n-\t\telse {\n-\t\t\tQAT_LOG(ERR, \"compression level not supported\");\n-\t\t\treturn -EINVAL;\n-\t\t}\n+\telse\n \t\treq_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(\n \t\t\t\tICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,\n \t\t\t\tICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_CNV,\n \t\t\t\tICP_QAT_FW_COMP_CNV_RECOVERY);\n-\t}\n-\n-\tswitch (xform->compress.algo) {\n-\tcase RTE_COMP_ALGO_DEFLATE:\n-\t\talgo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;\n-\t\tbreak;\n-\tcase RTE_COMP_ALGO_LZS:\n-\tdefault:\n-\t\t/* RTE_COMP_NULL */\n-\t\tQAT_LOG(ERR, \"compression algorithm not supported\");\n-\t\treturn -EINVAL;\n-\t}\n\n \tcomp_req = &qat_xform->qat_comp_req_tmpl;\n\n@@ -899,18 +873,10 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,\n \t\tcomp_req->comp_cd_ctrl.comp_state_addr =\n \t\t\t\tstream->state_registers_decomp_phys;\n\n-\t\t/* Enable A, B, C, D, and E (CAMs). */\n+\t\t/* RAM bank flags */\n \t\tcomp_req->comp_cd_ctrl.ram_bank_flags =\n-\t\t\tICP_QAT_FW_COMP_RAM_FLAGS_BUILD(\n-\t\t\t\tICP_QAT_FW_COMP_BANK_DISABLED, /* Bank I */\n-\t\t\t\tICP_QAT_FW_COMP_BANK_DISABLED, /* Bank H */\n-\t\t\t\tICP_QAT_FW_COMP_BANK_DISABLED, /* Bank G */\n-\t\t\t\tICP_QAT_FW_COMP_BANK_DISABLED, /* Bank F */\n-\t\t\t\tICP_QAT_FW_COMP_BANK_ENABLED, /* Bank E */\n-\t\t\t\tICP_QAT_FW_COMP_BANK_ENABLED, /* Bank D */\n-\t\t\t\tICP_QAT_FW_COMP_BANK_ENABLED, /* Bank C */\n-\t\t\t\tICP_QAT_FW_COMP_BANK_ENABLED, /* Bank B */\n-\t\t\t\tICP_QAT_FW_COMP_BANK_ENABLED); /* Bank A */\n+\t\t\t\tqat_comp_gen_dev_ops[qat_dev_gen]\n+\t\t\t\t\t.qat_comp_get_ram_bank_flags();\n\n \t\tcomp_req->comp_cd_ctrl.ram_banks_addr =\n \t\t\t\tstream->inflate_context_phys;\n@@ -924,13 +890,11 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,\n \t\t\tICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);\n \t}\n\n-\tcomp_req->cd_pars.sl.comp_slice_cfg_word[0] =\n-\t ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(\n-\t\tdirection,\n-\t\t/* In CPM 1.6 only valid mode ! */\n-\t\tICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, algo,\n-\t\t/* Translate level to depth */\n-\t\tcomp_level, ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);\n+\tres = qat_comp_gen_dev_ops[qat_dev_gen].qat_comp_set_slice_cfg_word(\n+\t\t\tqat_xform, xform, op_type,\n+\t\t\tcomp_req->cd_pars.sl.comp_slice_cfg_word);\n+\tif (res)\n+\t\treturn res;\n\n \tcomp_req->comp_pars.initial_adler = 1;\n \tcomp_req->comp_pars.initial_crc32 = 0;\n@@ -958,7 +922,8 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,\n \t\t\t\tICP_QAT_FW_SLICE_XLAT);\n\n \t\tcomp_req->u1.xlt_pars.inter_buff_ptr =\n-\t\t\t\tinterm_buff_mz->iova;\n+\t\t\t\t(qat_comp_get_num_im_bufs_required(qat_dev_gen)\n+\t\t\t\t\t== 0) ? 0 : interm_buff_mz->iova;\n \t}\n\n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n@@ -991,6 +956,8 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,\n \t\t\t void **private_xform)\n {\n \tstruct qat_comp_dev_private *qat = dev->data->dev_private;\n+\tenum qat_device_gen qat_dev_gen = qat->qat_dev->qat_dev_gen;\n+\tunsigned int im_bufs = qat_comp_get_num_im_bufs_required(qat_dev_gen);\n\n \tif (unlikely(private_xform == NULL)) {\n \t\tQAT_LOG(ERR, \"QAT: private_xform parameter is NULL\");\n@@ -1012,7 +979,8 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,\n\n \t\tif (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||\n \t\t ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)\n-\t\t\t\t && qat->interm_buff_mz == NULL))\n+\t\t\t\t && qat->interm_buff_mz == NULL\n+\t\t\t\t && im_bufs > 0))\n \t\t\tqat_xform->qat_comp_request_type =\n \t\t\t\t\tQAT_COMP_REQUEST_FIXED_COMP_STATELESS;\n\n@@ -1020,7 +988,8 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,\n \t\t\t\tRTE_COMP_HUFFMAN_DYNAMIC ||\n \t\t\t\txform->compress.deflate.huffman ==\n \t\t\t\t\t\tRTE_COMP_HUFFMAN_DEFAULT) &&\n-\t\t\t\tqat->interm_buff_mz != NULL)\n+\t\t\t\t(qat->interm_buff_mz != NULL ||\n+\t\t\t\t\t\tim_bufs == 0))\n\n \t\t\tqat_xform->qat_comp_request_type =\n \t\t\t\t\tQAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;\n@@ -1039,7 +1008,8 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,\n \t}\n\n \tif (qat_comp_create_templates(qat_xform, qat->interm_buff_mz, xform,\n-\t\t\t\t NULL, RTE_COMP_OP_STATELESS)) {\n+\t\t\t\t NULL, RTE_COMP_OP_STATELESS,\n+\t\t\t\t qat_dev_gen)) {\n \t\tQAT_LOG(ERR, \"QAT: Problem with setting compression\");\n \t\treturn -EINVAL;\n \t}\n@@ -1138,7 +1108,8 @@ qat_comp_stream_create(struct rte_compressdev *dev,\n \tptr->qat_xform.checksum_type = xform->decompress.chksum;\n\n \tif (qat_comp_create_templates(&ptr->qat_xform, qat->interm_buff_mz,\n-\t\t\t\t xform, ptr, RTE_COMP_OP_STATEFUL)) {\n+\t\t\t\t xform, ptr, RTE_COMP_OP_STATEFUL,\n+\t\t\t\t qat->qat_dev->qat_dev_gen)) {\n \t\tQAT_LOG(ERR, \"QAT: problem with creating descriptor template for stream\");\n \t\trte_mempool_put(qat->streampool, *stream);\n \t\t*stream = NULL;\ndiff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h\nindex 0444b50a1e..da7b9a6eec 100644\n--- a/drivers/compress/qat/qat_comp.h\n+++ b/drivers/compress/qat/qat_comp.h\n@@ -28,14 +28,16 @@\n #define QAT_MIN_OUT_BUF_SIZE 46\n\n /* maximum size of the state registers */\n-#define QAT_STATE_REGISTERS_MAX_SIZE 64\n+#define QAT_STATE_REGISTERS_MAX_SIZE 256 /* 64 bytes for GEN1-3, 256 for GEN4 */\n\n /* decompressor context size */\n #define QAT_INFLATE_CONTEXT_SIZE_GEN1 36864\n #define QAT_INFLATE_CONTEXT_SIZE_GEN2 34032\n #define QAT_INFLATE_CONTEXT_SIZE_GEN3 34032\n-#define QAT_INFLATE_CONTEXT_SIZE RTE_MAX(RTE_MAX(QAT_INFLATE_CONTEXT_SIZE_GEN1,\\\n-\t\tQAT_INFLATE_CONTEXT_SIZE_GEN2), QAT_INFLATE_CONTEXT_SIZE_GEN3)\n+#define QAT_INFLATE_CONTEXT_SIZE_GEN4 36864\n+#define QAT_INFLATE_CONTEXT_SIZE RTE_MAX(RTE_MAX(RTE_MAX(\\\n+\t\tQAT_INFLATE_CONTEXT_SIZE_GEN1, QAT_INFLATE_CONTEXT_SIZE_GEN2), \\\n+\t\tQAT_INFLATE_CONTEXT_SIZE_GEN3), QAT_INFLATE_CONTEXT_SIZE_GEN4)\n\n enum qat_comp_request_type {\n \tQAT_COMP_REQUEST_FIXED_COMP_STATELESS,\ndiff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c\nindex caac7839e9..9b24d46e97 100644\n--- a/drivers/compress/qat/qat_comp_pmd.c\n+++ b/drivers/compress/qat/qat_comp_pmd.c\n@@ -9,30 +9,29 @@\n\n #define QAT_PMD_COMP_SGL_DEF_SEGMENTS 16\n\n+struct qat_comp_gen_dev_ops qat_comp_gen_dev_ops[QAT_N_GENS];\n+\n struct stream_create_info {\n \tstruct qat_comp_dev_private *comp_dev;\n \tint socket_id;\n \tint error;\n };\n\n-static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {\n-\t{/* COMPRESSION - deflate */\n-\t .algo = RTE_COMP_ALGO_DEFLATE,\n-\t .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |\n-\t\t\t\tRTE_COMP_FF_CRC32_CHECKSUM |\n-\t\t\t\tRTE_COMP_FF_ADLER32_CHECKSUM |\n-\t\t\t\tRTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n-\t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n-\t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED |\n-\t\t\t\tRTE_COMP_FF_HUFFMAN_DYNAMIC |\n-\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_SGL_OUT |\n-\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_LB_OUT |\n-\t\t\t\tRTE_COMP_FF_OOP_LB_IN_SGL_OUT |\n-\t\t\t\tRTE_COMP_FF_STATEFUL_DECOMPRESSION,\n-\t .window_size = {.min = 15, .max = 15, .increment = 0} },\n-\t{RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };\n+static struct\n+qat_comp_capabilities_info qat_comp_get_capa_info(\n+\t\tenum qat_device_gen qat_dev_gen, struct qat_pci_device *qat_dev)\n+{\n+\tstruct qat_comp_capabilities_info ret = { .data = NULL, .size = 0 };\n\n-static void\n+\tif (qat_dev_gen >= QAT_N_GENS)\n+\t\treturn ret;\n+\tRTE_FUNC_PTR_OR_ERR_RET(qat_comp_gen_dev_ops[qat_dev_gen]\n+\t\t\t.qat_comp_get_capabilities, ret);\n+\treturn qat_comp_gen_dev_ops[qat_dev_gen]\n+\t\t\t.qat_comp_get_capabilities(qat_dev);\n+}\n+\n+void\n qat_comp_stats_get(struct rte_compressdev *dev,\n \t\tstruct rte_compressdev_stats *stats)\n {\n@@ -52,7 +51,7 @@ qat_comp_stats_get(struct rte_compressdev *dev,\n \tstats->dequeue_err_count = qat_stats.dequeue_err_count;\n }\n\n-static void\n+void\n qat_comp_stats_reset(struct rte_compressdev *dev)\n {\n \tstruct qat_comp_dev_private *qat_priv;\n@@ -67,7 +66,7 @@ qat_comp_stats_reset(struct rte_compressdev *dev)\n\n }\n\n-static int\n+int\n qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)\n {\n \tstruct qat_comp_dev_private *qat_private = dev->data->dev_private;\n@@ -95,23 +94,18 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)\n \t\t\t&(dev->data->queue_pairs[queue_pair_id]));\n }\n\n-static int\n+int\n qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n-\t\t uint32_t max_inflight_ops, int socket_id)\n+\t\tuint32_t max_inflight_ops, int socket_id)\n {\n-\tstruct qat_qp *qp;\n-\tint ret = 0;\n-\tuint32_t i;\n-\tstruct qat_qp_config qat_qp_conf;\n-\n+\tstruct qat_qp_config qat_qp_conf = {0};\n \tstruct qat_qp **qp_addr =\n \t\t\t(struct qat_qp **)&(dev->data->queue_pairs[qp_id]);\n \tstruct qat_comp_dev_private *qat_private = dev->data->dev_private;\n \tstruct qat_pci_device *qat_dev = qat_private->qat_dev;\n-\tconst struct qat_qp_hw_data *comp_hw_qps =\n-\t\t\tqat_gen_config[qat_private->qat_dev->qat_dev_gen]\n-\t\t\t\t .qp_hw_data[QAT_SERVICE_COMPRESSION];\n-\tconst struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;\n+\tstruct qat_qp *qp;\n+\tuint32_t i;\n+\tint ret;\n\n \t/* If qp is already in use free ring memory and qp metadata. */\n \tif (*qp_addr != NULL) {\n@@ -125,7 +119,13 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\treturn -EINVAL;\n \t}\n\n-\tqat_qp_conf.hw = qp_hw_data;\n+\n+\tqat_qp_conf.hw = qat_qp_get_hw_data(qat_dev, QAT_SERVICE_COMPRESSION,\n+\t\t\tqp_id);\n+\tif (qat_qp_conf.hw == NULL) {\n+\t\tQAT_LOG(ERR, \"qp_id %u invalid for this device\", qp_id);\n+\t\treturn -EINVAL;\n+\t}\n \tqat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);\n \tqat_qp_conf.nb_descriptors = max_inflight_ops;\n \tqat_qp_conf.socket_id = socket_id;\n@@ -134,7 +134,6 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \tret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);\n \tif (ret != 0)\n \t\treturn ret;\n-\n \t/* store a link to the qp in the qat_pci_device */\n \tqat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]\n \t\t\t\t\t\t\t\t= *qp_addr;\n@@ -189,7 +188,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n\n\n #define QAT_IM_BUFFER_DEBUG 0\n-static const struct rte_memzone *\n+const struct rte_memzone *\n qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n \t\t\t uint32_t buff_size)\n {\n@@ -202,8 +201,8 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n \tuint32_t full_size;\n \tuint32_t offset_of_flat_buffs;\n \tint i;\n-\tint num_im_sgls = qat_gen_config[\n-\t\tcomp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;\n+\tint num_im_sgls = qat_comp_get_num_im_bufs_required(\n+\t\t\tcomp_dev->qat_dev->qat_dev_gen);\n\n \tQAT_LOG(DEBUG, \"QAT COMP device %s needs %d sgls\",\n \t\t\t\tcomp_dev->qat_dev->name, num_im_sgls);\n@@ -480,8 +479,8 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)\n \t/* Free intermediate buffers */\n \tif (comp_dev->interm_buff_mz) {\n \t\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n-\t\tint i = qat_gen_config[\n-\t\t comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;\n+\t\tint i = qat_comp_get_num_im_bufs_required(\n+\t\t\t\tcomp_dev->qat_dev->qat_dev_gen);\n\n \t\twhile (--i >= 0) {\n \t\t\tsnprintf(mz_name, RTE_MEMZONE_NAMESIZE,\n@@ -509,28 +508,13 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)\n \t}\n }\n\n-static int\n+int\n qat_comp_dev_config(struct rte_compressdev *dev,\n \t\tstruct rte_compressdev_config *config)\n {\n \tstruct qat_comp_dev_private *comp_dev = dev->data->dev_private;\n \tint ret = 0;\n\n-\tif (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {\n-\t\tQAT_LOG(WARNING,\n-\t\t\t\"RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so\"\n-\t\t\t\" QAT device can't be used for Dynamic Deflate. \"\n-\t\t\t\"Did you really intend to do this?\");\n-\t} else {\n-\t\tcomp_dev->interm_buff_mz =\n-\t\t\t\tqat_comp_setup_inter_buffers(comp_dev,\n-\t\t\t\t\tRTE_PMD_QAT_COMP_IM_BUFFER_SIZE);\n-\t\tif (comp_dev->interm_buff_mz == NULL) {\n-\t\t\tret = -ENOMEM;\n-\t\t\tgoto error_out;\n-\t\t}\n-\t}\n-\n \tif (config->max_nb_priv_xforms) {\n \t\tcomp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,\n \t\t\t\t\t config, config->max_nb_priv_xforms);\n@@ -558,19 +542,19 @@ qat_comp_dev_config(struct rte_compressdev *dev,\n \treturn ret;\n }\n\n-static int\n+int\n qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)\n {\n \treturn 0;\n }\n\n-static void\n+void\n qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)\n {\n\n }\n\n-static int\n+int\n qat_comp_dev_close(struct rte_compressdev *dev)\n {\n \tint i;\n@@ -588,8 +572,7 @@ qat_comp_dev_close(struct rte_compressdev *dev)\n \treturn ret;\n }\n\n-\n-static void\n+void\n qat_comp_dev_info_get(struct rte_compressdev *dev,\n \t\t\tstruct rte_compressdev_info *info)\n {\n@@ -662,27 +645,6 @@ qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops,\n \treturn ret;\n }\n\n-static struct rte_compressdev_ops compress_qat_ops = {\n-\n-\t/* Device related operations */\n-\t.dev_configure\t\t= qat_comp_dev_config,\n-\t.dev_start\t\t= qat_comp_dev_start,\n-\t.dev_stop\t\t= qat_comp_dev_stop,\n-\t.dev_close\t\t= qat_comp_dev_close,\n-\t.dev_infos_get\t\t= qat_comp_dev_info_get,\n-\n-\t.stats_get\t\t= qat_comp_stats_get,\n-\t.stats_reset\t\t= qat_comp_stats_reset,\n-\t.queue_pair_setup\t= qat_comp_qp_setup,\n-\t.queue_pair_release\t= qat_comp_qp_release,\n-\n-\t/* Compression related operations */\n-\t.private_xform_create\t= qat_comp_private_xform_create,\n-\t.private_xform_free\t= qat_comp_private_xform_free,\n-\t.stream_create\t\t= qat_comp_stream_create,\n-\t.stream_free\t\t= qat_comp_stream_free\n-};\n-\n /* An rte_driver is needed in the registration of the device with compressdev.\n * The actual qat pci's rte_driver can't be used as its name represents\n * the whole pci device with all services. Think of this as a holder for a name\n@@ -693,6 +655,7 @@ static const struct rte_driver compdev_qat_driver = {\n \t.name = qat_comp_drv_name,\n \t.alias = qat_comp_drv_name\n };\n+\n int\n qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,\n \t\tstruct qat_dev_cmd_param *qat_dev_cmd_param)\n@@ -708,17 +671,21 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,\n \tchar capa_memz_name[RTE_COMPRESSDEV_NAME_MAX_LEN];\n \tstruct rte_compressdev *compressdev;\n \tstruct qat_comp_dev_private *comp_dev;\n+\tstruct qat_comp_capabilities_info capabilities_info;\n \tconst struct rte_compressdev_capabilities *capabilities;\n+\tconst struct qat_comp_gen_dev_ops *qat_comp_gen_ops =\n+\t\t\t&qat_comp_gen_dev_ops[qat_pci_dev->qat_dev_gen];\n \tuint64_t capa_size;\n\n-\tif (qat_pci_dev->qat_dev_gen == QAT_GEN4) {\n-\t\tQAT_LOG(ERR, \"Compression PMD not supported on QAT 4xxx\");\n-\t\treturn -EFAULT;\n-\t}\n \tsnprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, \"%s_%s\",\n \t\t\tqat_pci_dev->name, \"comp\");\n \tQAT_LOG(DEBUG, \"Creating QAT COMP device %s\", name);\n\n+\tif (qat_comp_gen_ops->compressdev_ops == NULL) {\n+\t\tQAT_LOG(DEBUG, \"Device %s does not support compression\", name);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \t/* Populate subset device to use in compressdev device creation */\n \tqat_dev_instance->comp_rte_dev.driver = &compdev_qat_driver;\n \tqat_dev_instance->comp_rte_dev.numa_node =\n@@ -733,13 +700,13 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,\n \tif (compressdev == NULL)\n \t\treturn -ENODEV;\n\n-\tcompressdev->dev_ops = &compress_qat_ops;\n+\tcompressdev->dev_ops = qat_comp_gen_ops->compressdev_ops;\n\n \tcompressdev->enqueue_burst = (compressdev_enqueue_pkt_burst_t)\n \t\t\tqat_enqueue_comp_op_burst;\n \tcompressdev->dequeue_burst = qat_comp_pmd_dequeue_first_op_burst;\n-\n-\tcompressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n+\tcompressdev->feature_flags =\n+\t\t\tqat_comp_gen_ops->qat_comp_get_feature_flags();\n\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n@@ -752,22 +719,20 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,\n \tcomp_dev->qat_dev = qat_pci_dev;\n \tcomp_dev->compressdev = compressdev;\n\n-\tswitch (qat_pci_dev->qat_dev_gen) {\n-\tcase QAT_GEN1:\n-\tcase QAT_GEN2:\n-\tcase QAT_GEN3:\n-\t\tcapabilities = qat_comp_gen_capabilities;\n-\t\tcapa_size = sizeof(qat_comp_gen_capabilities);\n-\t\tbreak;\n-\tdefault:\n-\t\tcapabilities = qat_comp_gen_capabilities;\n-\t\tcapa_size = sizeof(qat_comp_gen_capabilities);\n+\tcapabilities_info = qat_comp_get_capa_info(qat_pci_dev->qat_dev_gen,\n+\t\t\tqat_pci_dev);\n+\n+\tif (capabilities_info.data == NULL) {\n \t\tQAT_LOG(DEBUG,\n \t\t\t\"QAT gen %d capabilities unknown, default to GEN1\",\n \t\t\t\t\tqat_pci_dev->qat_dev_gen);\n-\t\tbreak;\n+\t\tcapabilities_info = qat_comp_get_capa_info(QAT_GEN1,\n+\t\t\t\tqat_pci_dev);\n \t}\n\n+\tcapabilities = capabilities_info.data;\n+\tcapa_size = capabilities_info.size;\n+\n \tcomp_dev->capa_mz = rte_memzone_lookup(capa_memz_name);\n \tif (comp_dev->capa_mz == NULL) {\n \t\tcomp_dev->capa_mz = rte_memzone_reserve(capa_memz_name,\ndiff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h\nindex 252b4b24e3..86317a513c 100644\n--- a/drivers/compress/qat/qat_comp_pmd.h\n+++ b/drivers/compress/qat/qat_comp_pmd.h\n@@ -11,10 +11,44 @@\n #include <rte_compressdev_pmd.h>\n\n #include \"qat_device.h\"\n+#include \"qat_comp.h\"\n\n /**< Intel(R) QAT Compression PMD driver name */\n #define COMPRESSDEV_NAME_QAT_PMD\tcompress_qat\n\n+/* Private data structure for a QAT compression device capability. */\n+struct qat_comp_capabilities_info {\n+\tconst struct rte_compressdev_capabilities *data;\n+\tuint64_t size;\n+};\n+\n+/**\n+ * Function prototypes for GENx specific compress device operations.\n+ **/\n+typedef struct qat_comp_capabilities_info (*get_comp_capabilities_info_t)\n+\t\t(struct qat_pci_device *qat_dev);\n+\n+typedef uint16_t (*get_comp_ram_bank_flags_t)(void);\n+\n+typedef int (*set_comp_slice_cfg_word_t)(struct qat_comp_xform *qat_xform,\n+\t\tconst struct rte_comp_xform *xform,\n+\t\tenum rte_comp_op_type op_type, uint32_t *comp_slice_cfg_word);\n+\n+typedef unsigned int (*get_comp_num_im_bufs_required_t)(void);\n+\n+typedef uint64_t (*get_comp_feature_flags_t)(void);\n+\n+struct qat_comp_gen_dev_ops {\n+\tstruct rte_compressdev_ops *compressdev_ops;\n+\tget_comp_feature_flags_t qat_comp_get_feature_flags;\n+\tget_comp_capabilities_info_t qat_comp_get_capabilities;\n+\tget_comp_ram_bank_flags_t qat_comp_get_ram_bank_flags;\n+\tset_comp_slice_cfg_word_t qat_comp_set_slice_cfg_word;\n+\tget_comp_num_im_bufs_required_t qat_comp_get_num_im_bufs_required;\n+};\n+\n+extern struct qat_comp_gen_dev_ops qat_comp_gen_dev_ops[];\n+\n /** private data structure for a QAT compression device.\n * This QAT device is a device offering only a compression service,\n * there can be one of these on each qat_pci_device (VF).\n@@ -37,6 +71,41 @@ struct qat_comp_dev_private {\n \tuint16_t min_enq_burst_threshold;\n };\n\n+int\n+qat_comp_dev_config(struct rte_compressdev *dev,\n+\t\tstruct rte_compressdev_config *config);\n+\n+int\n+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);\n+\n+void\n+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);\n+\n+int\n+qat_comp_dev_close(struct rte_compressdev *dev);\n+\n+void\n+qat_comp_dev_info_get(struct rte_compressdev *dev,\n+\t\tstruct rte_compressdev_info *info);\n+\n+void\n+qat_comp_stats_get(struct rte_compressdev *dev,\n+\t\tstruct rte_compressdev_stats *stats);\n+\n+void\n+qat_comp_stats_reset(struct rte_compressdev *dev);\n+\n+int\n+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);\n+\n+int\n+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n+\t\tuint32_t max_inflight_ops, int socket_id);\n+\n+const struct rte_memzone *\n+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n+\t\tuint32_t buff_size);\n+\n int\n qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,\n \t\tstruct qat_dev_cmd_param *qat_dev_cmd_param);\n@@ -44,5 +113,12 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,\n int\n qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev);\n\n+\n+static __rte_always_inline unsigned int\n+qat_comp_get_num_im_bufs_required(enum qat_device_gen gen)\n+{\n+\treturn (*qat_comp_gen_dev_ops[gen].qat_comp_get_num_im_bufs_required)();\n+}\n+\n #endif\n #endif /* _QAT_COMP_PMD_H_ */\n", "prefixes": [ "v8", "5/9" ] }