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GET /api/patches/103623/?format=api
{ "id": 103623, "url": "http://patches.dpdk.org/api/patches/103623/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211103075838.1486056-15-xuemingl@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211103075838.1486056-15-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211103075838.1486056-15-xuemingl@nvidia.com", "date": "2021-11-03T07:58:38", "name": "[v3,14/14] net/mlx5: add shared Rx queue port datapath support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bb729055812722f84b34f4b641c6cad46f359d17", "submitter": { "id": 1904, "url": "http://patches.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211103075838.1486056-15-xuemingl@nvidia.com/mbox/", "series": [ { "id": 20258, "url": "http://patches.dpdk.org/api/series/20258/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20258", "date": "2021-11-03T07:58:24", "name": "net/mlx5: support shared Rx queue", "version": 3, "mbox": "http://patches.dpdk.org/series/20258/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103623/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/103623/checks/", "tags": {}, "related": [], "headers": { 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David\n Christensen <drc@linux.vnet.ibm.com>, Ruifeng Wang <ruifeng.wang@arm.com>,\n Bruce Richardson <bruce.richardson@intel.com>, Konstantin Ananyev\n <konstantin.ananyev@intel.com>", "Date": "Wed, 3 Nov 2021 15:58:38 +0800", "Message-ID": "<20211103075838.1486056-15-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20211103075838.1486056-1-xuemingl@nvidia.com>", "References": "<20210727034204.20649-1-xuemingl@nvidia.com>\n <20211103075838.1486056-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "c1290b31-4b1a-4012-584b-08d99ea021af", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB2530:", "X-Microsoft-Antispam-PRVS": "\n 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SFS:(4636009)(36840700001)(46966006)(36756003)(7696005)(55016002)(70586007)(2616005)(26005)(7636003)(83380400001)(36860700001)(8936002)(336012)(1076003)(2906002)(47076005)(36906005)(70206006)(54906003)(82310400003)(426003)(316002)(4326008)(6286002)(6666004)(356005)(16526019)(186003)(508600001)(8676002)(86362001)(6916009)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Nov 2021 08:01:24.5591 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c1290b31-4b1a-4012-584b-08d99ea021af", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT027.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB2530", "Subject": "[dpdk-dev] [PATCH v3 14/14] net/mlx5: add shared Rx queue port\n datapath support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n\nWhen receive packet, mlx5 PMD saves mbuf port number from\nRxQ data.\n\nTo support shared RxQ, save port number into RQ context as user index.\nReceived packet resolve port number from CQE user index which derived\nfrom RQ context.\n\nLegacy Verbs API doesn't support RQ user index setting, still read from\nRxQ port number.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_devx.c | 1 +\n drivers/net/mlx5/mlx5_rx.c | 1 +\n drivers/net/mlx5/mlx5_rxq.c | 3 ++-\n drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 6 ++++++\n drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 12 +++++++++++-\n drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 8 +++++++-\n 6 files changed, 28 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex d3d189ab7f2..a9f9f4af700 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -277,6 +277,7 @@ mlx5_rxq_create_devx_rq_resources(struct mlx5_rxq_priv *rxq)\n \t\t\t\t\t\tMLX5_WQ_END_PAD_MODE_NONE;\n \trq_attr.wq_attr.pd = cdev->pdn;\n \trq_attr.counter_set_id = priv->counter_set_id;\n+\trq_attr.user_index = rte_cpu_to_be_16(priv->dev_data->port_id);\n \tif (rxq_data->shared) /* Create RMP based RQ. */\n \t\trxq->devx_rq.rmp = &rxq_ctrl->obj->devx_rmp;\n \t/* Create RQ using DevX API. */\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex 1ffa1b95b88..4d85f64accd 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -709,6 +709,7 @@ rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,\n {\n \t/* Update packet information. */\n \tpkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe, mcqe);\n+\tpkt->port = unlikely(rxq->shared) ? cqe->user_index_low : rxq->port_id;\n \n \tif (rxq->rss_hash) {\n \t\tuint32_t rss_hash_res = 0;\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 0f1f4660bc7..6c715c0803e 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -186,7 +186,8 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n \t\tmbuf_init->data_off = RTE_PKTMBUF_HEADROOM;\n \t\trte_mbuf_refcnt_set(mbuf_init, 1);\n \t\tmbuf_init->nb_segs = 1;\n-\t\tmbuf_init->port = rxq->port_id;\n+\t\t/* For shared queues port is provided in CQE */\n+\t\tmbuf_init->port = rxq->shared ? 0 : rxq->port_id;\n \t\tif (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)\n \t\t\tmbuf_init->ol_flags = RTE_MBUF_F_EXTERNAL;\n \t\t/*\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\nindex 1d00c1c43d1..423e229508c 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n@@ -1189,6 +1189,12 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \n \t\t/* D.5 fill in mbuf - rearm_data and packet_type. */\n \t\trxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);\n+\t\tif (unlikely(rxq->shared)) {\n+\t\t\tpkts[pos]->port = cq[pos].user_index_low;\n+\t\t\tpkts[pos + p1]->port = cq[pos + p1].user_index_low;\n+\t\t\tpkts[pos + p2]->port = cq[pos + p2].user_index_low;\n+\t\t\tpkts[pos + p3]->port = cq[pos + p3].user_index_low;\n+\t\t}\n \t\tif (rxq->hw_timestamp) {\n \t\t\tint offset = rxq->timestamp_offset;\n \t\t\tif (rxq->rt_timestamp) {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\nindex aa36df29a09..b1d16baa619 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n@@ -787,7 +787,17 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \t\t/* C.4 fill in mbuf - rearm_data and packet_type. */\n \t\trxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,\n \t\t\t\t\t opcode, &elts[pos]);\n-\t\tif (rxq->hw_timestamp) {\n+\t\tif (unlikely(rxq->shared)) {\n+\t\t\telts[pos]->port = container_of(p0, struct mlx5_cqe,\n+\t\t\t\t\t pkt_info)->user_index_low;\n+\t\t\telts[pos + 1]->port = container_of(p1, struct mlx5_cqe,\n+\t\t\t\t\t pkt_info)->user_index_low;\n+\t\t\telts[pos + 2]->port = container_of(p2, struct mlx5_cqe,\n+\t\t\t\t\t pkt_info)->user_index_low;\n+\t\t\telts[pos + 3]->port = container_of(p3, struct mlx5_cqe,\n+\t\t\t\t\t pkt_info)->user_index_low;\n+\t\t}\n+\t\tif (unlikely(rxq->hw_timestamp)) {\n \t\t\tint offset = rxq->timestamp_offset;\n \t\t\tif (rxq->rt_timestamp) {\n \t\t\t\tstruct mlx5_dev_ctx_shared *sh = rxq->sh;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\nindex b0fc29d7b9e..f3d838389e2 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n@@ -736,7 +736,13 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \t\t*err |= _mm_cvtsi128_si64(opcode);\n \t\t/* D.5 fill in mbuf - rearm_data and packet_type. */\n \t\trxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);\n-\t\tif (rxq->hw_timestamp) {\n+\t\tif (unlikely(rxq->shared)) {\n+\t\t\tpkts[pos]->port = cq[pos].user_index_low;\n+\t\t\tpkts[pos + p1]->port = cq[pos + p1].user_index_low;\n+\t\t\tpkts[pos + p2]->port = cq[pos + p2].user_index_low;\n+\t\t\tpkts[pos + p3]->port = cq[pos + p3].user_index_low;\n+\t\t}\n+\t\tif (unlikely(rxq->hw_timestamp)) {\n \t\t\tint offset = rxq->timestamp_offset;\n \t\t\tif (rxq->rt_timestamp) {\n \t\t\t\tstruct mlx5_dev_ctx_shared *sh = rxq->sh;\n", "prefixes": [ "v3", "14/14" ] }