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GET /api/patches/103611/?format=api
{ "id": 103611, "url": "http://patches.dpdk.org/api/patches/103611/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211103075838.1486056-4-xuemingl@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211103075838.1486056-4-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211103075838.1486056-4-xuemingl@nvidia.com", "date": "2021-11-03T07:58:27", "name": "[v3,03/14] common/mlx5: adds basic receive memory pool support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "43b9922a389c6dd7c4796e57781226f3516abfcd", "submitter": { "id": 1904, "url": "http://patches.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211103075838.1486056-4-xuemingl@nvidia.com/mbox/", "series": [ { "id": 20258, "url": "http://patches.dpdk.org/api/series/20258/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20258", "date": "2021-11-03T07:58:24", "name": "net/mlx5: support shared Rx queue", "version": 3, "mbox": "http://patches.dpdk.org/series/20258/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103611/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/103611/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 259B9A0C53;\n\tWed, 3 Nov 2021 08:59:32 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 07C9A41155;\n\tWed, 3 Nov 2021 08:59:19 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2066.outbound.protection.outlook.com [40.107.236.66])\n by mails.dpdk.org (Postfix) with ESMTP id A49CD4115C\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Xueming Li <xuemingl@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<xuemingl@nvidia.com>, Lior Margalit <lmargalit@nvidia.com>, Matan Azrad\n <matan@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, \"Ray\n Kinsella\" <mdr@ashroe.eu>", "Date": "Wed, 3 Nov 2021 15:58:27 +0800", "Message-ID": "<20211103075838.1486056-4-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20211103075838.1486056-1-xuemingl@nvidia.com>", "References": "<20210727034204.20649-1-xuemingl@nvidia.com>\n <20211103075838.1486056-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "5a86c148-ece8-4a35-80f8-08d99e9fd434", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3115:", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB3115EE7ED243463D6DF6E25AA18C9@DM6PR12MB3115.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8882;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n KM6jkAwEGcaPmkMXISWd9YLOz/nPEWOBFpEMC0f6HzRTF2/ROvZKYZqn7ler84R0bfdt3yx28gJIoT9EEJlrag4LLHWeM14T2YCMiRM+I0V44v6w8S+QxBixYCjYrxh4i07Px73vPhibDdI5k4uoKdvvIQB7tdiQ3OKSxtbA36Ha1twaB2jEIkLtTWk4bfcI8up/bsMUBzR+T5J/Gr5YMoKi4HNOycMtHCYdzhwM42C880cqIiCPlhlHQ86G+CsU9goSoH5t287YRQi13t6yMu2+V+e5GmbvF8CWg2IG6kAFgYv563H95NnKTsZLjK6egCZHjO1Q1sHTKAe05Y4IEanwSjpk26rdVrUB4mmZLHqHntYim1jQ0SNCsd6B6p48BVQDqiqjsOF7oemi+nB+b+1tPcMBirZRnTHe/ECwLUEEGI2aZf/+sjO4iFY24zGJXTkld5B9De4jebWR1R0zGIeD33xZGuxdIh18/FHKYKVROaMBgey10QlnPC9z+rsEJdbBUiDyLmrWRtHrzwqf+m9RvqjaGvLgYfk3RL8V4NaxoSe0GvrU3eCz+8KOFOi/x/+1sq4vlNNjl4EYqoi3ojiPwg0z5W9Pvei2fVnsiKKITH3AMvJB/NFSck9cnfBVaJhMJbAkwd6XLJ9sg84jGs/5jghzPwasIy5XBXICpfCG1vbBXksZjzcr6iNe0OUA1U7vB4NGztwiT9hhQMbaIA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(70586007)(54906003)(83380400001)(316002)(47076005)(426003)(7696005)(36860700001)(336012)(6286002)(4326008)(86362001)(26005)(7636003)(8936002)(5660300002)(508600001)(36756003)(82310400003)(2906002)(6916009)(8676002)(186003)(16526019)(55016002)(70206006)(1076003)(356005)(6666004)(2616005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Nov 2021 07:59:14.5715 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5a86c148-ece8-4a35-80f8-08d99e9fd434", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3115", "Subject": "[dpdk-dev] [PATCH v3 03/14] common/mlx5: adds basic receive memory\n pool support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The hardware Receive Memory Pool (RMP) object holds the destination for\nincoming packets/messages that are routed to the RMP through RQs. RMP\nenables sharing of memory across multiple Receive Queues. Multiple\nReceive Queues can be attached to the same RMP and consume memory\nfrom that shared poll. When using RMPs, completions are reported to the\nCQ pointed to by the RQ, and this Completion Queue can be shared as\nwell.\n\nThis patch adds DevX supports of PRM RMP object.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 52 +++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 16 ++++++\n drivers/common/mlx5/mlx5_prm.h | 85 +++++++++++++++++++++++++++-\n drivers/common/mlx5/version.map | 1 +\n 4 files changed, 153 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex fb7c8e986f8..119641df470 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -766,6 +766,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\tMLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);\n \tattr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t flow_counters_dump);\n+\tattr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);\n+\tattr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);\n \tattr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t log_max_rqt_size);\n \tattr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);\n@@ -1277,6 +1279,56 @@ mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,\n }\n \n /**\n+ * Create RMP using DevX API.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param [in] rmp_attr\n+ * Pointer to create RMP attributes structure.\n+ * @param [in] socket\n+ * CPU socket ID for allocations.\n+ *\n+ * @return\n+ * The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_rmp(void *ctx,\n+\t\t\t struct mlx5_devx_create_rmp_attr *rmp_attr,\n+\t\t\t int socket)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};\n+\tvoid *rmp_ctx, *wq_ctx;\n+\tstruct mlx5_devx_wq_attr *wq_attr;\n+\tstruct mlx5_devx_obj *rmp = NULL;\n+\n+\trmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);\n+\tif (!rmp) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate RMP data\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);\n+\trmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);\n+\tMLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);\n+\tMLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,\n+\t\t rmp_attr->basic_cyclic_rcv_wqe);\n+\twq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);\n+\twq_attr = &rmp_attr->wq_attr;\n+\tdevx_cmd_fill_wq_data(wq_ctx, wq_attr);\n+\trmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,\n+\t\t\t\t\t sizeof(out));\n+\tif (!rmp->obj) {\n+\t\tDRV_LOG(ERR, \"Failed to create RMP using DevX\");\n+\t\trte_errno = errno;\n+\t\tmlx5_free(rmp);\n+\t\treturn NULL;\n+\t}\n+\trmp->id = MLX5_GET(create_rmp_out, out, rmpn);\n+\treturn rmp;\n+}\n+\n+/*\n * Create TIR using DevX API.\n *\n * @param[in] ctx\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 80b5dca1eb4..5759c4c9473 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -93,6 +93,8 @@ struct mlx5_hca_flow_attr {\n struct mlx5_hca_attr {\n \tuint32_t eswitch_manager:1;\n \tuint32_t flow_counters_dump:1;\n+\tuint32_t mem_rq_rmp:1;\n+\tuint32_t log_max_rmp:5;\n \tuint32_t log_max_rqt_size:5;\n \tuint32_t parse_graph_flex_node:1;\n \tuint8_t flow_counter_bulk_alloc_bitmap;\n@@ -259,6 +261,17 @@ struct mlx5_devx_modify_rq_attr {\n \tuint32_t lwm:16; /* Contained WQ lwm. */\n };\n \n+/* Create RMP attributes structure, used by create RMP operation. */\n+struct mlx5_devx_create_rmp_attr {\n+\tuint32_t rsvd0:8;\n+\tuint32_t state:4;\n+\tuint32_t rsvd1:20;\n+\tuint32_t basic_cyclic_rcv_wqe:1;\n+\tuint32_t rsvd4:31;\n+\tuint32_t rsvd8[10];\n+\tstruct mlx5_devx_wq_attr wq_attr;\n+};\n+\n struct mlx5_rx_hash_field_select {\n \tuint32_t l3_prot_type:1;\n \tuint32_t l4_prot_type:1;\n@@ -536,6 +549,9 @@ __rte_internal\n int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,\n \t\t\t struct mlx5_devx_modify_rq_attr *rq_attr);\n __rte_internal\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx,\n+\t\t\tstruct mlx5_devx_create_rmp_attr *rq_attr, int socket);\n+__rte_internal\n struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,\n \t\t\t\t\t struct mlx5_devx_tir_attr *tir_attr);\n __rte_internal\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 53931ebf1cc..7063b195ff4 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1062,6 +1062,10 @@ enum {\n \tMLX5_CMD_OP_CREATE_RQ = 0x908,\n \tMLX5_CMD_OP_MODIFY_RQ = 0x909,\n \tMLX5_CMD_OP_QUERY_RQ = 0x90b,\n+\tMLX5_CMD_OP_CREATE_RMP = 0x90c,\n+\tMLX5_CMD_OP_MODIFY_RMP = 0x90d,\n+\tMLX5_CMD_OP_DESTROY_RMP = 0x90e,\n+\tMLX5_CMD_OP_QUERY_RMP = 0x90f,\n \tMLX5_CMD_OP_CREATE_TIS = 0x912,\n \tMLX5_CMD_OP_QUERY_TIS = 0x915,\n \tMLX5_CMD_OP_CREATE_RQT = 0x916,\n@@ -1561,7 +1565,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_378[0x3];\n \tu8 log_max_tis[0x5];\n \tu8 basic_cyclic_rcv_wqe[0x1];\n-\tu8 reserved_at_381[0x2];\n+\tu8 reserved_at_381[0x1];\n+\tu8 mem_rq_rmp[0x1];\n \tu8 log_max_rmp[0x5];\n \tu8 reserved_at_388[0x3];\n \tu8 log_max_rqt[0x5];\n@@ -2209,6 +2214,84 @@ struct mlx5_ifc_query_rq_in_bits {\n \tu8 reserved_at_60[0x20];\n };\n \n+enum {\n+\tMLX5_RMPC_STATE_RDY = 0x1,\n+\tMLX5_RMPC_STATE_ERR = 0x3,\n+};\n+\n+struct mlx5_ifc_rmpc_bits {\n+\tu8 reserved_at_0[0x8];\n+\tu8 state[0x4];\n+\tu8 reserved_at_c[0x14];\n+\tu8 basic_cyclic_rcv_wqe[0x1];\n+\tu8 reserved_at_21[0x1f];\n+\tu8 reserved_at_40[0x140];\n+\tstruct mlx5_ifc_wq_bits wq;\n+};\n+\n+struct mlx5_ifc_query_rmp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0xc0];\n+\tstruct mlx5_ifc_rmpc_bits rmp_context;\n+};\n+\n+struct mlx5_ifc_query_rmp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 rmpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_modify_rmp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_rmp_bitmask_bits {\n+\tu8 reserved_at_0[0x20];\n+\tu8 reserved_at_20[0x1f];\n+\tu8 lwm[0x1];\n+};\n+\n+struct mlx5_ifc_modify_rmp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 rmp_state[0x4];\n+\tu8 reserved_at_44[0x4];\n+\tu8 rmpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tstruct mlx5_ifc_rmp_bitmask_bits bitmask;\n+\tu8 reserved_at_c0[0x40];\n+\tstruct mlx5_ifc_rmpc_bits ctx;\n+};\n+\n+struct mlx5_ifc_create_rmp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 rmpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_create_rmp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0xc0];\n+\tstruct mlx5_ifc_rmpc_bits ctx;\n+};\n+\n struct mlx5_ifc_create_tis_out_bits {\n \tu8 status[0x8];\n \tu8 reserved_at_8[0x18];\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex 0ea8325f9ac..7265ff8c56f 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -30,6 +30,7 @@ INTERNAL {\n \tmlx5_devx_cmd_create_geneve_tlv_option;\n \tmlx5_devx_cmd_create_import_kek_obj;\n \tmlx5_devx_cmd_create_qp;\n+\tmlx5_devx_cmd_create_rmp;\n \tmlx5_devx_cmd_create_rq;\n \tmlx5_devx_cmd_create_rqt;\n \tmlx5_devx_cmd_create_sq;\n", "prefixes": [ "v3", "03/14" ] }