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GET /api/patches/103416/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 103416,
    "url": "http://patches.dpdk.org/api/patches/103416/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211102040556.7840-18-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211102040556.7840-18-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211102040556.7840-18-venkatkumar.duvvuru@broadcom.com",
    "date": "2021-11-02T04:05:53",
    "name": "[v3,17/20] net/bnxt: add Tx TruFlow table config for p4 device",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ae0d859bcedca5439f8de73eaeee33ed44739195",
    "submitter": {
        "id": 1635,
        "url": "http://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211102040556.7840-18-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 20191,
            "url": "http://patches.dpdk.org/api/series/20191/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20191",
            "date": "2021-11-02T04:05:36",
            "name": "fixes and enhancements to Truflow",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/20191/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/103416/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/103416/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 57DA9A0C4D;\n\tTue,  2 Nov 2021 05:08:19 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id ACB3D411EB;\n\tTue,  2 Nov 2021 05:06:35 +0100 (CET)",
            "from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com\n [192.19.166.228])\n by mails.dpdk.org (Postfix) with ESMTP id CE603411CB\n for <dev@dpdk.org>; Tue,  2 Nov 2021 05:06:33 +0100 (CET)",
            "from S60.dhcp.broadcom.net (unknown [10.123.66.170])\n (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n (No client certificate requested)\n by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 1D0097A21;\n Mon,  1 Nov 2021 21:06:31 -0700 (PDT)"
        ],
        "DKIM-Filter": "OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 1D0097A21",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1635825993;\n bh=B0dwwRkCrGn08f9Gb9GRfEOoPbzzW6U81SU0MkJ4CO0=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=q0g5Twx3Cdzl0iN44aSfxns6S4MRVV02UdUl6wKbRcWHwhJs5U0ErR75fztgib7FD\n sL5UtndhVqVuipdopU/jkJeV/bogqdRUhDwiyrWdC8T3YcUWi4IW5ljcGaQURkPmvW\n EOF68BRpkGb6B+p3ZhmcVDD5mI3ZpeX7dFzVOCQY=",
        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Jay Ding <jay.ding@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "Date": "Tue,  2 Nov 2021 09:35:53 +0530",
        "Message-Id": "<20211102040556.7840-18-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20211102040556.7840-1-venkatkumar.duvvuru@broadcom.com>",
        "References": "<20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com>\n <20211102040556.7840-1-venkatkumar.duvvuru@broadcom.com>",
        "Subject": "[dpdk-dev] [PATCH v3 17/20] net/bnxt: add Tx TruFlow table config\n for p4 device",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jay Ding <jay.ding@broadcom.com>\n\nAdd TX direction TruFlow table type config to be\ncompatible with other devices. For P4 device, the TX cfg\nis duplicated from RX.\n\nSigned-off-by: Jay Ding <jay.ding@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Farah Smith <farah.smith@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\n---\n drivers/net/bnxt/tf_core/tf_device.c    |   4 +-\n drivers/net/bnxt/tf_core/tf_device_p4.c | 107 ++++++++++++++++++++++++\n drivers/net/bnxt/tf_core/tf_device_p4.h |  58 +------------\n 3 files changed, 111 insertions(+), 58 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c\nindex 40db546604..4c416270b6 100644\n--- a/drivers/net/bnxt/tf_core/tf_device.c\n+++ b/drivers/net/bnxt/tf_core/tf_device.c\n@@ -131,11 +131,11 @@ tf_dev_bind_p4(struct tf *tfp,\n \t}\n \n \trsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX,\n-\t\t\t\t\t   tf_tbl_p4,\n+\t\t\t\t\t   tf_tbl_p4[TF_DIR_RX],\n \t\t\t\t\t   (uint16_t *)resources->tbl_cnt);\n \tif (rsv_cnt) {\n \t\ttbl_cfg.num_elements = TF_TBL_TYPE_MAX;\n-\t\ttbl_cfg.cfg = tf_tbl_p4;\n+\t\ttbl_cfg.cfg = tf_tbl_p4[TF_DIR_RX];\n \t\ttbl_cfg.resources = resources;\n \t\trc = tf_tbl_bind(tfp, &tbl_cfg);\n \t\tif (rc) {\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c\nindex 244bd08914..a6a59b8a07 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p4.c\n+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c\n@@ -59,6 +59,113 @@ const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {\n \t[CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = \"tb_scope\",\n };\n \n+struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {\n+\t[TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_METER_INST] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_METER_INST] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,\n+\t\t0, 0\n+\t},\n+\t[TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,\n+\t\t0, 0\n+\t},\n+};\n+\n /**\n  * Device specific function that retrieves the MAX number of HCAPI\n  * types the device supports.\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h\nindex e84c0f9e83..86de525995 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p4.h\n+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h\n@@ -12,6 +12,8 @@\n #include \"tf_if_tbl.h\"\n #include \"tf_global_cfg.h\"\n \n+extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX];\n+\n struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {\n \t[TF_IDENT_TYPE_L2_CTXT_HIGH] = {\n \t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH,\n@@ -58,62 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {\n \t},\n };\n \n-struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {\n-\t[TF_TBL_TYPE_FULL_ACT_RECORD] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_MCAST_GROUPS] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_ACT_ENCAP_8B] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_ACT_ENCAP_16B] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_ACT_ENCAP_64B] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_ACT_SP_SMAC] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_ACT_STATS_64] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_ACT_MODIFY_IPV4] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_METER_PROF] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_METER_INST] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,\n-\t\t0, 0\n-\t},\n-\t[TF_TBL_TYPE_MIRROR_CONFIG] = {\n-\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,\n-\t\t0, 0\n-\t},\n-\n-};\n-\n struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {\n \t[TF_EM_TBL_TYPE_TBL_SCOPE] = {\n \t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,\n",
    "prefixes": [
        "v3",
        "17/20"
    ]
}