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GET /api/patches/102678/?format=api
{ "id": 102678, "url": "http://patches.dpdk.org/api/patches/102678/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211022154600.2180938-7-fkelly@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211022154600.2180938-7-fkelly@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211022154600.2180938-7-fkelly@nvidia.com", "date": "2021-10-22T15:45:57", "name": "[07/10] regex/mlx5: removed redundant rxp csr file", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7a7e880900eb90a74acae255f7f0e45bb13082fc", "submitter": { "id": 2387, "url": "http://patches.dpdk.org/api/people/2387/?format=api", "name": "Francis Kelly", "email": "fkelly@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211022154600.2180938-7-fkelly@nvidia.com/mbox/", "series": [ { "id": 19921, "url": "http://patches.dpdk.org/api/series/19921/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19921", "date": "2021-10-22T15:45:51", "name": "[01/10] common/mlx5: update PRM definitions for regex availability", "version": 1, "mbox": "http://patches.dpdk.org/series/19921/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102678/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102678/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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"Message-ID": "<20211022154600.2180938-7-fkelly@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211022154600.2180938-1-fkelly@nvidia.com>", "References": "<20211022154600.2180938-1-fkelly@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "a9ffde78-13b5-4226-33d5-08d9957356ab", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB3078:", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB3078F787AEA07396F2037ED5B9809@BYAPR12MB3078.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7219;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(4636009)(46966006)(36840700001)(7696005)(1076003)(2906002)(86362001)(5660300002)(70586007)(426003)(82310400003)(36756003)(36860700001)(47076005)(54906003)(16526019)(26005)(336012)(2616005)(186003)(6666004)(6636002)(356005)(4326008)(508600001)(7636003)(55016002)(70206006)(8936002)(110136005)(8676002)(36906005)(6286002)(316002)(30864003)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Oct 2021 15:48:05.6014 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a9ffde78-13b5-4226-33d5-08d9957356ab", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT014.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB3078", "Subject": "[dpdk-dev] [PATCH 07/10] regex/mlx5: removed redundant rxp csr file", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The mlx5_rxp_csrs.h file has been deprecated as\nits contents has now been moved to FW.\n\nSigned-off-by: Francis Kelly <fkelly@nvidia.com>\n---\n drivers/regex/mlx5/mlx5_regex.c | 1 -\n drivers/regex/mlx5/mlx5_regex_control.c | 1 -\n drivers/regex/mlx5/mlx5_rxp.c | 1 -\n drivers/regex/mlx5/mlx5_rxp.h | 1 +\n drivers/regex/mlx5/mlx5_rxp_csrs.h | 342 ------------------------\n 5 files changed, 1 insertion(+), 345 deletions(-)\n delete mode 100644 drivers/regex/mlx5/mlx5_rxp_csrs.h", "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex d58851d41d..49ef6fb212 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -19,7 +19,6 @@\n \n #include \"mlx5_regex.h\"\n #include \"mlx5_regex_utils.h\"\n-#include \"mlx5_rxp_csrs.h\"\n \n #define MLX5_REGEX_DRIVER_NAME regex_mlx5\n \ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex 1783df923c..3e0a0cdd71 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -22,7 +22,6 @@\n \n #include \"mlx5_regex.h\"\n #include \"mlx5_regex_utils.h\"\n-#include \"mlx5_rxp_csrs.h\"\n #include \"mlx5_rxp.h\"\n \n #define MLX5_REGEX_NUM_WQE_PER_PAGE (4096/64)\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c\nindex 59c68544ad..dbd632fc74 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.c\n+++ b/drivers/regex/mlx5/mlx5_rxp.c\n@@ -17,7 +17,6 @@\n \n #include \"mlx5_regex.h\"\n #include \"mlx5_regex_utils.h\"\n-#include \"mlx5_rxp_csrs.h\"\n #include \"mlx5_rxp.h\"\n \n #define MLX5_REGEX_MAX_MATCHES MLX5_RXP_MAX_MATCHES\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.h b/drivers/regex/mlx5/mlx5_rxp.h\nindex 254e9cfa2b..315e3b4ca3 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.h\n+++ b/drivers/regex/mlx5/mlx5_rxp.h\n@@ -5,6 +5,7 @@\n #ifndef RTE_PMD_MLX5_REGEX_RXP_H_\n #define RTE_PMD_MLX5_REGEX_RXP_H_\n \n+#define MLX5_RXP_BF2_IDENTIFIER 0x0\n #define MLX5_RXP_MAX_JOB_LENGTH\t16384\n #define MLX5_RXP_MAX_SUBSETS 4095\n #define MLX5_RXP_CSR_NUM_ENTRIES 31\ndiff --git a/drivers/regex/mlx5/mlx5_rxp_csrs.h b/drivers/regex/mlx5/mlx5_rxp_csrs.h\ndeleted file mode 100644\nindex 08cb6f3261..0000000000\n--- a/drivers/regex/mlx5/mlx5_rxp_csrs.h\n+++ /dev/null\n@@ -1,342 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright 2020 Mellanox Technologies, Ltd\n- */\n-\n-#ifndef _MLX5_RXP_CSRS_H_\n-#define _MLX5_RXP_CSRS_H_\n-\n-/* BF types */\n-#define MLX5_RXP_BF2_IDENTIFIER 0x0\n-\n-/*\n- * Common to all RXP implementations\n- */\n-#define MLX5_RXP_CSR_BASE_ADDRESS 0x0000ul\n-#define MLX5_RXP_RTRU_CSR_BASE_ADDRESS 0x0100ul\n-#define MLX5_RXP_STATS_CSR_BASE_ADDRESS\t0x0200ul\n-#define MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS 0x0600ul\n-\n-#define MLX5_RXP_CSR_WIDTH 4\n-\n-/* This is the identifier we expect to see in the first RXP CSR */\n-#define MLX5_RXP_IDENTIFIER 0x5254\n-\n-/* Hyperion specific BAR0 offsets */\n-#define MLX5_RXP_FPGA_BASE_ADDRESS 0x0000ul\n-#define MLX5_RXP_PCIE_BASE_ADDRESS 0x1000ul\n-#define MLX5_RXP_IDMA_BASE_ADDRESS 0x2000ul\n-#define MLX5_RXP_EDMA_BASE_ADDRESS 0x3000ul\n-#define MLX5_RXP_SYSMON_BASE_ADDRESS 0xf300ul\n-#define MLX5_RXP_ISP_CSR_BASE_ADDRESS 0xf400ul\n-\n-/* Offset to the RXP common 4K CSR space */\n-#define MLX5_RXP_PCIE_CSR_BASE_ADDRESS 0xf000ul\n-\n-/* FPGA CSRs */\n-\n-#define MLX5_RXP_FPGA_VERSION (MLX5_RXP_FPGA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 0)\n-\n-/* PCIe CSRs */\n-#define MLX5_RXP_PCIE_INIT_ISR (MLX5_RXP_PCIE_BASE_ADDRESS + \\\n-\t\t\t\tMLX5_RXP_CSR_WIDTH * 0)\n-#define MLX5_RXP_PCIE_INIT_IMR (MLX5_RXP_PCIE_BASE_ADDRESS + \\\n-\t\t\t\tMLX5_RXP_CSR_WIDTH * 1)\n-#define MLX5_RXP_PCIE_INIT_CFG_STAT (MLX5_RXP_PCIE_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 2)\n-#define MLX5_RXP_PCIE_INIT_FLR (MLX5_RXP_PCIE_BASE_ADDRESS + \\\n-\t\t\t\tMLX5_RXP_CSR_WIDTH * 3)\n-#define MLX5_RXP_PCIE_INIT_CTRL\t(MLX5_RXP_PCIE_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 4)\n-\n-/* IDMA CSRs */\n-#define MLX5_RXP_IDMA_ISR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)\n-#define MLX5_RXP_IDMA_IMR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)\n-#define MLX5_RXP_IDMA_CSR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)\n-#define MLX5_RXP_IDMA_CSR_RST_MSK 0x0001\n-#define MLX5_RXP_IDMA_CSR_PDONE_MSK 0x0002\n-#define MLX5_RXP_IDMA_CSR_INIT_MSK 0x0004\n-#define MLX5_RXP_IDMA_CSR_EN_MSK 0x0008\n-#define MLX5_RXP_IDMA_QCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)\n-#define MLX5_RXP_IDMA_QCR_QAVAIL_MSK 0x00FF\n-#define MLX5_RXP_IDMA_QCR_QEN_MSK 0xFF00\n-#define MLX5_RXP_IDMA_DCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)\n-#define MLX5_RXP_IDMA_DWCTR (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 7)\n-#define MLX5_RXP_IDMA_DWTOR (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 8)\n-#define MLX5_RXP_IDMA_PADCR (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 9)\n-#define MLX5_RXP_IDMA_DFCR (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 10)\n-#define MLX5_RXP_IDMA_FOFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 16)\n-#define MLX5_RXP_IDMA_FOFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 17)\n-#define MLX5_RXP_IDMA_FOFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 18)\n-#define MLX5_RXP_IDMA_FUFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 24)\n-#define MLX5_RXP_IDMA_FUFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 25)\n-#define MLX5_RXP_IDMA_FUFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 26)\n-\n-#define MLX5_RXP_IDMA_QCSR_BASE\t(MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 128)\n-#define MLX5_RXP_IDMA_QCSR_RST_MSK 0x0001\n-#define MLX5_RXP_IDMA_QCSR_PDONE_MSK 0x0002\n-#define MLX5_RXP_IDMA_QCSR_INIT_MSK 0x0004\n-#define MLX5_RXP_IDMA_QCSR_EN_MSK 0x0008\n-#define MLX5_RXP_IDMA_QDPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 192)\n-#define MLX5_RXP_IDMA_QTPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 256)\n-#define MLX5_RXP_IDMA_QDRPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 320)\n-#define MLX5_RXP_IDMA_QDRALR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 384)\n-#define MLX5_RXP_IDMA_QDRAHR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 385)\n-\n-/* EDMA CSRs */\n-#define MLX5_RXP_EDMA_ISR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)\n-#define MLX5_RXP_EDMA_IMR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)\n-#define MLX5_RXP_EDMA_CSR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)\n-#define MLX5_RXP_EDMA_CSR_RST_MSK 0x0001\n-#define MLX5_RXP_EDMA_CSR_PDONE_MSK 0x0002\n-#define MLX5_RXP_EDMA_CSR_INIT_MSK 0x0004\n-#define MLX5_RXP_EDMA_CSR_EN_MSK 0x0008\n-#define MLX5_RXP_EDMA_QCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)\n-#define MLX5_RXP_EDMA_QCR_QAVAIL_MSK 0x00FF\n-#define MLX5_RXP_EDMA_QCR_QEN_MSK 0xFF00\n-#define MLX5_RXP_EDMA_DCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)\n-#define MLX5_RXP_EDMA_DWCTR (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 7)\n-#define MLX5_RXP_EDMA_DWTOR (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 8)\n-#define MLX5_RXP_EDMA_DFCR (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 10)\n-#define MLX5_RXP_EDMA_FOFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 16)\n-#define MLX5_RXP_EDMA_FOFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 17)\n-#define MLX5_RXP_EDMA_FOFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 18)\n-#define MLX5_RXP_EDMA_FUFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 24)\n-#define MLX5_RXP_EDMA_FUFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS +\\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 25)\n-#define MLX5_RXP_EDMA_FUFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 26)\n-\n-#define MLX5_RXP_EDMA_QCSR_BASE\t(MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 128)\n-#define MLX5_RXP_EDMA_QCSR_RST_MSK 0x0001\n-#define MLX5_RXP_EDMA_QCSR_PDONE_MSK 0x0002\n-#define MLX5_RXP_EDMA_QCSR_INIT_MSK 0x0004\n-#define MLX5_RXP_EDMA_QCSR_EN_MSK 0x0008\n-#define MLX5_RXP_EDMA_QTPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 256)\n-#define MLX5_RXP_EDMA_QDRPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 320)\n-#define MLX5_RXP_EDMA_QDRALR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 384)\n-#define MLX5_RXP_EDMA_QDRAHR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 385)\n-\n-/* Main CSRs */\n-#define MLX5_RXP_CSR_IDENTIFIER\t(MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 0)\n-#define MLX5_RXP_CSR_REVISION (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 1)\n-#define MLX5_RXP_CSR_CAPABILITY_0 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 2)\n-#define MLX5_RXP_CSR_CAPABILITY_1 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 3)\n-#define MLX5_RXP_CSR_CAPABILITY_2 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 4)\n-#define MLX5_RXP_CSR_CAPABILITY_3 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 5)\n-#define MLX5_RXP_CSR_CAPABILITY_4 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 6)\n-#define MLX5_RXP_CSR_CAPABILITY_5 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 7)\n-#define MLX5_RXP_CSR_CAPABILITY_6 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 8)\n-#define MLX5_RXP_CSR_CAPABILITY_7 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 9)\n-#define MLX5_RXP_CSR_STATUS (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 10)\n-#define MLX5_RXP_CSR_STATUS_INIT_DONE 0x0001\n-#define MLX5_RXP_CSR_STATUS_GOING 0x0008\n-#define MLX5_RXP_CSR_STATUS_IDLE 0x0040\n-#define MLX5_RXP_CSR_STATUS_TRACKER_OK 0x0080\n-#define MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT 0x0100\n-#define MLX5_RXP_CSR_FIFO_STATUS_0 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 11)\n-#define MLX5_RXP_CSR_FIFO_STATUS_1 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 12)\n-#define MLX5_RXP_CSR_JOB_DDOS_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 13)\n-/* 14 + 15 reserved */\n-#define MLX5_RXP_CSR_CORE_CLK_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 16)\n-#define MLX5_RXP_CSR_WRITE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 17)\n-#define MLX5_RXP_CSR_JOB_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\tMLX5_RXP_CSR_WIDTH * 18)\n-#define MLX5_RXP_CSR_JOB_ERROR_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 19)\n-#define MLX5_RXP_CSR_JOB_BYTE_COUNT0 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 20)\n-#define MLX5_RXP_CSR_JOB_BYTE_COUNT1 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 21)\n-#define MLX5_RXP_CSR_RESPONSE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 22)\n-#define MLX5_RXP_CSR_MATCH_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 23)\n-#define MLX5_RXP_CSR_CTRL (MLX5_RXP_CSR_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 24)\n-#define MLX5_RXP_CSR_CTRL_INIT 0x0001\n-#define MLX5_RXP_CSR_CTRL_GO 0x0008\n-#define MLX5_RXP_CSR_MAX_MATCH (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\tMLX5_RXP_CSR_WIDTH * 25)\n-#define MLX5_RXP_CSR_MAX_PREFIX\t(MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 26)\n-#define MLX5_RXP_CSR_MAX_PRI_THREAD (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 27)\n-#define MLX5_RXP_CSR_MAX_LATENCY (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 28)\n-#define MLX5_RXP_CSR_SCRATCH_1 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\tMLX5_RXP_CSR_WIDTH * 29)\n-#define MLX5_RXP_CSR_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 30)\n-#define MLX5_RXP_CSR_INTRA_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \\\n-\t\t\t\t\t MLX5_RXP_CSR_WIDTH * 31)\n-\n-/* Runtime Rule Update CSRs */\n-/* 0 + 1 reserved */\n-#define MLX5_RXP_RTRU_CSR_CAPABILITY (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 2)\n-/* 3-9 reserved */\n-#define MLX5_RXP_RTRU_CSR_STATUS (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 10)\n-#define MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE 0x0002\n-#define MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE 0x0010\n-#define MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE 0x0020\n-#define MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE 0x0040\n-#define MLX5_RXP_RTRU_CSR_STATUS_EM_INIT_DONE 0x0080\n-#define MLX5_RXP_RTRU_CSR_FIFO_STAT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 11)\n-/* 12-15 reserved */\n-#define MLX5_RXP_RTRU_CSR_CHECKSUM_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 16)\n-#define MLX5_RXP_RTRU_CSR_CHECKSUM_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 17)\n-#define MLX5_RXP_RTRU_CSR_CHECKSUM_2 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 18)\n-/* 19 + 20 reserved */\n-#define MLX5_RXP_RTRU_CSR_RTRU_COUNT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 21)\n-#define MLX5_RXP_RTRU_CSR_ROF_REV (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 22)\n-/* 23 reserved */\n-#define MLX5_RXP_RTRU_CSR_CTRL (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\tMLX5_RXP_CSR_WIDTH * 24)\n-#define MLX5_RXP_RTRU_CSR_CTRL_INIT 0x0001\n-#define MLX5_RXP_RTRU_CSR_CTRL_GO 0x0002\n-#define MLX5_RXP_RTRU_CSR_CTRL_SIP 0x0004\n-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK (3 << 4)\n-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2_EM (0 << 4)\n-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2 (1 << 4)\n-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2 (2 << 4)\n-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_EM (3 << 4)\n-#define MLX5_RXP_RTRU_CSR_ADDR (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\tMLX5_RXP_CSR_WIDTH * 25)\n-#define MLX5_RXP_RTRU_CSR_DATA_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 26)\n-#define MLX5_RXP_RTRU_CSR_DATA_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 27)\n-/* 28-31 reserved */\n-\n-/* Statistics CSRs */\n-#define MLX5_RXP_STATS_CSR_CLUSTER (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 0)\n-#define MLX5_RXP_STATS_CSR_L2_CACHE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 24)\n-#define MLX5_RXP_STATS_CSR_MPFE_FIFO (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 25)\n-#define MLX5_RXP_STATS_CSR_PE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 28)\n-#define MLX5_RXP_STATS_CSR_CP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 30)\n-#define MLX5_RXP_STATS_CSR_DP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n-\t\t\t MLX5_RXP_CSR_WIDTH * 31)\n-\n-/* Sysmon Stats CSRs */\n-#define MLX5_RXP_SYSMON_CSR_T_FPGA (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 0)\n-#define MLX5_RXP_SYSMON_CSR_V_VCCINT (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 1)\n-#define MLX5_RXP_SYSMON_CSR_V_VCCAUX (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 2)\n-#define MLX5_RXP_SYSMON_CSR_T_U1 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 20)\n-#define MLX5_RXP_SYSMON_CSR_I_EDG12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 21)\n-#define MLX5_RXP_SYSMON_CSR_I_VCC3V3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 22)\n-#define MLX5_RXP_SYSMON_CSR_I_VCC2V5 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 23)\n-#define MLX5_RXP_SYSMON_CSR_T_U2 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 28)\n-#define MLX5_RXP_SYSMON_CSR_I_AUX12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 29)\n-#define MLX5_RXP_SYSMON_CSR_I_VCC1V8 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 30)\n-#define MLX5_RXP_SYSMON_CSR_I_VDDR3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n-\t\t\t\t MLX5_RXP_CSR_WIDTH * 31)\n-\n-/* In Service Programming CSRs */\n-\n-/* RXP-F1 and RXP-ZYNQ specific CSRs */\n-#define MLX5_RXP_MQ_CP_BASE (0x0500ul)\n-#define MLX5_RXP_MQ_CP_CAPABILITY_BASE (MLX5_RXP_MQ_CP_BASE + \\\n-\t\t\t\t\t2 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_CAPABILITY_0 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \\\n-\t\t\t\t 0 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_CAPABILITY_1 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \\\n-\t\t\t\t 1 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_CAPABILITY_2 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \\\n-\t\t\t\t 2 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_CAPABILITY_3 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \\\n-\t\t\t\t 3 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_FIFO_STATUS_BASE (MLX5_RXP_MQ_CP_BASE + \\\n-\t\t\t\t\t 11 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_FIFO_STATUS_C0 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \\\n-\t\t\t\t 0 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_FIFO_STATUS_C1 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \\\n-\t\t\t\t 1 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_FIFO_STATUS_C2 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \\\n-\t\t\t\t 2 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXP_MQ_CP_FIFO_STATUS_C3 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \\\n-\t\t\t\t 3 * MLX5_RXP_CSR_WIDTH)\n-\n-/* Royalty tracker / licensing related CSRs */\n-#define MLX5_RXPL__CSR_IDENT (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n-\t\t\t 0 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXPL__IDENTIFIER 0x4c505852 /* MLX5_RXPL_ */\n-#define MLX5_RXPL__CSR_CAPABILITY (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n-\t\t\t\t 2 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXPL__TYPE_MASK 0xFF\n-#define MLX5_RXPL__TYPE_NONE 0\n-#define MLX5_RXPL__TYPE_MAXIM 1\n-#define MLX5_RXPL__TYPE_XILINX_DNA 2\n-#define MLX5_RXPL__CSR_STATUS (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n-\t\t\t 10 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXPL__CSR_IDENT_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n-\t\t\t\t16 * MLX5_RXP_CSR_WIDTH)\n-#define MLX5_RXPL__CSR_KEY_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n-\t\t\t 24 * MLX5_RXP_CSR_WIDTH)\n-\n-#endif /* _MLX5_RXP_CSRS_H_ */\n", "prefixes": [ "07/10" ] }