Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/102675/?format=api
{ "id": 102675, "url": "http://patches.dpdk.org/api/patches/102675/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211022154600.2180938-5-fkelly@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211022154600.2180938-5-fkelly@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211022154600.2180938-5-fkelly@nvidia.com", "date": "2021-10-22T15:45:55", "name": "[05/10] regex/mlx5: move RXP to CrSpace", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f740f3c3dbaa678224f75cd26fb39102f8f4fb72", "submitter": { "id": 2387, "url": "http://patches.dpdk.org/api/people/2387/?format=api", "name": "Francis Kelly", "email": "fkelly@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211022154600.2180938-5-fkelly@nvidia.com/mbox/", "series": [ { "id": 19921, "url": "http://patches.dpdk.org/api/series/19921/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19921", "date": "2021-10-22T15:45:51", "name": "[01/10] common/mlx5: update PRM definitions for regex availability", "version": 1, "mbox": "http://patches.dpdk.org/series/19921/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102675/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102675/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F079CA0C43;\n\tFri, 22 Oct 2021 17:48:14 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B914841212;\n\tFri, 22 Oct 2021 17:48:09 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2040.outbound.protection.outlook.com [40.107.244.40])\n by mails.dpdk.org (Postfix) with ESMTP id 8968B41208\n for <dev@dpdk.org>; Fri, 22 Oct 2021 17:48:07 +0200 (CEST)", "from DM6PR11CA0048.namprd11.prod.outlook.com (2603:10b6:5:14c::25)\n by MW3PR12MB4570.namprd12.prod.outlook.com (2603:10b6:303:5f::12) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.16; Fri, 22 Oct\n 2021 15:48:02 +0000", "from DM6NAM11FT014.eop-nam11.prod.protection.outlook.com\n (2603:10b6:5:14c:cafe::27) by DM6PR11CA0048.outlook.office365.com\n (2603:10b6:5:14c::25) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18 via Frontend\n Transport; Fri, 22 Oct 2021 15:48:02 +0000", "from mail.nvidia.com (216.228.112.34) by\n DM6NAM11FT014.mail.protection.outlook.com (10.13.173.132) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4628.16 via Frontend Transport; Fri, 22 Oct 2021 15:48:02 +0000", "from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Oct\n 2021 15:47:55 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=ddZIklUav29yrS7WZmgrfUEb13m90Q5dhvT1rzzOJqheJMjzsBCZdxHEh342KNWI5RufSzYId4wxQ+a8IfiZvy+LuEBU+KTlqSArmQd2oRCdUghcsmPqJXOJiXMeVZissnX6DuvC/yWBXMYseefWZBT8IG3FhT0HwWnE9aW9BssRq6EQo1jAHbvM3fKACyYJKewOG20I0StlB6K3ZiB1R1mI3QLosJ69op7YNVYIhJ/t+mHHc2E8UBSRMgYfpJft2ig54E+XW99G8QN0lCSHIoBgldAR3+0KGRGZvF4jrlLNJZarrtnRA/E/5ELesJ4okm66kwPZckLxWffpjHJSnA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=/NRvh9DfmoereoC+QpNJ+YHlXzKxxCbeiTyV8LjNbS0=;\n b=mLwlAKpsPtMkXZ3lf736wchkFngq4fGzQ0zlCKnvz9vMoFgGHgpTpWdfaRi4D7yT9BXZShFgyurnLCehLOAIS/2eDxy0UavIl+VO7guORApL39dfzr5sAsUvZPpD0kO9cCAxmI57Opv1cVFKTAAUlachdEDIZ7DZ3TVrkywstpVxvn8rEx7ItadI14sTYQwiwZS7niJAds4s+tFrHceKuwOwW0MU2gHGOVjlS14+ia6yCr0Yc9bPPyb+LQUzDvjA3i31VYowwCzg0ts7kasWRR6nLNzahbjceVHas7kj1g/1r1ubAx+LHnqxRKwKEzStbPu3AOoVSbxHjvhKtIKlxg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=quarantine pct=100) action=none\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/NRvh9DfmoereoC+QpNJ+YHlXzKxxCbeiTyV8LjNbS0=;\n b=NJ/hBID8K9txqeIrU2NBdPsyCnvxcJRlz/GUVGz4McuD18FDt9jMkvugLuCaVzn8BfxR5TRKEL8O4UXPov+GzvGnr1M3vT0DJ3AHZAYS0vGi7ysL71ZwW7sQa1UNtVfOaQu72IcWpqW/dzgwwxIM+3r64pY1Z5oRBGF94GZjIKa/BpCPuufEoVqYwYfUo2nPB/Bpzqm8iu1N3pmoWIdrdisn0emYzgqqQDo8y4cIXqwF+Er0JXBMJoLnBFOuL3RYH6br6sdagaHsY3LZH4hTQWzozbSzfb2qaO/Yf9mYfgu4GaObKiZGRsCos0xHigieNvINNU21vgxue4zPQIE+Fw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; gmail.com; dkim=none (message not signed)\n header.d=none;gmail.com; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Francis Kelly <fkelly@nvidia.com>", "To": "<tmonjalon@nvidia.com>, Ori Kam <orika@nvidia.com>", "CC": "<jamhunter@nvidia.com>, <aagbarih@nvidia.com>, <dev@dpdk.org>, Ady Agbarih\n <adypodoman@gmail.com>", "Date": "Fri, 22 Oct 2021 15:45:55 +0000", "Message-ID": "<20211022154600.2180938-5-fkelly@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211022154600.2180938-1-fkelly@nvidia.com>", "References": "<20211022154600.2180938-1-fkelly@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b7219521-089c-481d-5a15-08d9957354ba", "X-MS-TrafficTypeDiagnostic": "MW3PR12MB4570:", "X-Microsoft-Antispam-PRVS": "\n <MW3PR12MB4570B0FB82AF54681B4EC74BB9809@MW3PR12MB4570.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2399;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n FvjWo+U8ASNRZF98jyyQVyZAM7rpOBRpvg8pKa09iwlUJYotDg/qfD0Tj38PfmJpWV9Mbbq08FWm26z7+czhYjE3/HKTVijQSMUUp0iln/8+KigUkB1MD3lPV8NGdOj+HrRcpNDCrwLSwI9J7fjWnvU5kKzoPZ/6VgB/1tl2n7YL6plY0F7pNBQ3+Ejtv2e0LCA5oW5Ara1LwUTEedeSacoDl/QIHzMjx5izycQLDWns7PPqmtUgnb7/lDaG3cpdD8BtXPfbYwnhfoZr/d8LIVcqbbFVQGiTa8WOMhj0RbQH3IvM/jeQsQw2CN8xdkQm3OuRrlVTACmvzXhRNpKRYitdNC+R2xRinYfBbJz5hohjPDf29ueBBVAm0drvIywcOWuaWh7fCaYzOSrZ63yUySUNM8zvRw3k3WdPqO972m6mNjiYS8MTLWh5KMXQhWqS7mpKRdKZGPUlcmWMX9lOf6J+BDKC+Y4QhrKQoVUxMXDveJWEbx65BG6Qx4H0d3H8IvBSKOHdcwHYz2qF94A0q0Pj8lzZxIiLdMzJtcVIRxqfSPVdmNOtTCE0ksAQ59qE+ABRzTzbpOW4y8zUZ0sBXFRa3fSU4oDMkIHHaRt7kLCybUZoCjRExS/CTq0oBfc2AhFUM6EsJF9Pi8oKOyu6gkjMuvZz8NXUlAyLK6PaR/64n97zEVMmpOBRUAfJ3hCN6/OIZWQgB6KziIz9xS5KJQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(6029001)(4636009)(46966006)(36840700001)(47076005)(110136005)(1076003)(70586007)(7636003)(86362001)(82310400003)(54906003)(316002)(36906005)(55016002)(336012)(7696005)(70206006)(356005)(36756003)(4326008)(8676002)(2616005)(36860700001)(508600001)(16526019)(8936002)(6286002)(186003)(426003)(6636002)(2906002)(26005)(5660300002)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Oct 2021 15:48:02.1924 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b7219521-089c-481d-5a15-08d9957354ba", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT014.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4570", "Subject": "[dpdk-dev] [PATCH 05/10] regex/mlx5: move RXP to CrSpace", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ady Agbarih <adypodoman@gmail.com>\n\nAdd patch for programming the regex database through rof file,\nusing the firmware instead of manually through the software.\nNo need to setup the DB anymore, the regex-daemon is responsible\nfor that always.\nIn the new flow the regex driver only has to program rof rules\nby using set params devx cmd, requires rof mkey creation.\nThe rules file has to be read into 4KB aligned memory.\n\nSigned-off-by: Ady Agbarih <adypodoman@gmail.com>\n---\n drivers/regex/mlx5/mlx5_regex.h | 12 ----\n drivers/regex/mlx5/mlx5_rxp.c | 111 ++++++++++++++++++++------------\n drivers/regex/mlx5/mlx5_rxp.h | 4 +-\n 3 files changed, 72 insertions(+), 55 deletions(-)", "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 09b360a1ab..9741421e7a 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -46,16 +46,6 @@ struct mlx5_regex_qp {\n \tstruct mlx5_mr_ctrl mr_ctrl;\n };\n \n-struct mlx5_regex_db {\n-\tvoid *ptr; /* Pointer to the db memory. */\n-\tuint32_t len; /* The memory len. */\n-\tbool active; /* Active flag. */\n-\tuint8_t db_assigned_to_eng_num;\n-\t/**< To which engine the db is connected. */\n-\tstruct mlx5_regex_umem umem;\n-\t/**< The umem struct. */\n-};\n-\n struct mlx5_regex_priv {\n \tTAILQ_ENTRY(mlx5_regex_priv) next;\n \tstruct ibv_context *ctx; /* Device context. */\n@@ -64,8 +54,6 @@ struct mlx5_regex_priv {\n \tstruct mlx5_regex_qp *qps; /* Pointer to the qp array. */\n \tuint16_t nb_max_matches; /* Max number of matches. */\n \tenum mlx5_rxp_program_mode prog_mode;\n-\tstruct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES +\n-\t\t\t\tMLX5_RXP_EM_COUNT];\n \tuint32_t nb_engines; /* Number of RegEx engines. */\n \tstruct mlx5dv_devx_uar *uar; /* UAR object. */\n \tstruct ibv_pd *pd;\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c\nindex 8f54ab018e..59c68544ad 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.c\n+++ b/drivers/regex/mlx5/mlx5_rxp.c\n@@ -28,6 +28,12 @@\n #define MLX5_REGEX_RXP_ROF2_LINE_LEN 34\n \n /* Private Declarations */\n+static int\n+rxp_create_mkey(struct mlx5_regex_priv *priv, void *ptr, size_t size,\n+\tuint32_t access, struct mlx5_regex_mkey *mkey);\n+static inline void\n+rxp_destroy_mkey(struct mlx5_regex_mkey *mkey);\n+\n int\n mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,\n \t\t struct rte_regexdev_info *info)\n@@ -44,44 +50,46 @@ mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,\n }\n \n static int\n-rxp_db_setup(struct mlx5_regex_priv *priv)\n+rxp_create_mkey(struct mlx5_regex_priv *priv, void *ptr, size_t size,\n+\tuint32_t access, struct mlx5_regex_mkey *mkey)\n {\n-\tint ret;\n-\tuint8_t i;\n+\tstruct mlx5_devx_mkey_attr mkey_attr;\n \n-\t/* Setup database memories for both RXP engines + reprogram memory. */\n-\tfor (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {\n-\t\tpriv->db[i].ptr = rte_malloc(\"\", MLX5_MAX_DB_SIZE, 1 << 21);\n-\t\tif (!priv->db[i].ptr) {\n-\t\t\tDRV_LOG(ERR, \"Failed to alloc db memory!\");\n-\t\t\tret = ENODEV;\n-\t\t\tgoto tidyup_error;\n-\t\t}\n-\t\t/* Register the memory. */\n-\t\tpriv->db[i].umem.umem = mlx5_glue->devx_umem_reg(priv->ctx,\n-\t\t\t\t\t\t\tpriv->db[i].ptr,\n-\t\t\t\t\t\t\tMLX5_MAX_DB_SIZE, 7);\n-\t\tif (!priv->db[i].umem.umem) {\n-\t\t\tDRV_LOG(ERR, \"Failed to register memory!\");\n-\t\t\tret = ENODEV;\n-\t\t\tgoto tidyup_error;\n-\t\t}\n-\t\t/* Ensure set all DB memory to 0's before setting up DB. */\n-\t\tmemset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);\n-\t\t/* No data currently in database. */\n-\t\tpriv->db[i].len = 0;\n-\t\tpriv->db[i].active = false;\n-\t\tpriv->db[i].db_assigned_to_eng_num = MLX5_RXP_DB_NOT_ASSIGNED;\n+\t/* Register the memory. */\n+\tmkey->umem = mlx5_glue->devx_umem_reg(priv->ctx, ptr, size, access);\n+\tif (!mkey->umem) {\n+\t\tDRV_LOG(ERR, \"Failed to register memory!\");\n+\t\treturn -ENODEV;\n \t}\n-\treturn 0;\n-tidyup_error:\n-\tfor (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {\n-\t\tif (priv->db[i].umem.umem)\n-\t\t\tmlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);\n-\t\trte_free(priv->db[i].ptr);\n-\t\tpriv->db[i].ptr = NULL;\n+\t/* Create mkey */\n+\tmkey_attr = (struct mlx5_devx_mkey_attr) {\n+\t\t.addr = (uintptr_t)ptr,\n+\t\t.size = (uint32_t)size,\n+\t\t.umem_id = mlx5_os_get_umem_id(mkey->umem),\n+\t\t.pg_access = 1,\n+\t\t.umr_en = 0,\n+\t};\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tif (regex_get_pdn(priv->pd, &mkey_attr.pd) < 0) {\n+\t\tDRV_LOG(ERR, \"Failed to get pdn!\");\n+\t\treturn -ENODEV;\n+\t}\n+#endif\n+\tmkey->mkey = mlx5_devx_cmd_mkey_create(priv->ctx, &mkey_attr);\n+\tif (!mkey->mkey) {\n+\t\tDRV_LOG(ERR, \"Failed to create direct mkey!\");\n+\t\treturn -ENODEV;\n \t}\n-\treturn -ret;\n+\treturn 0;\n+}\n+\n+static inline void\n+rxp_destroy_mkey(struct mlx5_regex_mkey *mkey)\n+{\n+\tif (mkey->mkey)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(mkey->mkey));\n+\tif (mkey->umem)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(mkey->umem));\n }\n \n int\n@@ -89,6 +97,10 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,\n \t\t const char *rule_db, uint32_t rule_db_len)\n {\n \tstruct mlx5_regex_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_regex_mkey mkey;\n+\tuint32_t id;\n+\tint ret;\n+\tvoid *ptr;\n \n \tif (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED) {\n \t\tDRV_LOG(ERR, \"RXP programming mode not set!\");\n@@ -100,8 +112,31 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,\n \t}\n \tif (rule_db_len == 0)\n \t\treturn -EINVAL;\n+\t/* copy rules - rules have to be 4KB aligned. */\n+\tptr = rte_malloc(\"\", rule_db_len, 1 << 12);\n+\tif (!ptr) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate rules file memory.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\trte_memcpy(ptr, rule_db, rule_db_len);\n+\t/* Register umem and create rof mkey. */\n+\tret = rxp_create_mkey(priv, ptr, rule_db_len, /*access=*/7, &mkey);\n+\tif (ret < 0)\n+\t\treturn ret;\n \n-\treturn 0;\n+\tfor (id = 0; id < priv->nb_engines; id++) {\n+\t\tret = mlx5_devx_regex_rules_program(priv->ctx, id,\n+\t\t\tmkey.mkey->id, rule_db_len, (uintptr_t)ptr);\n+\t\tif (ret < 0) {\n+\t\t\tDRV_LOG(ERR, \"Failed to program rxp rules.\");\n+\t\t\tret = -ENODEV;\n+\t\t\tbreak;\n+\t\t}\n+\t\tret = 0;\n+\t}\n+\trxp_destroy_mkey(&mkey);\n+\trte_free(ptr);\n+\treturn ret;\n }\n \n int\n@@ -123,12 +158,6 @@ mlx5_regex_configure(struct rte_regexdev *dev,\n \t\treturn -rte_errno;\n \t}\n \tpriv->nb_max_matches = cfg->nb_max_matches;\n-\t/* Setup rxp db memories. */\n-\tif (rxp_db_setup(priv)) {\n-\t\tDRV_LOG(ERR, \"Failed to setup RXP db memory\");\n-\t\trte_errno = ENOMEM;\n-\t\treturn -rte_errno;\n-\t}\n \tif (cfg->rule_db != NULL) {\n \t\tret = mlx5_regex_rules_db_import(dev, cfg->rule_db,\n \t\t\t\t\t\t cfg->rule_db_len);\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.h b/drivers/regex/mlx5/mlx5_rxp.h\nindex 9686e24cdb..254e9cfa2b 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.h\n+++ b/drivers/regex/mlx5/mlx5_rxp.h\n@@ -129,9 +129,9 @@ enum mlx5_rxp_program_mode {\n #define MLX5_RXP_EM_COUNT 1u /* Extra External Memories to use. */\n #define MLX5_RXP_DB_NOT_ASSIGNED 0xFF\n \n-struct mlx5_regex_umem {\n+struct mlx5_regex_mkey {\n \tstruct mlx5dv_devx_umem *umem;\n-\tuint32_t id;\n+\tstruct mlx5_devx_obj *mkey;\n \tuint64_t offset;\n };\n \n", "prefixes": [ "05/10" ] }