Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/102321/?format=api
{ "id": 102321, "url": "http://patches.dpdk.org/api/patches/102321/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211019205602.3188203-18-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211019205602.3188203-18-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211019205602.3188203-18-michaelba@nvidia.com", "date": "2021-10-19T20:56:01", "name": "[v3,17/18] common/mlx5: support device DMA map and unmap", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "879512a4bcbc4ba1800bc0249311074ad69a9340", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211019205602.3188203-18-michaelba@nvidia.com/mbox/", "series": [ { "id": 19808, "url": "http://patches.dpdk.org/api/series/19808/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19808", "date": "2021-10-19T20:55:44", "name": "mlx5: sharing global MR cache between drivers", "version": 3, "mbox": "http://patches.dpdk.org/series/19808/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102321/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102321/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3133AA0C41;\n\tTue, 19 Oct 2021 22:58:26 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EF32C41194;\n\tTue, 19 Oct 2021 22:57:22 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2070.outbound.protection.outlook.com [40.107.244.70])\n by mails.dpdk.org (Postfix) with ESMTP id 08FCD41185\n for <dev@dpdk.org>; Tue, 19 Oct 2021 22:57:05 +0200 (CEST)", "from BN0PR02CA0015.namprd02.prod.outlook.com (2603:10b6:408:e4::20)\n by CH2PR12MB3928.namprd12.prod.outlook.com (2603:10b6:610:23::11)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.15; Tue, 19 Oct\n 2021 20:57:02 +0000", "from BN8NAM11FT033.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:e4:cafe::31) by BN0PR02CA0015.outlook.office365.com\n (2603:10b6:408:e4::20) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.15 via Frontend\n Transport; Tue, 19 Oct 2021 20:57:02 +0000", "from mail.nvidia.com (216.228.112.34) by\n BN8NAM11FT033.mail.protection.outlook.com (10.13.177.149) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 20:57:02 +0000", "from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct\n 2021 20:56:52 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=H/JxXTohrH+eV/JmiacMfO+ozK4UhGRVi3RzJg8Rz8MD1a6KyxvH8zEIOv64PIAEyrqis6AXvvrwgEVWkY08nT4u+ohlu8KQSjYOw8Y/Fa8j7c8Zd8dGPUqC6WnJ4BA71aYmbmy7pIsPN0TpdNutUVMk2ho59trG+73AtGjbYKIcld61IBwGggZwIMAHHzPWrlO7Wz9xBMMQs/InX82/iP2+fZsrtV5QxvUBB1wOMshD1hoEhH/JE3G+g3npCqMHnTSdzs/91j4TFnHzx9cbK/wR5bY4bhfi1zjsNXYTdxc4L/CmNJYLTLUQkEjck6XwTxV0PKSkGoj1yqRVcb8wvA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=6aD9ZFVsDmuSloouxqYvXoK9/MHrf06SDxHixyj/v3Q=;\n b=boPFvxIdrFStgpH+PQLBsBRkGe1dN03sbCV7JE/SqaLspnE9uShVEOWy2PxnHBNo9M/3P1AJ7utAMq3yJbeIVb258BYIxMRc7wBUdeomMJ1hMBqFC48bdRzSx+xajchqHedWqTHvnVt0WjzGt8dvkduO22FyhDmAR9Vvva1mjuNn+HEt5DPfLWpEguN34y+ZNr8btJEuPkwP/i803JOHA8EXZQmdXcMWEVX4h84F0Avejqxo3nwrHgZtx8/Cn1VhCwffvC2gqbCbwjzEawJ4S5V1YADxgHwzSfyUIL0eNho7sqI6Llx4dUxvD+CwB+gDwbtMojOPHc1ND1udCgxyfg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=quarantine pct=100) action=none\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=6aD9ZFVsDmuSloouxqYvXoK9/MHrf06SDxHixyj/v3Q=;\n b=DO0jnpCZ+xrycn4AvgmxCWiVIQaR0Y0oLnZz/0X0LdfMLhqJE5gMyXjurSwU8x29nAp36D4mKN+xDL67gCnLp3ouKlbrRvrdPRn/axPuKVJ+zbu9GjFiT4Mfo8uJIwDgZR3cgaWNzz8cwXofmWkfTSGVyW7Ri7ZduX+pZEgYvZdStjlcr3B82GUQMm+OUJJary6bAxxPDRJ4WIi4Wh92IVrkXEuUbCPbr9Z81fp72EzpCX+vq/ParxgYqWw4Wb+i/LrZwUXmQ31B1RDeLCv0FXxTEyDh3ANm6KpI0lajtY4jPaShai+DABhs6fHC2vfKxFsWIHomZOHdfOK2IdeJ7Q==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>,\n Michael Baum <michaelba@oss.nvidia.com>", "Date": "Tue, 19 Oct 2021 23:56:01 +0300", "Message-ID": "<20211019205602.3188203-18-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211019205602.3188203-1-michaelba@nvidia.com>", "References": "<20211006220350.2357487-1-michaelba@nvidia.com>\n <20211019205602.3188203-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "7cc7b2be-d98e-4f7a-87c2-08d993430037", "X-MS-TrafficTypeDiagnostic": "CH2PR12MB3928:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <CH2PR12MB3928FDE02F8D00404ACED39ACCBD9@CH2PR12MB3928.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2201;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n m6PmI4E6iXtPQI62ZVMN92xhmUAYrDmX0pKSfYRHkwiTS+ubsArxlAP2lGirRPIkOorDsh2w3WUe91k7UMCTJfMCGbefeUeTpQlQrOS0jhttA3rVpLmt8YGZPKg3a4QwQUwiNiVdKzBVnJe3zRWqNsJXGTKv7vPwf1JGTZcs/0//QI78QEo5IqNGwNetjTCSvMKJBs4AOrVZ0IFuybwxBzpSsaKEhz7pC75dWtSK1eaj2ds0TxySq1CY9nD/t42iBV2QzF2Y2qboF80FlrRGmBstUglWdXa356MP3BnDBDUKfIAojkyHZcsQSHW/G9llCDF18EjqNzdCPJN+9kNRPRmV2e0uQDSlNldnVMkPct9DGCHb0IIqTf08Rb9ne7BtCQTOyVEDjlGbwc7ipEPvyk5Vyjn+lbnySmZabZiMuxlqdyy8y0kuEtM4RDFhvmfxFl/wuIYwMuBMc7Vj6/DOAieU+T8s982X0DxRGoJBNKt20kb/nKtYjDloGD3BsHs54afj6SQ9ZKDE0nnoBlYv3Qi/CjJ0j6YoI7+bn3n5ptrXC/ruV9WrpeHVJEk8zxLGju4U3wpXm67Ri47XYN65B89kCgBHTOP0R9ONvYnBmEBJISBfcnpD6mYhKAQYCQTAuETybD2BifW6X6Dlg91r50jOhsMY1e7rlRcJfZ9sERmup0BltsTaoCYQPgIQas9HWHKqOL75tuD8od1mGXqQ7g==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(186003)(8676002)(16526019)(336012)(4326008)(8936002)(26005)(6286002)(70206006)(70586007)(5660300002)(426003)(2616005)(6916009)(316002)(36906005)(508600001)(7696005)(54906003)(2876002)(55016002)(356005)(2906002)(7636003)(82310400003)(36756003)(83380400001)(86362001)(1076003)(6666004)(36860700001)(47076005)(107886003)(30864003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Oct 2021 20:57:02.2428 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7cc7b2be-d98e-4f7a-87c2-08d993430037", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT033.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB3928", "Subject": "[dpdk-dev] [PATCH v3 17/18] common/mlx5: support device DMA map and\n unmap", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nSince MR management has moved to the common area, there is no longer a\nneed for the DMA map and unmap function for each driver.\nThis patch share those functions. For most drivers it supports these\noperations for the first time.\n\nSigned-off-by: Michael Baum <michaelba@oss.nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common.c | 144 +++++++++++++++++----------\n drivers/common/mlx5/mlx5_common.h | 41 --------\n drivers/common/mlx5/mlx5_common_mr.c | 2 +-\n drivers/common/mlx5/mlx5_common_mr.h | 25 ++---\n drivers/common/mlx5/version.map | 9 --\n drivers/net/mlx5/mlx5.c | 2 -\n drivers/net/mlx5/mlx5_mr.c | 132 ------------------------\n 7 files changed, 100 insertions(+), 255 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c\nindex d6acf87493..0ed1477eb8 100644\n--- a/drivers/common/mlx5/mlx5_common.c\n+++ b/drivers/common/mlx5/mlx5_common.c\n@@ -258,12 +258,6 @@ is_valid_class_combination(uint32_t user_classes)\n \treturn 0;\n }\n \n-static bool\n-device_class_enabled(const struct mlx5_common_device *device, uint32_t class)\n-{\n-\treturn (device->classes_loaded & class) > 0;\n-}\n-\n static bool\n mlx5_bus_match(const struct mlx5_class_driver *drv,\n \t const struct rte_device *dev)\n@@ -597,62 +591,106 @@ mlx5_common_dev_remove(struct rte_device *eal_dev)\n \treturn ret;\n }\n \n+/**\n+ * Callback to DMA map external memory to a device.\n+ *\n+ * @param rte_dev\n+ * Pointer to the generic device.\n+ * @param addr\n+ * Starting virtual address of memory to be mapped.\n+ * @param iova\n+ * Starting IOVA address of memory to be mapped.\n+ * @param len\n+ * Length of memory segment being mapped.\n+ *\n+ * @return\n+ * 0 on success, negative value on error.\n+ */\n int\n-mlx5_common_dev_dma_map(struct rte_device *dev, void *addr, uint64_t iova,\n-\t\t\tsize_t len)\n+mlx5_common_dev_dma_map(struct rte_device *rte_dev, void *addr,\n+\t\t\tuint64_t iova __rte_unused, size_t len)\n {\n-\tstruct mlx5_class_driver *driver = NULL;\n-\tstruct mlx5_class_driver *temp;\n-\tstruct mlx5_common_device *mdev;\n-\tint ret = -EINVAL;\n-\n-\tmdev = to_mlx5_device(dev);\n-\tif (!mdev)\n-\t\treturn -ENODEV;\n-\tTAILQ_FOREACH(driver, &drivers_list, next) {\n-\t\tif (!device_class_enabled(mdev, driver->drv_class) ||\n-\t\t driver->dma_map == NULL)\n-\t\t\tcontinue;\n-\t\tret = driver->dma_map(dev, addr, iova, len);\n-\t\tif (ret)\n-\t\t\tgoto map_err;\n+\tstruct mlx5_common_device *dev;\n+\tstruct mlx5_mr *mr;\n+\n+\tdev = to_mlx5_device(rte_dev);\n+\tif (!dev) {\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"Unable to find matching mlx5 device to device %s\",\n+\t\t\trte_dev->name);\n+\t\trte_errno = ENODEV;\n+\t\treturn -1;\n \t}\n-\treturn ret;\n-map_err:\n-\tTAILQ_FOREACH(temp, &drivers_list, next) {\n-\t\tif (temp == driver)\n-\t\t\tbreak;\n-\t\tif (device_class_enabled(mdev, temp->drv_class) &&\n-\t\t temp->dma_map && temp->dma_unmap)\n-\t\t\ttemp->dma_unmap(dev, addr, iova, len);\n+\tmr = mlx5_create_mr_ext(dev->pd, (uintptr_t)addr, len,\n+\t\t\t\tSOCKET_ID_ANY, dev->mr_scache.reg_mr_cb);\n+\tif (!mr) {\n+\t\tDRV_LOG(WARNING, \"Device %s unable to DMA map\", rte_dev->name);\n+\t\trte_errno = EINVAL;\n+\t\treturn -1;\n \t}\n-\treturn ret;\n+\trte_rwlock_write_lock(&dev->mr_scache.rwlock);\n+\tLIST_INSERT_HEAD(&dev->mr_scache.mr_list, mr, mr);\n+\t/* Insert to the global cache table. */\n+\tmlx5_mr_insert_cache(&dev->mr_scache, mr);\n+\trte_rwlock_write_unlock(&dev->mr_scache.rwlock);\n+\treturn 0;\n }\n \n+/**\n+ * Callback to DMA unmap external memory to a device.\n+ *\n+ * @param rte_dev\n+ * Pointer to the generic device.\n+ * @param addr\n+ * Starting virtual address of memory to be unmapped.\n+ * @param iova\n+ * Starting IOVA address of memory to be unmapped.\n+ * @param len\n+ * Length of memory segment being unmapped.\n+ *\n+ * @return\n+ * 0 on success, negative value on error.\n+ */\n int\n-mlx5_common_dev_dma_unmap(struct rte_device *dev, void *addr, uint64_t iova,\n-\t\t\t size_t len)\n+mlx5_common_dev_dma_unmap(struct rte_device *rte_dev, void *addr,\n+\t\t\t uint64_t iova __rte_unused, size_t len __rte_unused)\n {\n-\tstruct mlx5_class_driver *driver;\n-\tstruct mlx5_common_device *mdev;\n-\tint local_ret = -EINVAL;\n-\tint ret = 0;\n-\n-\tmdev = to_mlx5_device(dev);\n-\tif (!mdev)\n-\t\treturn -ENODEV;\n-\t/* There is no unmap error recovery in current implementation. */\n-\tTAILQ_FOREACH_REVERSE(driver, &drivers_list, mlx5_drivers, next) {\n-\t\tif (!device_class_enabled(mdev, driver->drv_class) ||\n-\t\t driver->dma_unmap == NULL)\n-\t\t\tcontinue;\n-\t\tlocal_ret = driver->dma_unmap(dev, addr, iova, len);\n-\t\tif (local_ret && (ret == 0))\n-\t\t\tret = local_ret;\n+\tstruct mlx5_common_device *dev;\n+\tstruct mr_cache_entry entry;\n+\tstruct mlx5_mr *mr;\n+\n+\tdev = to_mlx5_device(rte_dev);\n+\tif (!dev) {\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"Unable to find matching mlx5 device to device %s.\",\n+\t\t\trte_dev->name);\n+\t\trte_errno = ENODEV;\n+\t\treturn -1;\n \t}\n-\tif (local_ret)\n-\t\tret = local_ret;\n-\treturn ret;\n+\trte_rwlock_read_lock(&dev->mr_scache.rwlock);\n+\tmr = mlx5_mr_lookup_list(&dev->mr_scache, &entry, (uintptr_t)addr);\n+\tif (!mr) {\n+\t\trte_rwlock_read_unlock(&dev->mr_scache.rwlock);\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"Address 0x%\" PRIxPTR \" wasn't registered to device %s\",\n+\t\t\t(uintptr_t)addr, rte_dev->name);\n+\t\trte_errno = EINVAL;\n+\t\treturn -1;\n+\t}\n+\tLIST_REMOVE(mr, mr);\n+\tDRV_LOG(DEBUG, \"MR(%p) is removed from list.\", (void *)mr);\n+\tmlx5_mr_free(mr, dev->mr_scache.dereg_mr_cb);\n+\tmlx5_mr_rebuild_cache(&dev->mr_scache);\n+\t/*\n+\t * No explicit wmb is needed after updating dev_gen due to\n+\t * store-release ordering in unlock that provides the\n+\t * implicit barrier at the software visible level.\n+\t */\n+\t++dev->mr_scache.dev_gen;\n+\tDRV_LOG(DEBUG, \"Broadcasting local cache flush, gen=%d.\",\n+\t\tdev->mr_scache.dev_gen);\n+\trte_rwlock_read_unlock(&dev->mr_scache.rwlock);\n+\treturn 0;\n }\n \n void\ndiff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex 1a6b8c0f52..72ff0ff809 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -364,44 +364,6 @@ typedef int (mlx5_class_driver_probe_t)(struct mlx5_common_device *dev);\n */\n typedef int (mlx5_class_driver_remove_t)(struct mlx5_common_device *dev);\n \n-/**\n- * Driver-specific DMA mapping. After a successful call the device\n- * will be able to read/write from/to this segment.\n- *\n- * @param dev\n- * Pointer to the device.\n- * @param addr\n- * Starting virtual address of memory to be mapped.\n- * @param iova\n- * Starting IOVA address of memory to be mapped.\n- * @param len\n- * Length of memory segment being mapped.\n- * @return\n- * - 0 On success.\n- * - Negative value and rte_errno is set otherwise.\n- */\n-typedef int (mlx5_class_driver_dma_map_t)(struct rte_device *dev, void *addr,\n-\t\t\t\t\t uint64_t iova, size_t len);\n-\n-/**\n- * Driver-specific DMA un-mapping. After a successful call the device\n- * will not be able to read/write from/to this segment.\n- *\n- * @param dev\n- * Pointer to the device.\n- * @param addr\n- * Starting virtual address of memory to be unmapped.\n- * @param iova\n- * Starting IOVA address of memory to be unmapped.\n- * @param len\n- * Length of memory segment being unmapped.\n- * @return\n- * - 0 On success.\n- * - Negative value and rte_errno is set otherwise.\n- */\n-typedef int (mlx5_class_driver_dma_unmap_t)(struct rte_device *dev, void *addr,\n-\t\t\t\t\t uint64_t iova, size_t len);\n-\n /** Device already probed can be probed again to check for new ports. */\n #define MLX5_DRV_PROBE_AGAIN 0x0004\n \n@@ -414,9 +376,6 @@ struct mlx5_class_driver {\n \tconst char *name; /**< Driver name. */\n \tmlx5_class_driver_probe_t *probe; /**< Device probe function. */\n \tmlx5_class_driver_remove_t *remove; /**< Device remove function. */\n-\tmlx5_class_driver_dma_map_t *dma_map; /**< Device DMA map function. */\n-\tmlx5_class_driver_dma_unmap_t *dma_unmap;\n-\t/**< Device DMA unmap function. */\n \tconst struct rte_pci_id *id_table; /**< ID table, NULL terminated. */\n \tuint32_t probe_again:1;\n \t/**< Device already probed can be probed again to check new device. */\ndiff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c\nindex d63e973b60..5bfddac08e 100644\n--- a/drivers/common/mlx5/mlx5_common_mr.c\n+++ b/drivers/common/mlx5/mlx5_common_mr.c\n@@ -455,7 +455,7 @@ mlx5_mr_lookup_list(struct mlx5_mr_share_cache *share_cache,\n * @return\n * Searched LKey on success, UINT32_MAX on failure and rte_errno is set.\n */\n-uint32_t\n+static uint32_t\n mlx5_mr_lookup_cache(struct mlx5_mr_share_cache *share_cache,\n \t\t struct mr_cache_entry *entry, uintptr_t addr)\n {\ndiff --git a/drivers/common/mlx5/mlx5_common_mr.h b/drivers/common/mlx5/mlx5_common_mr.h\nindex 0bc3519fd9..8a7af05ca5 100644\n--- a/drivers/common/mlx5/mlx5_common_mr.h\n+++ b/drivers/common/mlx5/mlx5_common_mr.h\n@@ -124,12 +124,13 @@ mlx5_mr_lookup_lkey(struct mr_cache_entry *lkp_tbl, uint16_t *cached_idx,\n \treturn UINT32_MAX;\n }\n \n+/* mlx5_common_mr.c */\n+\n __rte_internal\n int mlx5_mr_ctrl_init(struct mlx5_mr_ctrl *mr_ctrl, uint32_t *dev_gen_ptr,\n \t\t int socket);\n __rte_internal\n void mlx5_mr_btree_free(struct mlx5_mr_btree *bt);\n-__rte_internal\n void mlx5_mr_btree_dump(struct mlx5_mr_btree *bt __rte_unused);\n __rte_internal\n uint32_t mlx5_mr_addr2mr_bh(void *pd, struct mlx5_mp_id *mp_id,\n@@ -142,36 +143,30 @@ uint32_t mlx5_mr_mempool2mr_bh(struct mlx5_mr_share_cache *share_cache,\n \t\t\t struct rte_mempool *mp, uintptr_t addr);\n void mlx5_mr_release_cache(struct mlx5_mr_share_cache *mr_cache);\n int mlx5_mr_create_cache(struct mlx5_mr_share_cache *share_cache, int socket);\n-__rte_internal\n void mlx5_mr_dump_cache(struct mlx5_mr_share_cache *share_cache __rte_unused);\n-__rte_internal\n void mlx5_mr_rebuild_cache(struct mlx5_mr_share_cache *share_cache);\n __rte_internal\n void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);\n void mlx5_free_mr_by_addr(struct mlx5_mr_share_cache *share_cache,\n \t\t\t const char *ibdev_name, const void *addr, size_t len);\n-__rte_internal\n-int\n-mlx5_mr_insert_cache(struct mlx5_mr_share_cache *share_cache,\n-\t\t struct mlx5_mr *mr);\n-__rte_internal\n-uint32_t\n-mlx5_mr_lookup_cache(struct mlx5_mr_share_cache *share_cache,\n-\t\t struct mr_cache_entry *entry, uintptr_t addr);\n-__rte_internal\n+int mlx5_mr_insert_cache(struct mlx5_mr_share_cache *share_cache,\n+\t\t\t struct mlx5_mr *mr);\n struct mlx5_mr *\n mlx5_mr_lookup_list(struct mlx5_mr_share_cache *share_cache,\n \t\t struct mr_cache_entry *entry, uintptr_t addr);\n-__rte_internal\n struct mlx5_mr *\n mlx5_create_mr_ext(void *pd, uintptr_t addr, size_t len, int socket_id,\n \t\t mlx5_reg_mr_t reg_mr_cb);\n+void mlx5_mr_free(struct mlx5_mr *mr, mlx5_dereg_mr_t dereg_mr_cb);\n __rte_internal\n uint32_t\n mlx5_mr_create_primary(void *pd,\n \t\t struct mlx5_mr_share_cache *share_cache,\n \t\t struct mr_cache_entry *entry, uintptr_t addr,\n \t\t unsigned int mr_ext_memseg_en);\n+\n+/* mlx5_common_verbs.c */\n+\n __rte_internal\n int\n mlx5_common_verbs_reg_mr(void *pd, void *addr, size_t length,\n@@ -183,10 +178,6 @@ mlx5_common_verbs_dereg_mr(struct mlx5_pmd_mr *pmd_mr);\n void\n mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, mlx5_dereg_mr_t *dereg_mr_cb);\n \n-__rte_internal\n-void\n-mlx5_mr_free(struct mlx5_mr *mr, mlx5_dereg_mr_t dereg_mr_cb);\n-\n __rte_internal\n int\n mlx5_mr_mempool_register(struct mlx5_mr_share_cache *share_cache, void *pd,\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex 12128e4738..28a0944a93 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -12,8 +12,6 @@ INTERNAL {\n \tmlx5_common_verbs_reg_mr; # WINDOWS_NO_EXPORT\n \tmlx5_common_verbs_dereg_mr; # WINDOWS_NO_EXPORT\n \n-\tmlx5_create_mr_ext;\n-\n \tmlx5_dev_is_pci;\n \n \tmlx5_devx_alloc_uar; # WINDOWS_NO_EXPORT\n@@ -107,18 +105,11 @@ INTERNAL {\n \tmlx5_mp_uninit_secondary; # WINDOWS_NO_EXPORT\n \n \tmlx5_mr_addr2mr_bh;\n-\tmlx5_mr_btree_dump;\n \tmlx5_mr_btree_free;\n \tmlx5_mr_create_primary;\n mlx5_mr_ctrl_init;\n-\tmlx5_mr_dump_cache;\n \tmlx5_mr_flush_local_cache;\n-\tmlx5_mr_free;\n-\tmlx5_mr_insert_cache;\n-\tmlx5_mr_lookup_cache;\n-\tmlx5_mr_lookup_list;\n \tmlx5_mr_mb2mr;\n-\tmlx5_mr_rebuild_cache;\n \n \tmlx5_nl_allmulti; # WINDOWS_NO_EXPORT\n \tmlx5_nl_ifindex; # WINDOWS_NO_EXPORT\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 91aa5c0c75..17113be873 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -2589,8 +2589,6 @@ static struct mlx5_class_driver mlx5_net_driver = {\n \t.id_table = mlx5_pci_id_map,\n \t.probe = mlx5_os_net_probe,\n \t.remove = mlx5_net_remove,\n-\t.dma_map = mlx5_net_dma_map,\n-\t.dma_unmap = mlx5_net_dma_unmap,\n \t.probe_again = 1,\n \t.intr_lsc = 1,\n \t.intr_rmv = 1,\ndiff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\nindex 38780202dc..ac3d8e2492 100644\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ b/drivers/net/mlx5/mlx5_mr.c\n@@ -87,135 +87,3 @@ mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb)\n \t}\n \treturn mlx5_tx_addr2mr_bh(txq, addr);\n }\n-\n-/**\n- * Finds the first ethdev that match the device.\n- * The existence of multiple ethdev per pci device is only with representors.\n- * On such case, it is enough to get only one of the ports as they all share\n- * the same ibv context.\n- *\n- * @param dev\n- * Pointer to the device.\n- *\n- * @return\n- * Pointer to the ethdev if found, NULL otherwise.\n- */\n-static struct rte_eth_dev *\n-dev_to_eth_dev(struct rte_device *dev)\n-{\n-\tuint16_t port_id;\n-\n-\tport_id = rte_eth_find_next_of(0, dev);\n-\tif (port_id == RTE_MAX_ETHPORTS)\n-\t\treturn NULL;\n-\treturn &rte_eth_devices[port_id];\n-}\n-\n-/**\n- * Callback to DMA map external memory to a device.\n- *\n- * @param rte_dev\n- * Pointer to the generic device.\n- * @param addr\n- * Starting virtual address of memory to be mapped.\n- * @param iova\n- * Starting IOVA address of memory to be mapped.\n- * @param len\n- * Length of memory segment being mapped.\n- *\n- * @return\n- * 0 on success, negative value on error.\n- */\n-int\n-mlx5_net_dma_map(struct rte_device *rte_dev, void *addr,\n-\t\t uint64_t iova __rte_unused, size_t len)\n-{\n-\tstruct rte_eth_dev *dev;\n-\tstruct mlx5_mr *mr;\n-\tstruct mlx5_priv *priv;\n-\tstruct mlx5_common_device *cdev;\n-\n-\tdev = dev_to_eth_dev(rte_dev);\n-\tif (!dev) {\n-\t\tDRV_LOG(WARNING, \"unable to find matching ethdev \"\n-\t\t\t\t \"to device %s\", rte_dev->name);\n-\t\trte_errno = ENODEV;\n-\t\treturn -1;\n-\t}\n-\tpriv = dev->data->dev_private;\n-\tcdev = priv->sh->cdev;\n-\tmr = mlx5_create_mr_ext(cdev->pd, (uintptr_t)addr, len,\n-\t\t\t\tSOCKET_ID_ANY, cdev->mr_scache.reg_mr_cb);\n-\tif (!mr) {\n-\t\tDRV_LOG(WARNING,\n-\t\t\t\"port %u unable to dma map\", dev->data->port_id);\n-\t\trte_errno = EINVAL;\n-\t\treturn -1;\n-\t}\n-\trte_rwlock_write_lock(&cdev->mr_scache.rwlock);\n-\tLIST_INSERT_HEAD(&cdev->mr_scache.mr_list, mr, mr);\n-\t/* Insert to the global cache table. */\n-\tmlx5_mr_insert_cache(&cdev->mr_scache, mr);\n-\trte_rwlock_write_unlock(&cdev->mr_scache.rwlock);\n-\treturn 0;\n-}\n-\n-/**\n- * Callback to DMA unmap external memory to a device.\n- *\n- * @param rte_dev\n- * Pointer to the generic device.\n- * @param addr\n- * Starting virtual address of memory to be unmapped.\n- * @param iova\n- * Starting IOVA address of memory to be unmapped.\n- * @param len\n- * Length of memory segment being unmapped.\n- *\n- * @return\n- * 0 on success, negative value on error.\n- */\n-int\n-mlx5_net_dma_unmap(struct rte_device *rte_dev, void *addr,\n-\t\t uint64_t iova __rte_unused, size_t len __rte_unused)\n-{\n-\tstruct rte_eth_dev *dev;\n-\tstruct mlx5_priv *priv;\n-\tstruct mlx5_common_device *cdev;\n-\tstruct mlx5_mr *mr;\n-\tstruct mr_cache_entry entry;\n-\n-\tdev = dev_to_eth_dev(rte_dev);\n-\tif (!dev) {\n-\t\tDRV_LOG(WARNING, \"unable to find matching ethdev to device %s\",\n-\t\t\trte_dev->name);\n-\t\trte_errno = ENODEV;\n-\t\treturn -1;\n-\t}\n-\tpriv = dev->data->dev_private;\n-\tcdev = priv->sh->cdev;\n-\trte_rwlock_write_lock(&cdev->mr_scache.rwlock);\n-\tmr = mlx5_mr_lookup_list(&cdev->mr_scache, &entry, (uintptr_t)addr);\n-\tif (!mr) {\n-\t\trte_rwlock_write_unlock(&cdev->mr_scache.rwlock);\n-\t\tDRV_LOG(WARNING, \"address 0x%\" PRIxPTR \" wasn't registered to device %s\",\n-\t\t\t(uintptr_t)addr, rte_dev->name);\n-\t\trte_errno = EINVAL;\n-\t\treturn -1;\n-\t}\n-\tLIST_REMOVE(mr, mr);\n-\tDRV_LOG(DEBUG, \"port %u remove MR(%p) from list\", dev->data->port_id,\n-\t (void *)mr);\n-\tmlx5_mr_free(mr, cdev->mr_scache.dereg_mr_cb);\n-\tmlx5_mr_rebuild_cache(&cdev->mr_scache);\n-\t/*\n-\t * No explicit wmb is needed after updating dev_gen due to\n-\t * store-release ordering in unlock that provides the\n-\t * implicit barrier at the software visible level.\n-\t */\n-\t++cdev->mr_scache.dev_gen;\n-\tDRV_LOG(DEBUG, \"broadcasting local cache flush, gen=%d\",\n-\t cdev->mr_scache.dev_gen);\n-\trte_rwlock_write_unlock(&cdev->mr_scache.rwlock);\n-\treturn 0;\n-}\n", "prefixes": [ "v3", "17/18" ] }