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GET /api/patches/102316/?format=api
{ "id": 102316, "url": "http://patches.dpdk.org/api/patches/102316/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211019205602.3188203-13-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211019205602.3188203-13-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211019205602.3188203-13-michaelba@nvidia.com", "date": "2021-10-19T20:55:56", "name": "[v3,12/18] net/mlx5: remove redundancy in MR file", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7fed9f6abf7c46a7289479c58dc553d33825b66b", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211019205602.3188203-13-michaelba@nvidia.com/mbox/", "series": [ { "id": 19808, "url": "http://patches.dpdk.org/api/series/19808/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19808", "date": "2021-10-19T20:55:44", "name": "mlx5: sharing global MR cache between drivers", "version": 3, "mbox": "http://patches.dpdk.org/series/19808/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102316/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102316/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 69011A0C41;\n\tTue, 19 Oct 2021 22:57:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9CD414117D;\n\tTue, 19 Oct 2021 22:57:03 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2075.outbound.protection.outlook.com [40.107.223.75])\n by mails.dpdk.org (Postfix) with ESMTP id 5C33941176\n for <dev@dpdk.org>; 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CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(8676002)(5660300002)(83380400001)(55016002)(508600001)(86362001)(36860700001)(2906002)(82310400003)(26005)(47076005)(36756003)(6916009)(16526019)(356005)(316002)(2616005)(7696005)(4326008)(70586007)(70206006)(54906003)(2876002)(336012)(107886003)(7636003)(8936002)(186003)(1076003)(426003)(6286002)(6666004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Oct 2021 20:56:45.1700 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 46c4e44b-ad66-4b8d-0d63-08d99342f5f7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT035.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1575", "Subject": "[dpdk-dev] [PATCH v3 12/18] net/mlx5: remove redundancy in MR file", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nThis patch remove two redundant things from MR file:\n\n1. mr_find_contig_memsegs_data structure which is moved to common file\n before.\n2. External memory mechanism - mlx5_tx_update_ext_mp function.\n Since commit [1] which added support for DMA map and unmap, external\n mem must be configured by the user using rte_mem_map function and no\n need to handle this in pmd.\n\n[1]\ncommit 989e999d9305\n(\"net/mlx5: support PCI device DMA map and unmap\")\n\nSigned-off-by: Michael Baum <michaelba@oss.nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_mr.c | 142 +------------------------------------\n drivers/net/mlx5/mlx5_tx.h | 2 -\n 2 files changed, 1 insertion(+), 143 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\nindex 4d884f7295..9ce973d95c 100644\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ b/drivers/net/mlx5/mlx5_mr.c\n@@ -17,19 +17,6 @@\n #include \"mlx5_rx.h\"\n #include \"mlx5_tx.h\"\n \n-struct mr_find_contig_memsegs_data {\n-\tuintptr_t addr;\n-\tuintptr_t start;\n-\tuintptr_t end;\n-\tconst struct rte_memseg_list *msl;\n-};\n-\n-struct mr_update_mp_data {\n-\tstruct rte_eth_dev *dev;\n-\tstruct mlx5_mr_ctrl *mr_ctrl;\n-\tint ret;\n-};\n-\n /**\n * Callback for memory event. This can be called from both primary and secondary\n * process.\n@@ -134,70 +121,7 @@ mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb)\n \t\t}\n \t\t/* Fallback for generic mechanism in corner cases. */\n \t}\n-\tlkey = mlx5_tx_addr2mr_bh(txq, addr);\n-\tif (lkey == UINT32_MAX && rte_errno == ENXIO) {\n-\t\t/* Mempool may have externally allocated memory. */\n-\t\treturn mlx5_tx_update_ext_mp(txq, addr, mlx5_mb2mp(mb));\n-\t}\n-\treturn lkey;\n-}\n-\n-/**\n- * Called during rte_mempool_mem_iter() by mlx5_mr_update_ext_mp().\n- *\n- * Externally allocated chunk is registered and a MR is created for the chunk.\n- * The MR object is added to the global list. If memseg list of a MR object\n- * (mr->msl) is null, the MR object can be regarded as externally allocated\n- * memory.\n- *\n- * Once external memory is registered, it should be static. If the memory is\n- * freed and the virtual address range has different physical memory mapped\n- * again, it may cause crash on device due to the wrong translation entry. PMD\n- * can't track the free event of the external memory for now.\n- */\n-static void\n-mlx5_mr_update_ext_mp_cb(struct rte_mempool *mp, void *opaque,\n-\t\t\t struct rte_mempool_memhdr *memhdr,\n-\t\t\t unsigned mem_idx __rte_unused)\n-{\n-\tstruct mr_update_mp_data *data = opaque;\n-\tstruct rte_eth_dev *dev = data->dev;\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n-\tstruct mlx5_mr_ctrl *mr_ctrl = data->mr_ctrl;\n-\tstruct mlx5_mr *mr = NULL;\n-\tuintptr_t addr = (uintptr_t)memhdr->addr;\n-\tsize_t len = memhdr->len;\n-\tstruct mr_cache_entry entry;\n-\tuint32_t lkey;\n-\n-\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n-\t/* If already registered, it should return. */\n-\trte_rwlock_read_lock(&sh->share_cache.rwlock);\n-\tlkey = mlx5_mr_lookup_cache(&sh->share_cache, &entry, addr);\n-\trte_rwlock_read_unlock(&sh->share_cache.rwlock);\n-\tif (lkey != UINT32_MAX)\n-\t\treturn;\n-\tDRV_LOG(DEBUG, \"port %u register MR for chunk #%d of mempool (%s)\",\n-\t\tdev->data->port_id, mem_idx, mp->name);\n-\tmr = mlx5_create_mr_ext(sh->cdev->pd, addr, len, mp->socket_id,\n-\t\t\t\tsh->share_cache.reg_mr_cb);\n-\tif (!mr) {\n-\t\tDRV_LOG(WARNING,\n-\t\t\t\"port %u unable to allocate a new MR of\"\n-\t\t\t\" mempool (%s).\",\n-\t\t\tdev->data->port_id, mp->name);\n-\t\tdata->ret = -1;\n-\t\treturn;\n-\t}\n-\trte_rwlock_write_lock(&sh->share_cache.rwlock);\n-\tLIST_INSERT_HEAD(&sh->share_cache.mr_list, mr, mr);\n-\t/* Insert to the global cache table. */\n-\tmlx5_mr_insert_cache(&sh->share_cache, mr);\n-\trte_rwlock_write_unlock(&sh->share_cache.rwlock);\n-\t/* Insert to the local cache table */\n-\tmlx5_mr_addr2mr_bh(sh->cdev->pd, &priv->mp_id, &sh->share_cache,\n-\t\t\t mr_ctrl, addr, sh->cdev->config.mr_ext_memseg_en);\n+\treturn mlx5_tx_addr2mr_bh(txq, addr);\n }\n \n /**\n@@ -331,67 +255,3 @@ mlx5_net_dma_unmap(struct rte_device *rte_dev, void *addr,\n \trte_rwlock_write_unlock(&sh->share_cache.rwlock);\n \treturn 0;\n }\n-\n-/**\n- * Register MR for entire memory chunks in a Mempool having externally allocated\n- * memory and fill in local cache.\n- *\n- * @param dev\n- * Pointer to Ethernet device.\n- * @param mr_ctrl\n- * Pointer to per-queue MR control structure.\n- * @param mp\n- * Pointer to registering Mempool.\n- *\n- * @return\n- * 0 on success, -1 on failure.\n- */\n-static uint32_t\n-mlx5_mr_update_ext_mp(struct rte_eth_dev *dev, struct mlx5_mr_ctrl *mr_ctrl,\n-\t\t struct rte_mempool *mp)\n-{\n-\tstruct mr_update_mp_data data = {\n-\t\t.dev = dev,\n-\t\t.mr_ctrl = mr_ctrl,\n-\t\t.ret = 0,\n-\t};\n-\n-\trte_mempool_mem_iter(mp, mlx5_mr_update_ext_mp_cb, &data);\n-\treturn data.ret;\n-}\n-\n-/**\n- * Register MR entire memory chunks in a Mempool having externally allocated\n- * memory and search LKey of the address to return.\n- *\n- * @param dev\n- * Pointer to Ethernet device.\n- * @param addr\n- * Search key.\n- * @param mp\n- * Pointer to registering Mempool where addr belongs.\n- *\n- * @return\n- * LKey for address on success, UINT32_MAX on failure.\n- */\n-uint32_t\n-mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,\n-\t\t struct rte_mempool *mp)\n-{\n-\tstruct mlx5_txq_ctrl *txq_ctrl =\n-\t\tcontainer_of(txq, struct mlx5_txq_ctrl, txq);\n-\tstruct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;\n-\tstruct mlx5_priv *priv = txq_ctrl->priv;\n-\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n-\t\tDRV_LOG(WARNING,\n-\t\t\t\"port %u using address (%p) from unregistered mempool\"\n-\t\t\t\" having externally allocated memory\"\n-\t\t\t\" in secondary process, please create mempool\"\n-\t\t\t\" prior to rte_eth_dev_start()\",\n-\t\t\tPORT_ID(priv), (void *)addr);\n-\t\treturn UINT32_MAX;\n-\t}\n-\tmlx5_mr_update_ext_mp(ETH_DEV(priv), mr_ctrl, mp);\n-\treturn mlx5_tx_addr2mr_bh(txq, addr);\n-}\ndiff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h\nindex e722738682..cdbcf659df 100644\n--- a/drivers/net/mlx5/mlx5_tx.h\n+++ b/drivers/net/mlx5/mlx5_tx.h\n@@ -239,8 +239,6 @@ int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n /* mlx5_mr.c */\n \n uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);\n-uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,\n-\t\t\t struct rte_mempool *mp);\n \n /* mlx5_tx_empw.c */\n \n", "prefixes": [ "v3", "12/18" ] }