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GET /api/patches/102315/?format=api
{ "id": 102315, "url": "http://patches.dpdk.org/api/patches/102315/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211019205602.3188203-11-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211019205602.3188203-11-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211019205602.3188203-11-michaelba@nvidia.com", "date": "2021-10-19T20:55:54", "name": "[v3,10/18] common/mlx5: share the protection domain object", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "642797397c77c8e80c055c6d270d28cd67bdf15c", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211019205602.3188203-11-michaelba@nvidia.com/mbox/", "series": [ { "id": 19808, "url": "http://patches.dpdk.org/api/series/19808/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19808", "date": "2021-10-19T20:55:44", "name": "mlx5: sharing global MR cache between drivers", "version": 3, "mbox": "http://patches.dpdk.org/series/19808/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102315/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102315/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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"X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4153", "Subject": "[dpdk-dev] [PATCH v3 10/18] common/mlx5: share the protection\n domain object", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nCreate shared Protection Domain in common area and add it and its PDN as\nfields of common device structure.\n\nUse this Protection Domain in all drivers and remove the PD and PDN\nfields from their private structure.\n\nSigned-off-by: Michael Baum <michaelba@oss.nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/linux/mlx5_common_os.c | 43 ++++++++++++++\n drivers/common/mlx5/linux/mlx5_common_os.h | 8 ---\n drivers/common/mlx5/mlx5_common.c | 11 ++++\n drivers/common/mlx5/mlx5_common.h | 3 +\n drivers/common/mlx5/version.map | 2 -\n drivers/common/mlx5/windows/mlx5_common_os.c | 59 ++++++++++----------\n drivers/common/mlx5/windows/mlx5_common_os.h | 3 -\n drivers/compress/mlx5/mlx5_compress.c | 58 +++----------------\n drivers/crypto/mlx5/mlx5_crypto.c | 56 +++----------------\n drivers/crypto/mlx5/mlx5_crypto.h | 2 -\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 2 +-\n drivers/net/mlx5/linux/mlx5_mp_os.c | 2 +-\n drivers/net/mlx5/linux/mlx5_os.c | 37 +-----------\n drivers/net/mlx5/linux/mlx5_verbs.c | 14 ++---\n drivers/net/mlx5/mlx5.c | 27 +++------\n drivers/net/mlx5/mlx5.h | 3 -\n drivers/net/mlx5/mlx5_devx.c | 4 +-\n drivers/net/mlx5/mlx5_flow.c | 2 +-\n drivers/net/mlx5/mlx5_flow_aso.c | 17 +++---\n drivers/net/mlx5/mlx5_flow_dv.c | 17 +++---\n drivers/net/mlx5/mlx5_mr.c | 12 ++--\n drivers/net/mlx5/mlx5_rxq.c | 4 +-\n drivers/net/mlx5/mlx5_trigger.c | 3 +-\n drivers/net/mlx5/mlx5_txpp.c | 4 +-\n drivers/net/mlx5/windows/mlx5_os.c | 21 -------\n drivers/regex/mlx5/mlx5_regex.c | 10 ----\n drivers/regex/mlx5/mlx5_regex.h | 21 -------\n drivers/regex/mlx5/mlx5_regex_control.c | 6 +-\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 13 ++---\n drivers/vdpa/mlx5/mlx5_vdpa.c | 38 +------------\n drivers/vdpa/mlx5/mlx5_vdpa.h | 2 -\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 +-\n drivers/vdpa/mlx5/mlx5_vdpa_lm.c | 2 +-\n drivers/vdpa/mlx5/mlx5_vdpa_mem.c | 6 +-\n drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 2 +-\n 35 files changed, 167 insertions(+), 349 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c\nindex 341822cf71..8db3fe790a 100644\n--- a/drivers/common/mlx5/linux/mlx5_common_os.c\n+++ b/drivers/common/mlx5/linux/mlx5_common_os.c\n@@ -406,6 +406,49 @@ mlx5_glue_constructor(void)\n \tmlx5_glue = NULL;\n }\n \n+/**\n+ * Allocate Protection Domain object and extract its pdn using DV API.\n+ *\n+ * @param[out] cdev\n+ * Pointer to the mlx5 device.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_os_pd_create(struct mlx5_common_device *cdev)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tstruct mlx5dv_obj obj;\n+\tstruct mlx5dv_pd pd_info;\n+\tint ret;\n+#endif\n+\n+\tcdev->pd = mlx5_glue->alloc_pd(cdev->ctx);\n+\tif (cdev->pd == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate PD.\");\n+\t\treturn errno ? -errno : -ENOMEM;\n+\t}\n+\tif (cdev->config.devx == 0)\n+\t\treturn 0;\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tobj.pd.in = cdev->pd;\n+\tobj.pd.out = &pd_info;\n+\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Fail to get PD object info.\");\n+\t\tmlx5_glue->dealloc_pd(cdev->pd);\n+\t\tcdev->pd = NULL;\n+\t\treturn -errno;\n+\t}\n+\tcdev->pdn = pd_info.pdn;\n+\treturn 0;\n+#else\n+\tDRV_LOG(ERR, \"Cannot get pdn - no DV support.\");\n+\treturn -ENOTSUP;\n+#endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n+}\n+\n static struct ibv_device *\n mlx5_os_get_ibv_device(const struct rte_pci_addr *addr)\n {\ndiff --git a/drivers/common/mlx5/linux/mlx5_common_os.h b/drivers/common/mlx5/linux/mlx5_common_os.h\nindex 0e605c3a9e..c2957f91ec 100644\n--- a/drivers/common/mlx5/linux/mlx5_common_os.h\n+++ b/drivers/common/mlx5/linux/mlx5_common_os.h\n@@ -203,14 +203,6 @@ mlx5_os_get_devx_uar_page_id(void *uar)\n #endif\n }\n \n-__rte_internal\n-static inline void *\n-mlx5_os_alloc_pd(void *ctx)\n-{\n-\treturn mlx5_glue->alloc_pd(ctx);\n-}\n-\n-__rte_internal\n static inline int\n mlx5_os_dealloc_pd(void *pd)\n {\ndiff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c\nindex 5786b5c0b9..ec246c15f9 100644\n--- a/drivers/common/mlx5/mlx5_common.c\n+++ b/drivers/common/mlx5/mlx5_common.c\n@@ -320,6 +320,10 @@ mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size)\n static void\n mlx5_dev_hw_global_release(struct mlx5_common_device *cdev)\n {\n+\tif (cdev->pd != NULL) {\n+\t\tclaim_zero(mlx5_os_dealloc_pd(cdev->pd));\n+\t\tcdev->pd = NULL;\n+\t}\n \tif (cdev->ctx != NULL) {\n \t\tclaim_zero(mlx5_glue->close_device(cdev->ctx));\n \t\tcdev->ctx = NULL;\n@@ -346,7 +350,14 @@ mlx5_dev_hw_global_prepare(struct mlx5_common_device *cdev, uint32_t classes)\n \tret = mlx5_os_open_device(cdev, classes);\n \tif (ret < 0)\n \t\treturn ret;\n+\t/* Allocate Protection Domain object and extract its pdn. */\n+\tret = mlx5_os_pd_create(cdev);\n+\tif (ret)\n+\t\tgoto error;\n \treturn 0;\n+error:\n+\tmlx5_dev_hw_global_release(cdev);\n+\treturn ret;\n }\n \n static void\ndiff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex 066860045a..d72002ca3c 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -346,6 +346,8 @@ struct mlx5_common_device {\n \tTAILQ_ENTRY(mlx5_common_device) next;\n \tuint32_t classes_loaded;\n \tvoid *ctx; /* Verbs/DV/DevX context. */\n+\tvoid *pd; /* Protection Domain. */\n+\tuint32_t pdn; /* Protection Domain Number. */\n \tstruct mlx5_common_dev_config config; /* Device configuration. */\n };\n \n@@ -447,5 +449,6 @@ mlx5_dev_is_pci(const struct rte_device *dev);\n /* mlx5_common_os.c */\n \n int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes);\n+int mlx5_os_pd_create(struct mlx5_common_device *cdev);\n \n #endif /* RTE_PMD_MLX5_COMMON_H_ */\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex 24925fc4e4..44c4593888 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -135,8 +135,6 @@ INTERNAL {\n \tmlx5_nl_vlan_vmwa_create; # WINDOWS_NO_EXPORT\n \tmlx5_nl_vlan_vmwa_delete; # WINDOWS_NO_EXPORT\n \n-\tmlx5_os_alloc_pd;\n-\tmlx5_os_dealloc_pd;\n \tmlx5_os_dereg_mr;\n \tmlx5_os_reg_mr;\n \tmlx5_os_umem_dereg;\ndiff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c\nindex b7178cbbcf..4d0f1e92e3 100644\n--- a/drivers/common/mlx5/windows/mlx5_common_os.c\n+++ b/drivers/common/mlx5/windows/mlx5_common_os.c\n@@ -25,35 +25,6 @@ mlx5_glue_constructor(void)\n {\n }\n \n-/**\n- * Allocate PD. Given a DevX context object\n- * return an mlx5-pd object.\n- *\n- * @param[in] ctx\n- * Pointer to context.\n- *\n- * @return\n- * The mlx5_pd if pd is valid, NULL and errno otherwise.\n- */\n-void *\n-mlx5_os_alloc_pd(void *ctx)\n-{\n-\tstruct mlx5_pd *ppd = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct mlx5_pd),\n-\t\t\t\t\t 0, SOCKET_ID_ANY);\n-\tif (!ppd)\n-\t\treturn NULL;\n-\n-\tstruct mlx5_devx_obj *obj = mlx5_devx_cmd_alloc_pd(ctx);\n-\tif (!obj) {\n-\t\tmlx5_free(ppd);\n-\t\treturn NULL;\n-\t}\n-\tppd->obj = obj;\n-\tppd->pdn = obj->id;\n-\tppd->devx_ctx = ctx;\n-\treturn ppd;\n-}\n-\n /**\n * Release PD. Releases a given mlx5_pd object\n *\n@@ -73,6 +44,36 @@ mlx5_os_dealloc_pd(void *pd)\n \treturn 0;\n }\n \n+/**\n+ * Allocate Protection Domain object and extract its pdn using DV API.\n+ *\n+ * @param[out] dev\n+ * Pointer to the mlx5 device.\n+ *\n+ * @return\n+ * 0 on success, a negative value otherwise.\n+ */\n+int\n+mlx5_os_pd_create(struct mlx5_common_device *cdev)\n+{\n+\tstruct mlx5_pd *pd;\n+\n+\tpd = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pd), 0, SOCKET_ID_ANY);\n+\tif (!pd)\n+\t\treturn -1;\n+\tstruct mlx5_devx_obj *obj = mlx5_devx_cmd_alloc_pd(cdev->ctx);\n+\tif (!obj) {\n+\t\tmlx5_free(pd);\n+\t\treturn -1;\n+\t}\n+\tpd->obj = obj;\n+\tpd->pdn = obj->id;\n+\tpd->devx_ctx = cdev->ctx;\n+\tcdev->pd = pd;\n+\tcdev->pdn = pd->pdn;\n+\treturn 0;\n+}\n+\n /**\n * Detect if a devx_device_bdf object has identical DBDF values to the\n * rte_pci_addr found in bus/pci probing.\ndiff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h\nindex 3756e1959b..c99645aefd 100644\n--- a/drivers/common/mlx5/windows/mlx5_common_os.h\n+++ b/drivers/common/mlx5/windows/mlx5_common_os.h\n@@ -248,9 +248,6 @@ mlx5_os_devx_subscribe_devx_event(void *eventc,\n \treturn -ENOTSUP;\n }\n \n-__rte_internal\n-void *mlx5_os_alloc_pd(void *ctx);\n-__rte_internal\n int mlx5_os_dealloc_pd(void *pd);\n __rte_internal\n void *mlx5_os_umem_reg(void *ctx, void *addr, size_t size, uint32_t access);\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 246a9c994b..4c8e67c4df 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -38,11 +38,9 @@ struct mlx5_compress_priv {\n \tstruct rte_compressdev *compressdev;\n \tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n \tvoid *uar;\n-\tuint32_t pdn; /* Protection Domain number. */\n \tuint8_t min_block_size;\n \tuint8_t qp_ts_format; /* Whether SQ supports timestamp formats. */\n \t/* Minimum huffman block size supported by the device. */\n-\tstruct ibv_pd *pd;\n \tstruct rte_compressdev_config dev_config;\n \tLIST_HEAD(xform_list, mlx5_compress_xform) xform_list;\n \trte_spinlock_t xform_sl;\n@@ -190,7 +188,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),\n \t};\n \tstruct mlx5_devx_qp_attr qp_attr = {\n-\t\t.pd = priv->pdn,\n+\t\t.pd = priv->cdev->pdn,\n \t\t.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar),\n \t\t.user_index = qp_id,\n \t};\n@@ -230,7 +228,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \tqp->priv = priv;\n \tqp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),\n \t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n-\tif (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *\n+\tif (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *\n \t\t\t\t\tsizeof(struct mlx5_gga_compress_opaque),\n \t\t\t\t\t\t\t &qp->opaque_mr) != 0) {\n \t\trte_free(opaq_buf);\n@@ -469,8 +467,8 @@ mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr,\n \tif (likely(lkey != UINT32_MAX))\n \t\treturn lkey;\n \t/* Take slower bottom-half on miss. */\n-\treturn mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr,\n-\t\t\t\t !!(ol_flags & EXT_ATTACHED_MBUF));\n+\treturn mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,\n+\t\t\t\t addr, !!(ol_flags & EXT_ATTACHED_MBUF));\n }\n \n static __rte_always_inline uint32_t\n@@ -691,12 +689,8 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,\n }\n \n static void\n-mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)\n+mlx5_compress_uar_release(struct mlx5_compress_priv *priv)\n {\n-\tif (priv->pd != NULL) {\n-\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n-\t\tpriv->pd = NULL;\n-\t}\n \tif (priv->uar != NULL) {\n \t\tmlx5_glue->devx_free_uar(priv->uar);\n \t\tpriv->uar = NULL;\n@@ -704,46 +698,12 @@ mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)\n }\n \n static int\n-mlx5_compress_pd_create(struct mlx5_compress_priv *priv)\n+mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv)\n {\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tstruct mlx5dv_obj obj;\n-\tstruct mlx5dv_pd pd_info;\n-\tint ret;\n-\n-\tpriv->pd = mlx5_glue->alloc_pd(priv->cdev->ctx);\n-\tif (priv->pd == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate PD.\");\n-\t\treturn errno ? -errno : -ENOMEM;\n-\t}\n-\tobj.pd.in = priv->pd;\n-\tobj.pd.out = &pd_info;\n-\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n-\tif (ret != 0) {\n-\t\tDRV_LOG(ERR, \"Fail to get PD object info.\");\n-\t\tmlx5_glue->dealloc_pd(priv->pd);\n-\t\tpriv->pd = NULL;\n-\t\treturn -errno;\n-\t}\n-\tpriv->pdn = pd_info.pdn;\n-\treturn 0;\n-#else\n-\t(void)priv;\n-\tDRV_LOG(ERR, \"Cannot get pdn - no DV support.\");\n-\treturn -ENOTSUP;\n-#endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n-}\n-\n-static int\n-mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)\n-{\n-\tif (mlx5_compress_pd_create(priv) != 0)\n-\t\treturn -1;\n \tpriv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);\n \tif (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==\n \t NULL) {\n \t\trte_errno = errno;\n-\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n \t\tDRV_LOG(ERR, \"Failed to allocate UAR.\");\n \t\treturn -1;\n \t}\n@@ -839,14 +799,14 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev)\n \tpriv->compressdev = compressdev;\n \tpriv->min_block_size = att.compress_min_block_size;\n \tpriv->qp_ts_format = att.qp_ts_format;\n-\tif (mlx5_compress_hw_global_prepare(priv) != 0) {\n+\tif (mlx5_compress_uar_prepare(priv) != 0) {\n \t\trte_compressdev_pmd_destroy(priv->compressdev);\n \t\treturn -1;\n \t}\n \tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n \t\t\t MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {\n \t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n-\t\tmlx5_compress_hw_global_release(priv);\n+\t\tmlx5_compress_uar_release(priv);\n \t\trte_compressdev_pmd_destroy(priv->compressdev);\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n@@ -881,7 +841,7 @@ mlx5_compress_dev_remove(struct mlx5_common_device *cdev)\n \t\t\trte_mem_event_callback_unregister(\"MLX5_MEM_EVENT_CB\",\n \t\t\t\t\t\t\t NULL);\n \t\tmlx5_mr_release_cache(&priv->mr_scache);\n-\t\tmlx5_compress_hw_global_release(priv);\n+\t\tmlx5_compress_uar_release(priv);\n \t\trte_compressdev_pmd_destroy(priv->compressdev);\n \t}\n \treturn 0;\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 10ac633c77..b22b7836e1 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -333,8 +333,8 @@ mlx5_crypto_addr2mr(struct mlx5_crypto_priv *priv, uintptr_t addr,\n \tif (likely(lkey != UINT32_MAX))\n \t\treturn lkey;\n \t/* Take slower bottom-half on miss. */\n-\treturn mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr,\n-\t\t\t\t !!(ol_flags & EXT_ATTACHED_MBUF));\n+\treturn mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,\n+\t\t\t\t addr, !!(ol_flags & EXT_ATTACHED_MBUF));\n }\n \n static __rte_always_inline uint32_t\n@@ -610,7 +610,7 @@ mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,\n \tstruct mlx5_umr_wqe *umr;\n \tuint32_t i;\n \tstruct mlx5_devx_mkey_attr attr = {\n-\t\t.pd = priv->pdn,\n+\t\t.pd = priv->cdev->pdn,\n \t\t.umr_en = 1,\n \t\t.crypto_en = 1,\n \t\t.set_remote_rw = 1,\n@@ -664,7 +664,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n \t}\n-\tattr.pd = priv->pdn;\n+\tattr.pd = priv->cdev->pdn;\n \tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n \tattr.cqn = qp->cq_obj.cq->id;\n \tattr.rq_size = 0;\n@@ -754,12 +754,8 @@ static struct rte_cryptodev_ops mlx5_crypto_ops = {\n };\n \n static void\n-mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv)\n+mlx5_crypto_uar_release(struct mlx5_crypto_priv *priv)\n {\n-\tif (priv->pd != NULL) {\n-\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n-\t\tpriv->pd = NULL;\n-\t}\n \tif (priv->uar != NULL) {\n \t\tmlx5_glue->devx_free_uar(priv->uar);\n \t\tpriv->uar = NULL;\n@@ -767,47 +763,13 @@ mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv)\n }\n \n static int\n-mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv)\n+mlx5_crypto_uar_prepare(struct mlx5_crypto_priv *priv)\n {\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tstruct mlx5dv_obj obj;\n-\tstruct mlx5dv_pd pd_info;\n-\tint ret;\n-\n-\tpriv->pd = mlx5_glue->alloc_pd(priv->cdev->ctx);\n-\tif (priv->pd == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate PD.\");\n-\t\treturn errno ? -errno : -ENOMEM;\n-\t}\n-\tobj.pd.in = priv->pd;\n-\tobj.pd.out = &pd_info;\n-\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n-\tif (ret != 0) {\n-\t\tDRV_LOG(ERR, \"Fail to get PD object info.\");\n-\t\tmlx5_glue->dealloc_pd(priv->pd);\n-\t\tpriv->pd = NULL;\n-\t\treturn -errno;\n-\t}\n-\tpriv->pdn = pd_info.pdn;\n-\treturn 0;\n-#else\n-\t(void)priv;\n-\tDRV_LOG(ERR, \"Cannot get pdn - no DV support.\");\n-\treturn -ENOTSUP;\n-#endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n-}\n-\n-static int\n-mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv)\n-{\n-\tif (mlx5_crypto_pd_create(priv) != 0)\n-\t\treturn -1;\n \tpriv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);\n \tif (priv->uar)\n \t\tpriv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);\n \tif (priv->uar == NULL || priv->uar_addr == NULL) {\n \t\trte_errno = errno;\n-\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n \t\tDRV_LOG(ERR, \"Failed to allocate UAR.\");\n \t\treturn -1;\n \t}\n@@ -1011,14 +973,14 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)\n \tpriv->login_obj = login;\n \tpriv->crypto_dev = crypto_dev;\n \tpriv->qp_ts_format = attr.qp_ts_format;\n-\tif (mlx5_crypto_hw_global_prepare(priv) != 0) {\n+\tif (mlx5_crypto_uar_prepare(priv) != 0) {\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n \t\treturn -1;\n \t}\n \tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n \t\t\t MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {\n \t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n-\t\tmlx5_crypto_hw_global_release(priv);\n+\t\tmlx5_crypto_uar_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n@@ -1066,7 +1028,7 @@ mlx5_crypto_dev_remove(struct mlx5_common_device *cdev)\n \t\t\trte_mem_event_callback_unregister(\"MLX5_MEM_EVENT_CB\",\n \t\t\t\t\t\t\t NULL);\n \t\tmlx5_mr_release_cache(&priv->mr_scache);\n-\t\tmlx5_crypto_hw_global_release(priv);\n+\t\tmlx5_crypto_uar_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n \t\tclaim_zero(mlx5_devx_cmd_destroy(priv->login_obj));\n \t}\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 14dd3b9c9a..27ae9cff2c 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -23,10 +23,8 @@ struct mlx5_crypto_priv {\n \tstruct rte_cryptodev *crypto_dev;\n \tvoid *uar; /* User Access Region. */\n \tvolatile uint64_t *uar_addr;\n-\tuint32_t pdn; /* Protection Domain number. */\n \tuint32_t max_segs_num; /* Maximum supported data segs. */\n \tuint8_t qp_ts_format; /* Whether QP supports timestamp formats. */\n-\tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n \tstruct rte_cryptodev_config dev_config;\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_dek.c b/drivers/crypto/mlx5/mlx5_crypto_dek.c\nindex 94f21ec036..de0d2545d1 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_dek.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_dek.c\n@@ -94,7 +94,7 @@ mlx5_crypto_dek_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)\n \tstruct mlx5_crypto_dek *dek = rte_zmalloc(__func__, sizeof(*dek),\n \t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n \tstruct mlx5_devx_dek_attr dek_attr = {\n-\t\t.pd = ctx->priv->pdn,\n+\t\t.pd = ctx->priv->cdev->pdn,\n \t\t.key_purpose = MLX5_CRYPTO_KEY_PURPOSE_AES_XTS,\n \t\t.has_keytag = 1,\n \t};\ndiff --git a/drivers/net/mlx5/linux/mlx5_mp_os.c b/drivers/net/mlx5/linux/mlx5_mp_os.c\nindex 35b2dfd3b2..286a7caf36 100644\n--- a/drivers/net/mlx5/linux/mlx5_mp_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_mp_os.c\n@@ -90,7 +90,7 @@ mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)\n \tswitch (param->type) {\n \tcase MLX5_MP_REQ_CREATE_MR:\n \t\tmp_init_msg(&priv->mp_id, &mp_res, param->type);\n-\t\tlkey = mlx5_mr_create_primary(priv->sh->pd,\n+\t\tlkey = mlx5_mr_create_primary(cdev->pd,\n \t\t\t\t\t &priv->sh->share_cache,\n \t\t\t\t\t &entry, param->args.addr,\n \t\t\t\t\t cdev->config.mr_ext_memseg_en);\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 6b02decaec..36927e0dcc 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -785,7 +785,7 @@ mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)\n \t\t\t\t\t\t .wq_type = IBV_WQT_RQ,\n \t\t\t\t\t\t .max_wr = 1,\n \t\t\t\t\t\t .max_sge = 1,\n-\t\t\t\t\t\t .pd = priv->sh->pd,\n+\t\t\t\t\t\t .pd = priv->sh->cdev->pd,\n \t\t\t\t\t\t .cq = cq,\n \t\t\t\t\t\t});\n \t\t\tif (wq) {\n@@ -2711,41 +2711,6 @@ mlx5_os_net_probe(struct mlx5_common_device *cdev)\n \t\treturn mlx5_os_auxiliary_probe(cdev);\n }\n \n-/**\n- * Extract pdn of PD object using DV API.\n- *\n- * @param[in] pd\n- * Pointer to the verbs PD object.\n- * @param[out] pdn\n- * Pointer to the PD object number variable.\n- *\n- * @return\n- * 0 on success, error value otherwise.\n- */\n-int\n-mlx5_os_get_pdn(void *pd, uint32_t *pdn)\n-{\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tstruct mlx5dv_obj obj;\n-\tstruct mlx5dv_pd pd_info;\n-\tint ret = 0;\n-\n-\tobj.pd.in = pd;\n-\tobj.pd.out = &pd_info;\n-\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n-\tif (ret) {\n-\t\tDRV_LOG(DEBUG, \"Fail to get PD object info\");\n-\t\treturn ret;\n-\t}\n-\t*pdn = pd_info.pdn;\n-\treturn 0;\n-#else\n-\t(void)pd;\n-\t(void)pdn;\n-\treturn -ENOTSUP;\n-#endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n-}\n-\n /**\n * Install shared asynchronous device events handler.\n * This function is implemented to support event sharing\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex 981fc2ee7c..fb10dd0839 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -289,7 +289,7 @@ mlx5_rxq_ibv_wq_create(struct rte_eth_dev *dev, uint16_t idx)\n \t\t.max_wr = wqe_n >> rxq_data->sges_n,\n \t\t/* Max number of scatter/gather elements in a WR. */\n \t\t.max_sge = 1 << rxq_data->sges_n,\n-\t\t.pd = priv->sh->pd,\n+\t\t.pd = priv->sh->cdev->pd,\n \t\t.cq = rxq_obj->ibv_cq,\n \t\t.comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,\n \t\t.create_flags = (rxq_data->vlan_strip ?\n@@ -627,7 +627,7 @@ mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n \t\t\t\t},\n \t\t\t\t.rwq_ind_tbl = ind_tbl->ind_table,\n-\t\t\t\t.pd = priv->sh->pd,\n+\t\t\t\t.pd = priv->sh->cdev->pd,\n \t\t\t },\n \t\t\t &qp_init_attr);\n #else\n@@ -648,7 +648,7 @@ mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n \t\t\t\t},\n \t\t\t\t.rwq_ind_tbl = ind_tbl->ind_table,\n-\t\t\t\t.pd = priv->sh->pd,\n+\t\t\t\t.pd = priv->sh->cdev->pd,\n \t\t\t });\n #endif\n \tif (!qp) {\n@@ -741,7 +741,7 @@ mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev *dev)\n \t\t\t\t\t\t .wq_type = IBV_WQT_RQ,\n \t\t\t\t\t\t .max_wr = 1,\n \t\t\t\t\t\t .max_sge = 1,\n-\t\t\t\t\t\t .pd = priv->sh->pd,\n+\t\t\t\t\t\t .pd = priv->sh->cdev->pd,\n \t\t\t\t\t\t .cq = rxq->ibv_cq,\n \t\t\t\t\t });\n \tif (!rxq->wq) {\n@@ -807,7 +807,7 @@ mlx5_ibv_drop_action_create(struct rte_eth_dev *dev)\n \t\t\t\t.rx_hash_fields_mask = 0,\n \t\t\t\t},\n \t\t\t.rwq_ind_tbl = ind_tbl,\n-\t\t\t.pd = priv->sh->pd\n+\t\t\t.pd = priv->sh->cdev->pd\n \t\t });\n \tif (!hrxq->qp) {\n \t\tDRV_LOG(DEBUG, \"Port %u cannot allocate QP for drop queue.\",\n@@ -895,7 +895,7 @@ mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx)\n \tqp_attr.qp_type = IBV_QPT_RAW_PACKET,\n \t/* Do *NOT* enable this, completions events are managed per Tx burst. */\n \tqp_attr.sq_sig_all = 0;\n-\tqp_attr.pd = priv->sh->pd;\n+\tqp_attr.pd = priv->sh->cdev->pd;\n \tqp_attr.comp_mask = IBV_QP_INIT_ATTR_PD;\n \tif (txq_data->inlen_send)\n \t\tqp_attr.cap.max_inline_data = txq_ctrl->max_inline_data;\n@@ -1117,7 +1117,7 @@ mlx5_rxq_ibv_obj_dummy_lb_create(struct rte_eth_dev *dev)\n \t\t\t\t&(struct ibv_qp_init_attr_ex){\n \t\t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n \t\t\t\t\t.comp_mask = IBV_QP_INIT_ATTR_PD,\n-\t\t\t\t\t.pd = sh->pd,\n+\t\t\t\t\t.pd = sh->cdev->pd,\n \t\t\t\t\t.send_cq = sh->self_lb.ibv_cq,\n \t\t\t\t\t.recv_cq = sh->self_lb.ibv_cq,\n \t\t\t\t\t.cap.max_recv_wr = 1,\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 6c50c43951..1bb490c5e7 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1109,7 +1109,7 @@ mlx5_dev_ctx_shared_mempool_unregister(struct mlx5_dev_ctx_shared *sh,\n \tmlx5_mp_id_init(&mp_id, 0);\n \tif (mlx5_mr_mempool_unregister(&sh->share_cache, mp, &mp_id) < 0)\n \t\tDRV_LOG(WARNING, \"Failed to unregister mempool %s for PD %p: %s\",\n-\t\t\tmp->name, sh->pd, rte_strerror(rte_errno));\n+\t\t\tmp->name, sh->cdev->pd, rte_strerror(rte_errno));\n }\n \n /**\n@@ -1129,10 +1129,11 @@ mlx5_dev_ctx_shared_mempool_register_cb(struct rte_mempool *mp, void *arg)\n \tint ret;\n \n \tmlx5_mp_id_init(&mp_id, 0);\n-\tret = mlx5_mr_mempool_register(&sh->share_cache, sh->pd, mp, &mp_id);\n+\tret = mlx5_mr_mempool_register(&sh->share_cache, sh->cdev->pd, mp,\n+\t\t\t\t &mp_id);\n \tif (ret < 0 && rte_errno != EEXIST)\n \t\tDRV_LOG(ERR, \"Failed to register existing mempool %s for PD %p: %s\",\n-\t\t\tmp->name, sh->pd, rte_strerror(rte_errno));\n+\t\t\tmp->name, sh->cdev->pd, rte_strerror(rte_errno));\n }\n \n /**\n@@ -1171,10 +1172,11 @@ mlx5_dev_ctx_shared_mempool_event_cb(enum rte_mempool_event event,\n \tswitch (event) {\n \tcase RTE_MEMPOOL_EVENT_READY:\n \t\tmlx5_mp_id_init(&mp_id, 0);\n-\t\tif (mlx5_mr_mempool_register(&sh->share_cache, sh->pd, mp,\n+\t\tif (mlx5_mr_mempool_register(&sh->share_cache, sh->cdev->pd, mp,\n \t\t\t\t\t &mp_id) < 0)\n \t\t\tDRV_LOG(ERR, \"Failed to register new mempool %s for PD %p: %s\",\n-\t\t\t\tmp->name, sh->pd, rte_strerror(rte_errno));\n+\t\t\t\tmp->name, sh->cdev->pd,\n+\t\t\t\trte_strerror(rte_errno));\n \t\tbreak;\n \tcase RTE_MEMPOOL_EVENT_DESTROY:\n \t\tmlx5_dev_ctx_shared_mempool_unregister(sh, mp);\n@@ -1306,18 +1308,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\tsh->port[i].ih_port_id = RTE_MAX_ETHPORTS;\n \t\tsh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;\n \t}\n-\tsh->pd = mlx5_os_alloc_pd(sh->cdev->ctx);\n-\tif (sh->pd == NULL) {\n-\t\tDRV_LOG(ERR, \"PD allocation failure\");\n-\t\terr = ENOMEM;\n-\t\tgoto error;\n-\t}\n \tif (sh->devx) {\n-\t\terr = mlx5_os_get_pdn(sh->pd, &sh->pdn);\n-\t\tif (err) {\n-\t\t\tDRV_LOG(ERR, \"Fail to extract pdn from PD\");\n-\t\t\tgoto error;\n-\t\t}\n \t\tsh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);\n \t\tif (!sh->td) {\n \t\t\tDRV_LOG(ERR, \"TD allocation failure\");\n@@ -1405,8 +1396,6 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\tmlx5_glue->devx_free_uar(sh->devx_rx_uar);\n \tif (sh->tx_uar)\n \t\tmlx5_glue->devx_free_uar(sh->tx_uar);\n-\tif (sh->pd)\n-\t\tclaim_zero(mlx5_os_dealloc_pd(sh->pd));\n \tmlx5_free(sh);\n \tMLX5_ASSERT(err > 0);\n \trte_errno = err;\n@@ -1487,8 +1476,6 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)\n \t\tmlx5_glue->devx_free_uar(sh->tx_uar);\n \t\tsh->tx_uar = NULL;\n \t}\n-\tif (sh->pd)\n-\t\tclaim_zero(mlx5_os_dealloc_pd(sh->pd));\n \tif (sh->tis)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(sh->tis));\n \tif (sh->td)\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 2c92b2ce13..7048f7bd1c 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1140,8 +1140,6 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t max_port; /* Maximal IB device port index. */\n \tstruct mlx5_bond_info bond; /* Bonding information. */\n \tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n-\tvoid *pd; /* Protection Domain. */\n-\tuint32_t pdn; /* Protection Domain number. */\n \tuint32_t tdn; /* Transport Domain number. */\n \tchar ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */\n \tchar ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */\n@@ -1769,7 +1767,6 @@ void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev);\n struct rte_pci_driver;\n int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);\n void mlx5_os_free_shared_dr(struct mlx5_priv *priv);\n-int mlx5_os_get_pdn(void *pd, uint32_t *pdn);\n int mlx5_os_net_probe(struct mlx5_common_device *cdev);\n void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);\n void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 1fb835cb0d..b98b82bf79 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -276,7 +276,7 @@ mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx)\n \trq_attr.wq_attr.end_padding_mode = priv->config.hw_padding ?\n \t\t\t\t\t\tMLX5_WQ_END_PAD_MODE_ALIGN :\n \t\t\t\t\t\tMLX5_WQ_END_PAD_MODE_NONE;\n-\trq_attr.wq_attr.pd = priv->sh->pdn;\n+\trq_attr.wq_attr.pd = priv->sh->cdev->pdn;\n \trq_attr.counter_set_id = priv->counter_set_id;\n \t/* Create RQ using DevX API. */\n \treturn mlx5_devx_rq_create(priv->sh->cdev->ctx, &rxq_ctrl->obj->rq_obj,\n@@ -994,7 +994,7 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,\n \t\t.tis_lst_sz = 1,\n \t\t.tis_num = priv->sh->tis->id,\n \t\t.wq_attr = (struct mlx5_devx_wq_attr){\n-\t\t\t.pd = priv->sh->pdn,\n+\t\t\t.pd = priv->sh->cdev->pdn,\n \t\t\t.uar_page =\n \t\t\t\t mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar),\n \t\t},\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex abe8a0d7fe..a4d85f4a8f 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -7639,7 +7639,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh)\n \tmkey_attr.addr = (uintptr_t)mem;\n \tmkey_attr.size = size;\n \tmkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);\n-\tmkey_attr.pd = sh->pdn;\n+\tmkey_attr.pd = sh->cdev->pdn;\n \tmkey_attr.relaxed_ordering_write = sh->cmng.relaxed_ordering_write;\n \tmkey_attr.relaxed_ordering_read = sh->cmng.relaxed_ordering_read;\n \tmem_mng->dm = mlx5_devx_cmd_mkey_create(sh->cdev->ctx, &mkey_attr);\ndiff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c\nindex 49eec7a6b6..17e3f2a300 100644\n--- a/drivers/net/mlx5/mlx5_flow_aso.c\n+++ b/drivers/net/mlx5/mlx5_flow_aso.c\n@@ -103,7 +103,7 @@ mlx5_aso_reg_mr(struct mlx5_dev_ctx_shared *sh, size_t length,\n \t\tDRV_LOG(ERR, \"Failed to create ASO bits mem for MR.\");\n \t\treturn -1;\n \t}\n-\tret = sh->share_cache.reg_mr_cb(sh->pd, mr->addr, length, mr);\n+\tret = sh->share_cache.reg_mr_cb(sh->cdev->pd, mr->addr, length, mr);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to create direct Mkey.\");\n \t\tmlx5_free(mr->addr);\n@@ -317,8 +317,9 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,\n \t\t\t\t sq_desc_n, &sh->aso_age_mng->aso_sq.mr, 0))\n \t\t\treturn -1;\n \t\tif (mlx5_aso_sq_create(cdev->ctx, &sh->aso_age_mng->aso_sq, 0,\n-\t\t\t\t sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,\n-\t\t\t\t sh->sq_ts_format)) {\n+\t\t\t\t sh->tx_uar, cdev->pdn,\n+\t\t\t\t MLX5_ASO_QUEUE_LOG_DESC,\n+\t\t\t\t sh->sq_ts_format)) {\n \t\t\tmlx5_aso_dereg_mr(sh, &sh->aso_age_mng->aso_sq.mr);\n \t\t\treturn -1;\n \t\t}\n@@ -326,8 +327,9 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,\n \t\tbreak;\n \tcase ASO_OPC_MOD_POLICER:\n \t\tif (mlx5_aso_sq_create(cdev->ctx, &sh->mtrmng->pools_mng.sq, 0,\n-\t\t\t\t sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,\n-\t\t\t\t sh->sq_ts_format))\n+\t\t\t\t sh->tx_uar, cdev->pdn,\n+\t\t\t\t MLX5_ASO_QUEUE_LOG_DESC,\n+\t\t\t\t sh->sq_ts_format))\n \t\t\treturn -1;\n \t\tmlx5_aso_mtr_init_sq(&sh->mtrmng->pools_mng.sq);\n \t\tbreak;\n@@ -337,8 +339,9 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,\n \t\t\t\t &sh->ct_mng->aso_sq.mr, 0))\n \t\t\treturn -1;\n \t\tif (mlx5_aso_sq_create(cdev->ctx, &sh->ct_mng->aso_sq, 0,\n-\t\t\t\tsh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,\n-\t\t\t\tsh->sq_ts_format)) {\n+\t\t\t\t sh->tx_uar, cdev->pdn,\n+\t\t\t\t MLX5_ASO_QUEUE_LOG_DESC,\n+\t\t\t\t sh->sq_ts_format)) {\n \t\t\tmlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);\n \t\t\treturn -1;\n \t\t}\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 7bd4518ca4..1b2d837ddb 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -6467,12 +6467,10 @@ flow_dv_mtr_container_resize(struct rte_eth_dev *dev)\n * NULL otherwise and rte_errno is set.\n */\n static struct mlx5_aso_mtr_pool *\n-flow_dv_mtr_pool_create(struct rte_eth_dev *dev,\n-\t\t\t struct mlx5_aso_mtr **mtr_free)\n+flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_aso_mtr_pools_mng *pools_mng =\n-\t\t\t\t&priv->sh->mtrmng->pools_mng;\n+\tstruct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;\n \tstruct mlx5_aso_mtr_pool *pool = NULL;\n \tstruct mlx5_devx_obj *dcs = NULL;\n \tuint32_t i;\n@@ -6480,7 +6478,8 @@ flow_dv_mtr_pool_create(struct rte_eth_dev *dev,\n \n \tlog_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);\n \tdcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,\n-\t\t\tpriv->sh->pdn, log_obj_size);\n+\t\t\t\t\t\t priv->sh->cdev->pdn,\n+\t\t\t\t\t\t log_obj_size);\n \tif (!dcs) {\n \t\trte_errno = ENODATA;\n \t\treturn NULL;\n@@ -6502,8 +6501,7 @@ flow_dv_mtr_pool_create(struct rte_eth_dev *dev,\n \tpools_mng->n_valid++;\n \tfor (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {\n \t\tpool->mtrs[i].offset = i;\n-\t\tLIST_INSERT_HEAD(&pools_mng->meters,\n-\t\t\t\t\t\t&pool->mtrs[i], next);\n+\t\tLIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);\n \t}\n \tpool->mtrs[0].offset = 0;\n \t*mtr_free = &pool->mtrs[0];\n@@ -11956,7 +11954,7 @@ flow_dv_age_pool_create(struct rte_eth_dev *dev,\n \tuint32_t i;\n \n \tobj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,\n-\t\t\t\t\t\t priv->sh->pdn);\n+\t\t\t\t\t\t priv->sh->cdev->pdn);\n \tif (!obj) {\n \t\trte_errno = ENODATA;\n \t\tDRV_LOG(ERR, \"Failed to create flow_hit_aso_obj using DevX.\");\n@@ -12384,7 +12382,8 @@ flow_dv_ct_pool_create(struct rte_eth_dev *dev,\n \tuint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);\n \n \tobj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,\n-\t\t\t\t\t\tpriv->sh->pdn, log_obj_size);\n+\t\t\t\t\t\t\t priv->sh->cdev->pdn,\n+\t\t\t\t\t\t\t log_obj_size);\n \tif (!obj) {\n \t\trte_errno = ENODATA;\n \t\tDRV_LOG(ERR, \"Failed to create conn_track_offload_obj using DevX.\");\ndiff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\nindex f16f4f6a67..4d884f7295 100644\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ b/drivers/net/mlx5/mlx5_mr.c\n@@ -84,7 +84,7 @@ mlx5_tx_addr2mr_bh(struct mlx5_txq_data *txq, uintptr_t addr)\n \tstruct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;\n \tstruct mlx5_priv *priv = txq_ctrl->priv;\n \n-\treturn mlx5_mr_addr2mr_bh(priv->sh->pd, &priv->mp_id,\n+\treturn mlx5_mr_addr2mr_bh(priv->sh->cdev->pd, &priv->mp_id,\n \t\t\t\t &priv->sh->share_cache, mr_ctrl, addr,\n \t\t\t\t priv->sh->cdev->config.mr_ext_memseg_en);\n }\n@@ -180,7 +180,7 @@ mlx5_mr_update_ext_mp_cb(struct rte_mempool *mp, void *opaque,\n \t\treturn;\n \tDRV_LOG(DEBUG, \"port %u register MR for chunk #%d of mempool (%s)\",\n \t\tdev->data->port_id, mem_idx, mp->name);\n-\tmr = mlx5_create_mr_ext(sh->pd, addr, len, mp->socket_id,\n+\tmr = mlx5_create_mr_ext(sh->cdev->pd, addr, len, mp->socket_id,\n \t\t\t\tsh->share_cache.reg_mr_cb);\n \tif (!mr) {\n \t\tDRV_LOG(WARNING,\n@@ -196,8 +196,8 @@ mlx5_mr_update_ext_mp_cb(struct rte_mempool *mp, void *opaque,\n \tmlx5_mr_insert_cache(&sh->share_cache, mr);\n \trte_rwlock_write_unlock(&sh->share_cache.rwlock);\n \t/* Insert to the local cache table */\n-\tmlx5_mr_addr2mr_bh(sh->pd, &priv->mp_id, &sh->share_cache, mr_ctrl,\n-\t\t\t addr, priv->sh->cdev->config.mr_ext_memseg_en);\n+\tmlx5_mr_addr2mr_bh(sh->cdev->pd, &priv->mp_id, &sh->share_cache,\n+\t\t\t mr_ctrl, addr, sh->cdev->config.mr_ext_memseg_en);\n }\n \n /**\n@@ -256,8 +256,8 @@ mlx5_net_dma_map(struct rte_device *rte_dev, void *addr,\n \t}\n \tpriv = dev->data->dev_private;\n \tsh = priv->sh;\n-\tmr = mlx5_create_mr_ext(sh->pd, (uintptr_t)addr, len, SOCKET_ID_ANY,\n-\t\t\t\tsh->share_cache.reg_mr_cb);\n+\tmr = mlx5_create_mr_ext(sh->cdev->pd, (uintptr_t)addr, len,\n+\t\t\t\tSOCKET_ID_ANY, sh->share_cache.reg_mr_cb);\n \tif (!mr) {\n \t\tDRV_LOG(WARNING,\n \t\t\t\"port %u unable to dma map\", dev->data->port_id);\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 247f36e5d7..43ea890d2b 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1242,8 +1242,8 @@ mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n-\tret = mlx5_mr_mempool_register(&priv->sh->share_cache, priv->sh->pd,\n-\t\t\t\t mp, &priv->mp_id);\n+\tret = mlx5_mr_mempool_register(&priv->sh->share_cache,\n+\t\t\t\t priv->sh->cdev->pd, mp, &priv->mp_id);\n \tif (ret < 0 && rte_errno != EEXIST) {\n \t\tret = rte_errno;\n \t\tDRV_LOG(ERR, \"port %u failed to register a mempool for Multi-Packet RQ\",\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex e93647aafd..cf4fbd3c9f 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -149,7 +149,8 @@ mlx5_rxq_mempool_register(struct mlx5_rxq_ctrl *rxq_ctrl)\n \tfor (s = 0; s < rxq_ctrl->rxq.rxseg_n; s++) {\n \t\tmp = rxq_ctrl->rxq.rxseg[s].mp;\n \t\tret = mlx5_mr_mempool_register(&priv->sh->share_cache,\n-\t\t\t\t\t priv->sh->pd, mp, &priv->mp_id);\n+\t\t\t\t\t priv->sh->cdev->pd, mp,\n+\t\t\t\t\t &priv->mp_id);\n \t\tif (ret < 0 && rte_errno != EEXIST)\n \t\t\treturn ret;\n \t\trte_mempool_mem_iter(mp, mlx5_rxq_mempool_register_cb,\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex 6dd362c48a..fb7b36197c 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -232,7 +232,7 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n \t\t.tis_lst_sz = 1,\n \t\t.tis_num = sh->tis->id,\n \t\t.wq_attr = (struct mlx5_devx_wq_attr){\n-\t\t\t.pd = sh->pdn,\n+\t\t\t.pd = sh->cdev->pdn,\n \t\t\t.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar),\n \t\t},\n \t\t.ts_format = mlx5_ts_format_conv(sh->sq_ts_format),\n@@ -444,7 +444,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)\n \tsq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;\n \tsq_attr.wq_attr.cd_slave = 1;\n \tsq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);\n-\tsq_attr.wq_attr.pd = sh->pdn;\n+\tsq_attr.wq_attr.pd = sh->cdev->pdn;\n \tsq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);\n \tret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj,\n \t\t\t\t log2above(wq->sq_size),\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex e1010beeb5..e927defbf1 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -965,25 +965,4 @@ mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,\n \t*dereg_mr_cb = mlx5_os_dereg_mr;\n }\n \n-/**\n- * Extract pdn of PD object using DevX\n- *\n- * @param[in] pd\n- * Pointer to the DevX PD object.\n- * @param[out] pdn\n- * Pointer to the PD object number variable.\n- *\n- * @return\n- * 0 on success, error value otherwise.\n- */\n-int\n-mlx5_os_get_pdn(void *pd, uint32_t *pdn)\n-{\n-\tif (!pd)\n-\t\treturn -EINVAL;\n-\n-\t*pdn = ((struct mlx5_pd *)pd)->pdn;\n-\treturn 0;\n-}\n-\n const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};\ndiff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex f915a9d047..54d3e64f43 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -187,12 +187,6 @@ mlx5_regex_dev_probe(struct mlx5_common_device *cdev)\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\tpriv->pd = mlx5_glue->alloc_pd(priv->cdev->ctx);\n-\tif (!priv->pd) {\n-\t\tDRV_LOG(ERR, \"can't allocate pd.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n \tpriv->regexdev->dev_ops = &mlx5_regexdev_ops;\n \tpriv->regexdev->enqueue = mlx5_regexdev_enqueue;\n #ifdef HAVE_MLX5_UMR_IMKEY\n@@ -230,8 +224,6 @@ mlx5_regex_dev_probe(struct mlx5_common_device *cdev)\n \treturn 0;\n \n error:\n-\tif (priv->pd)\n-\t\tmlx5_glue->dealloc_pd(priv->pd);\n \tif (priv->uar)\n \t\tmlx5_glue->devx_free_uar(priv->uar);\n \tif (priv->regexdev)\n@@ -264,8 +256,6 @@ mlx5_regex_dev_remove(struct mlx5_common_device *cdev)\n \t\t\t\t\t\t\t NULL);\n \t\tif (priv->mr_scache.cache.table)\n \t\t\tmlx5_mr_release_cache(&priv->mr_scache);\n-\t\tif (priv->pd)\n-\t\t\tmlx5_glue->dealloc_pd(priv->pd);\n \t\tif (priv->uar)\n \t\t\tmlx5_glue->devx_free_uar(priv->uar);\n \t\tif (priv->regexdev)\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 1d19067513..c128b7acbb 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -68,7 +68,6 @@ struct mlx5_regex_priv {\n \t\t\t\tMLX5_RXP_EM_COUNT];\n \tuint32_t nb_engines; /* Number of RegEx engines. */\n \tstruct mlx5dv_devx_uar *uar; /* UAR object. */\n-\tstruct ibv_pd *pd;\n \tTAILQ_ENTRY(mlx5_regex_priv) mem_event_cb;\n \t/**< Called by memory event callback. */\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n@@ -79,26 +78,6 @@ struct mlx5_regex_priv {\n \tuint32_t mmo_regex_sq_cap:1;\n };\n \n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-static inline int\n-regex_get_pdn(void *pd, uint32_t *pdn)\n-{\n-\tstruct mlx5dv_obj obj;\n-\tstruct mlx5dv_pd pd_info;\n-\tint ret = 0;\n-\n-\tobj.pd.in = pd;\n-\tobj.pd.out = &pd_info;\n-\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n-\tif (ret) {\n-\t\tDRV_LOG(DEBUG, \"Fail to get PD object info\");\n-\t\treturn ret;\n-\t}\n-\t*pdn = pd_info.pdn;\n-\treturn 0;\n-}\n-#endif\n-\n /* mlx5_regex.c */\n int mlx5_regex_start(struct rte_regexdev *dev);\n int mlx5_regex_stop(struct rte_regexdev *dev);\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex fa95ce72c9..1136de1d7e 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -138,21 +138,17 @@ regex_ctrl_create_hw_qp(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \tstruct mlx5_devx_qp_attr attr = {\n \t\t.cqn = qp->cq.cq_obj.cq->id,\n \t\t.uar_index = priv->uar->page_id,\n+\t\t.pd = priv->cdev->pdn,\n \t\t.ts_format = mlx5_ts_format_conv(priv->qp_ts_format),\n \t\t.user_index = q_ind,\n \t};\n \tstruct mlx5_regex_hw_qp *qp_obj = &qp->qps[q_ind];\n-\tuint32_t pd_num = 0;\n \tint ret;\n \n \tqp_obj->log_nb_desc = log_nb_desc;\n \tqp_obj->qpn = q_ind;\n \tqp_obj->ci = 0;\n \tqp_obj->pi = 0;\n-\tret = regex_get_pdn(priv->pd, &pd_num);\n-\tif (ret)\n-\t\treturn ret;\n-\tattr.pd = pd_num;\n \tattr.rq_size = 0;\n \tattr.sq_size = RTE_BIT32(MLX5_REGEX_WQE_LOG_NUM(priv->has_umr,\n \t\t\tlog_nb_desc));\ndiff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c\nindex f9d79d3549..575b639752 100644\n--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c\n+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c\n@@ -138,8 +138,8 @@ mlx5_regex_addr2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl,\n \tif (likely(lkey != UINT32_MAX))\n \t\treturn lkey;\n \t/* Take slower bottom-half on miss. */\n-\treturn mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr,\n-\t\t\t\t !!(mbuf->ol_flags & EXT_ATTACHED_MBUF));\n+\treturn mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,\n+\t\t\t\t addr, !!(mbuf->ol_flags & EXT_ATTACHED_MBUF));\n }\n \n \n@@ -639,7 +639,7 @@ setup_qps(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue)\n static int\n setup_buffers(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp)\n {\n-\tstruct ibv_pd *pd = priv->pd;\n+\tstruct ibv_pd *pd = priv->cdev->pd;\n \tuint32_t i;\n \tint err;\n \n@@ -746,12 +746,7 @@ mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id)\n \n \tif (priv->has_umr) {\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\t\tif (regex_get_pdn(priv->pd, &attr.pd)) {\n-\t\t\terr = -rte_errno;\n-\t\t\tDRV_LOG(ERR, \"Failed to get pdn.\");\n-\t\t\tmlx5_regexdev_teardown_fastpath(priv, qp_id);\n-\t\t\treturn err;\n-\t\t}\n+\t\tattr.pd = priv->cdev->pdn;\n #endif\n \t\tfor (i = 0; i < qp->nb_desc; i++) {\n \t\t\tattr.klm_num = MLX5_REGEX_MAX_KLM_NUM;\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c\nindex 2468202ceb..fe68ab0252 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.c\n@@ -188,37 +188,6 @@ mlx5_vdpa_features_set(int vid)\n \treturn 0;\n }\n \n-static int\n-mlx5_vdpa_pd_create(struct mlx5_vdpa_priv *priv)\n-{\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tpriv->pd = mlx5_glue->alloc_pd(priv->cdev->ctx);\n-\tif (priv->pd == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate PD.\");\n-\t\treturn errno ? -errno : -ENOMEM;\n-\t}\n-\tstruct mlx5dv_obj obj;\n-\tstruct mlx5dv_pd pd_info;\n-\tint ret = 0;\n-\n-\tobj.pd.in = priv->pd;\n-\tobj.pd.out = &pd_info;\n-\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Fail to get PD object info.\");\n-\t\tmlx5_glue->dealloc_pd(priv->pd);\n-\t\tpriv->pd = NULL;\n-\t\treturn -errno;\n-\t}\n-\tpriv->pdn = pd_info.pdn;\n-\treturn 0;\n-#else\n-\t(void)priv;\n-\tDRV_LOG(ERR, \"Cannot get pdn - no DV support.\");\n-\treturn -ENOTSUP;\n-#endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n-}\n-\n static int\n mlx5_vdpa_mtu_set(struct mlx5_vdpa_priv *priv)\n {\n@@ -289,10 +258,6 @@ mlx5_vdpa_dev_close(int vid)\n \tmlx5_vdpa_virtqs_release(priv);\n \tmlx5_vdpa_event_qp_global_release(priv);\n \tmlx5_vdpa_mem_dereg(priv);\n-\tif (priv->pd) {\n-\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n-\t\tpriv->pd = NULL;\n-\t}\n \tpriv->configured = 0;\n \tpriv->vid = 0;\n \t/* The mutex may stay locked after event thread cancel - initiate it. */\n@@ -320,8 +285,7 @@ mlx5_vdpa_dev_config(int vid)\n \tif (mlx5_vdpa_mtu_set(priv))\n \t\tDRV_LOG(WARNING, \"MTU cannot be set on device %s.\",\n \t\t\t\tvdev->device->name);\n-\tif (mlx5_vdpa_pd_create(priv) || mlx5_vdpa_mem_register(priv) ||\n-\t mlx5_vdpa_err_event_setup(priv) ||\n+\tif (mlx5_vdpa_mem_register(priv) || mlx5_vdpa_err_event_setup(priv) ||\n \t mlx5_vdpa_virtqs_prepare(priv) || mlx5_vdpa_steer_setup(priv) ||\n \t mlx5_vdpa_cqe_event_setup(priv)) {\n \t\tmlx5_vdpa_dev_close(vid);\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h\nindex 1fe57c72b8..d9a68e701e 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.h\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h\n@@ -131,8 +131,6 @@ struct mlx5_vdpa_priv {\n \tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n \tint vid; /* vhost device id. */\n \tstruct mlx5_hca_vdpa_attr caps;\n-\tuint32_t pdn; /* Protection Domain number. */\n-\tstruct ibv_pd *pd;\n \tuint32_t gpa_mkey_index;\n \tstruct ibv_mr *null_mr;\n \tstruct rte_vhost_memory *vmem;\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nindex 979a2abd41..47f9afe855 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -593,7 +593,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,\n \t\treturn -1;\n \tif (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))\n \t\treturn -1;\n-\tattr.pd = priv->pdn;\n+\tattr.pd = priv->cdev->pdn;\n \tattr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);\n \teqp->fw_qp = mlx5_devx_cmd_create_qp(priv->cdev->ctx, &attr);\n \tif (!eqp->fw_qp) {\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c\nindex 0b0ffeb07d..3e8d9eb9a2 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c\n@@ -39,7 +39,7 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base,\n \tstruct mlx5_devx_mkey_attr mkey_attr = {\n \t\t\t.addr = (uintptr_t)log_base,\n \t\t\t.size = log_size,\n-\t\t\t.pd = priv->pdn,\n+\t\t\t.pd = priv->cdev->pdn,\n \t\t\t.pg_access = 1,\n \t};\n \tstruct mlx5_devx_virtq_attr attr = {\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c\nindex c5cdb3abd7..f551a094cd 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c\n@@ -193,7 +193,7 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv)\n \tif (!mem)\n \t\treturn -rte_errno;\n \tpriv->vmem = mem;\n-\tpriv->null_mr = mlx5_glue->alloc_null_mr(priv->pd);\n+\tpriv->null_mr = mlx5_glue->alloc_null_mr(priv->cdev->pd);\n \tif (!priv->null_mr) {\n \t\tDRV_LOG(ERR, \"Failed to allocate null MR.\");\n \t\tret = -errno;\n@@ -220,7 +220,7 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv)\n \t\tmkey_attr.addr = (uintptr_t)(reg->guest_phys_addr);\n \t\tmkey_attr.size = reg->size;\n \t\tmkey_attr.umem_id = entry->umem->umem_id;\n-\t\tmkey_attr.pd = priv->pdn;\n+\t\tmkey_attr.pd = priv->cdev->pdn;\n \t\tmkey_attr.pg_access = 1;\n \t\tentry->mkey = mlx5_devx_cmd_mkey_create(priv->cdev->ctx,\n \t\t\t\t\t\t\t&mkey_attr);\n@@ -268,7 +268,7 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv)\n \t}\n \tmkey_attr.addr = (uintptr_t)(mem->regions[0].guest_phys_addr);\n \tmkey_attr.size = mem_size;\n-\tmkey_attr.pd = priv->pdn;\n+\tmkey_attr.pd = priv->cdev->pdn;\n \tmkey_attr.umem_id = 0;\n \t/* Must be zero for KLM mode. */\n \tmkey_attr.log_entity_size = mode == MLX5_MKC_ACCESS_MODE_KLM_FBS ?\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\nindex 5ef31de834..cfd50d92f5 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n@@ -322,7 +322,7 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index)\n \tattr.mkey = priv->gpa_mkey_index;\n \tattr.tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id;\n \tattr.queue_index = index;\n-\tattr.pd = priv->pdn;\n+\tattr.pd = priv->cdev->pdn;\n \tattr.hw_latency_mode = priv->hw_latency_mode;\n \tattr.hw_max_latency_us = priv->hw_max_latency_us;\n \tattr.hw_max_pending_comp = priv->hw_max_pending_comp;\n", "prefixes": [ "v3", "10/18" ] }