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GET /api/patches/102306/?format=api
{ "id": 102306, "url": "http://patches.dpdk.org/api/patches/102306/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211019205602.3188203-2-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211019205602.3188203-2-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211019205602.3188203-2-michaelba@nvidia.com", "date": "2021-10-19T20:55:45", "name": "[v3,01/18] net/mlx5/windows: fix miss callback register for mem event", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "01b6ed2af80aa4d3182171e6b94120d24f17e50d", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211019205602.3188203-2-michaelba@nvidia.com/mbox/", "series": [ { "id": 19808, "url": "http://patches.dpdk.org/api/series/19808/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19808", "date": "2021-10-19T20:55:44", "name": "mlx5: sharing global MR cache between drivers", "version": 3, "mbox": "http://patches.dpdk.org/series/19808/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102306/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/102306/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E9CEAA0C43;\n\tTue, 19 Oct 2021 22:56:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D19B941100;\n\tTue, 19 Oct 2021 22:56:34 +0200 (CEST)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1anam02on2070.outbound.protection.outlook.com [40.107.96.70])\n by mails.dpdk.org (Postfix) with ESMTP id 915C24003E;\n Tue, 19 Oct 2021 22:56:30 +0200 (CEST)", "from BN9PR03CA0808.namprd03.prod.outlook.com (2603:10b6:408:13f::33)\n by BL0PR12MB4865.namprd12.prod.outlook.com (2603:10b6:208:17c::8)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>,\n Michael Baum <michaelba@oss.nvidia.com>, <stable@dpdk.org>", "Date": "Tue, 19 Oct 2021 23:55:45 +0300", "Message-ID": "<20211019205602.3188203-2-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211019205602.3188203-1-michaelba@nvidia.com>", "References": "<20211006220350.2357487-1-michaelba@nvidia.com>\n <20211019205602.3188203-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "3812ea0d-674c-40ad-cd19-08d99342ebfa", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB4865:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB4865E96447810B238E57DF22CCBD9@BL0PR12MB4865.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:5516;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Klo1Xc56+UASepZ7XFTeTWf1Fm85Z5nyGzoRWR99YrKOrj78V8XWVKjRvW3f6PFuiPgMrjU+NiikhNdF7FQwLZdz05GYDx2RjFpxVBgeVB6ecqP2o6I80um2BSituPBmYHAXyyeSClseTxMp/pJhTb/HDa1rJg3QVUzg2VtQCoOXGtUjAYqLOOFJpiN9sF3GOlJnHijpPfCHdBQe5fdC5Ly6Bc5J7Ph80BcRjPzlqsHr/MR5aNEa6+7B1q6nAysmaznVqDFnI0/WPrIm5/842bIRocqezEK6UtXe33sihyg8oDMsTLX0xNX7bJq/A+4I+xliFp7uY2ggbmm5rXxV6V3MEc3aCLEKrt0APztnvK0QrW1M/zk8Zw/MsWlER5zc2+QhrVPoFbY/2PqDeMGiOFLLaZhexy9LcP0QmRFdJ3/pvDQ2OkvFmL/4UZbveILo0goHOmHYuResT4lXoLGJoPbS7czTMX3g5f4dqD+gI08liMmlaNpH5WPbUPEHpf0i7gda3INZTg3z1OnsDUHloSHN/NGUSz1kcAEpM25dMuBvjLKbLJ54eHe8vgf8sx/QItGnr4+m/zxpSTDpimsVz3yjp1DayfT8y6zUliOLCxq4bHd3DZuQ/ckrVwVEOj8D0mphYjTplAMyndpuTD8ETcidTMvcbI1CK5HS5hyMB8yt6/hV7j+WzGxc43wa4E3oEyJenFRPGtObIgBx0Wjw5Q==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(5660300002)(36860700001)(47076005)(8676002)(4326008)(186003)(16526019)(70586007)(70206006)(83380400001)(6286002)(2906002)(7696005)(336012)(26005)(2876002)(8936002)(82310400003)(316002)(2616005)(55016002)(426003)(86362001)(54906003)(1076003)(36756003)(356005)(6916009)(7636003)(508600001)(6666004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Oct 2021 20:56:27.9266 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3812ea0d-674c-40ad-cd19-08d99342ebfa", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT012.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB4865", "Subject": "[dpdk-dev] [PATCH v3 01/18] net/mlx5/windows: fix miss callback\n register for mem event", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nIn device initialization, the driver registers to free hugepages events.\nWhen husepage is released, this callback frees all its related MRs.\n\nIn Windows initialization, this callback is not registered what may\ncause to use invalid memory.\n\nThis patch adds memory event callback registration in Windows\ninitialization.\n\nFixes: 980826dc6f0f (\"net/mlx5: probe on Windows\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@oss.nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/windows/mlx5_os.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 149253d174..459414d5c2 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -122,8 +122,21 @@ mlx5_init_shared_data(void)\n static int\n mlx5_init_once(void)\n {\n+\tstruct mlx5_shared_data *sd;\n+\n \tif (mlx5_init_shared_data())\n \t\treturn -rte_errno;\n+\tsd = mlx5_shared_data;\n+\trte_spinlock_lock(&sd->lock);\n+\tMLX5_ASSERT(sd);\n+\tif (!sd->init_done) {\n+\t\tLIST_INIT(&sd->mem_event_cb_list);\n+\t\trte_rwlock_init(&sd->mem_event_rwlock);\n+\t\trte_mem_event_callback_register(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\tmlx5_mr_mem_event_cb, NULL);\n+\t\tsd->init_done = true;\n+\t}\n+\trte_spinlock_unlock(&sd->lock);\n \treturn 0;\n }\n \n", "prefixes": [ "v3", "01/18" ] }