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GET /api/patches/102012/?format=api
{ "id": 102012, "url": "http://patches.dpdk.org/api/patches/102012/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211018123835.1080174-8-conor.walsh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211018123835.1080174-8-conor.walsh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211018123835.1080174-8-conor.walsh@intel.com", "date": "2021-10-18T12:38:30", "name": "[v8,07/12] dma/ioat: add data path completion functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9fd7403703e835864272baa8c31ecb51f8ef82a1", "submitter": { "id": 1935, "url": "http://patches.dpdk.org/api/people/1935/?format=api", "name": "Conor Walsh", "email": "conor.walsh@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211018123835.1080174-8-conor.walsh@intel.com/mbox/", "series": [ { "id": 19738, "url": "http://patches.dpdk.org/api/series/19738/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19738", "date": "2021-10-18T12:38:23", "name": "dma: add dmadev driver for ioat devices", "version": 8, "mbox": "http://patches.dpdk.org/series/19738/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102012/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102012/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3984AA0C43;\n\tMon, 18 Oct 2021 14:39:27 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D8ECB41151;\n\tMon, 18 Oct 2021 14:39:00 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 6F8C941151\n for <dev@dpdk.org>; Mon, 18 Oct 2021 14:38:59 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Oct 2021 05:38:59 -0700", "from silpixa00401160.ir.intel.com ([10.55.129.96])\n by orsmga005.jf.intel.com with ESMTP; 18 Oct 2021 05:38:56 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10140\"; a=\"228117662\"", "E=Sophos;i=\"5.85,382,1624345200\"; d=\"scan'208\";a=\"228117662\"", "E=Sophos;i=\"5.85,382,1624345200\"; d=\"scan'208\";a=\"661361125\"" ], "X-ExtLoop1": "1", "From": "Conor Walsh <conor.walsh@intel.com>", "To": "bruce.richardson@intel.com, thomas@monjalon.net, fengchengwen@huawei.com,\n jerinj@marvell.com, kevin.laatz@intel.com", "Cc": "dev@dpdk.org,\n\tConor Walsh <conor.walsh@intel.com>", "Date": "Mon, 18 Oct 2021 12:38:30 +0000", "Message-Id": "<20211018123835.1080174-8-conor.walsh@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211018123835.1080174-1-conor.walsh@intel.com>", "References": "<20210827172550.1522362-1-conor.walsh@intel.com>\n <20211018123835.1080174-1-conor.walsh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v8 07/12] dma/ioat: add data path completion\n functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add the data path functions for gathering completed operations\nfrom IOAT devices.\n\nSigned-off-by: Conor Walsh <conor.walsh@intel.com>\nSigned-off-by: Kevin Laatz <kevin.laatz@intel.com>\nAcked-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n doc/guides/dmadevs/ioat.rst | 33 +++++++-\n drivers/dma/ioat/ioat_dmadev.c | 141 +++++++++++++++++++++++++++++++++\n 2 files changed, 173 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/dmadevs/ioat.rst b/doc/guides/dmadevs/ioat.rst\nindex 9ee4e372a8..9ac90e3108 100644\n--- a/doc/guides/dmadevs/ioat.rst\n+++ b/doc/guides/dmadevs/ioat.rst\n@@ -90,7 +90,38 @@ Performing Data Copies\n ~~~~~~~~~~~~~~~~~~~~~~~\n \n Refer to the :ref:`Enqueue / Dequeue APIs <dmadev_enqueue_dequeue>` section of the dmadev library\n-documentation for details on operation enqueue and submission API usage.\n+documentation for details on operation enqueue, submission and completion API usage.\n \n It is expected that, for efficiency reasons, a burst of operations will be enqueued to the\n device via multiple enqueue calls between calls to the ``rte_dma_submit()`` function.\n+\n+When gathering completions, ``rte_dma_completed()`` should be used, up until the point an error\n+occurs with an operation. If an error was encountered, ``rte_dma_completed_status()`` must be used\n+to reset the device and continue processing operations. This function will also gather the status\n+of each individual operation which is filled in to the ``status`` array provided as parameter\n+by the application.\n+\n+The status codes supported by IOAT are:\n+\n+* ``RTE_DMA_STATUS_SUCCESSFUL``: The operation was successful.\n+* ``RTE_DMA_STATUS_INVALID_SRC_ADDR``: The operation failed due to an invalid source address.\n+* ``RTE_DMA_STATUS_INVALID_DST_ADDR``: The operation failed due to an invalid destination address.\n+* ``RTE_DMA_STATUS_INVALID_LENGTH``: The operation failed due to an invalid descriptor length.\n+* ``RTE_DMA_STATUS_DESCRIPTOR_READ_ERROR``: The device could not read the descriptor.\n+* ``RTE_DMA_STATUS_ERROR_UNKNOWN``: The operation failed due to an unspecified error.\n+\n+The following code shows how to retrieve the number of successfully completed\n+copies within a burst and then uses ``rte_dma_completed_status()`` to check\n+which operation failed and reset the device to continue processing operations:\n+\n+.. code-block:: C\n+\n+ enum rte_dma_status_code status[COMP_BURST_SZ];\n+ uint16_t count, idx, status_count;\n+ bool error = 0;\n+\n+ count = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error);\n+\n+ if (error){\n+ status_count = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ, &idx, status);\n+ }\ndiff --git a/drivers/dma/ioat/ioat_dmadev.c b/drivers/dma/ioat/ioat_dmadev.c\nindex 4d00fec5c8..0318f67772 100644\n--- a/drivers/dma/ioat/ioat_dmadev.c\n+++ b/drivers/dma/ioat/ioat_dmadev.c\n@@ -6,6 +6,7 @@\n #include <rte_dmadev_pmd.h>\n #include <rte_malloc.h>\n #include <rte_prefetch.h>\n+#include <rte_errno.h>\n \n #include \"ioat_internal.h\"\n \n@@ -362,6 +363,144 @@ ioat_dev_dump(const struct rte_dma_dev *dev, FILE *f)\n \treturn __dev_dump(dev->fp_obj->dev_private, f);\n }\n \n+/* Returns the index of the last completed operation. */\n+static inline uint16_t\n+__get_last_completed(const struct ioat_dmadev *ioat, int *state)\n+{\n+\t/* Status register contains the address of the completed operation */\n+\tuint64_t status = ioat->status;\n+\n+\t/* lower 3 bits indicate \"transfer status\" : active, idle, halted.\n+\t * We can ignore bit 0.\n+\t */\n+\t*state = status & IOAT_CHANSTS_STATUS;\n+\n+\t/* If we are just after recovering from an error the address returned by\n+\t * status will be 0, in this case we return the offset - 1 as the last\n+\t * completed. If not return the status value minus the chainaddr which\n+\t * gives us an offset into the ring. Right shifting by 6 (divide by 64)\n+\t * gives the index of the completion from the HW point of view and adding\n+\t * the offset translates the ring index from HW to SW point of view.\n+\t */\n+\tif ((status & ~IOAT_CHANSTS_STATUS) == 0)\n+\t\treturn ioat->offset - 1;\n+\n+\treturn (status - ioat->ring_addr) >> 6;\n+}\n+\n+/* Translates IOAT ChanERRs to DMA error codes. */\n+static inline enum rte_dma_status_code\n+__translate_status_ioat_to_dma(uint32_t chanerr)\n+{\n+\tif (chanerr & IOAT_CHANERR_INVALID_SRC_ADDR_MASK)\n+\t\treturn RTE_DMA_STATUS_INVALID_SRC_ADDR;\n+\telse if (chanerr & IOAT_CHANERR_INVALID_DST_ADDR_MASK)\n+\t\treturn RTE_DMA_STATUS_INVALID_DST_ADDR;\n+\telse if (chanerr & IOAT_CHANERR_INVALID_LENGTH_MASK)\n+\t\treturn RTE_DMA_STATUS_INVALID_LENGTH;\n+\telse if (chanerr & IOAT_CHANERR_DESCRIPTOR_READ_ERROR_MASK)\n+\t\treturn RTE_DMA_STATUS_DESCRIPTOR_READ_ERROR;\n+\telse\n+\t\treturn RTE_DMA_STATUS_ERROR_UNKNOWN;\n+}\n+\n+/* Returns details of operations that have been completed. */\n+static uint16_t\n+ioat_completed(void *dev_private, uint16_t qid __rte_unused, const uint16_t max_ops,\n+\t\tuint16_t *last_idx, bool *has_error)\n+{\n+\tstruct ioat_dmadev *ioat = dev_private;\n+\n+\tconst unsigned short mask = (ioat->qcfg.nb_desc - 1);\n+\tconst unsigned short read = ioat->next_read;\n+\tunsigned short last_completed, count;\n+\tint state, fails = 0;\n+\n+\t/* Do not do any work if there is an uncleared error. */\n+\tif (ioat->failure != 0) {\n+\t\t*has_error = true;\n+\t\t*last_idx = ioat->next_read - 2;\n+\t\treturn 0;\n+\t}\n+\n+\tlast_completed = __get_last_completed(ioat, &state);\n+\tcount = (last_completed + 1 - read) & mask;\n+\n+\t/* Cap count at max_ops or set as last run in batch. */\n+\tif (count > max_ops)\n+\t\tcount = max_ops;\n+\n+\tif (count == max_ops || state != IOAT_CHANSTS_HALTED) {\n+\t\tioat->next_read = read + count;\n+\t\t*last_idx = ioat->next_read - 1;\n+\t} else {\n+\t\t*has_error = true;\n+\t\trte_errno = EIO;\n+\t\tioat->failure = ioat->regs->chanerr;\n+\t\tioat->next_read = read + count + 1;\n+\t\tif (__ioat_recover(ioat) != 0) {\n+\t\t\tIOAT_PMD_ERR(\"Device HALTED and could not be recovered\\n\");\n+\t\t\t__dev_dump(dev_private, stdout);\n+\t\t\treturn 0;\n+\t\t}\n+\t\t__submit(ioat);\n+\t\tfails++;\n+\t\t*last_idx = ioat->next_read - 2;\n+\t}\n+\n+\treturn count;\n+}\n+\n+/* Returns detailed status information about operations that have been completed. */\n+static uint16_t\n+ioat_completed_status(void *dev_private, uint16_t qid __rte_unused,\n+\t\tuint16_t max_ops, uint16_t *last_idx, enum rte_dma_status_code *status)\n+{\n+\tstruct ioat_dmadev *ioat = dev_private;\n+\n+\tconst unsigned short mask = (ioat->qcfg.nb_desc - 1);\n+\tconst unsigned short read = ioat->next_read;\n+\tunsigned short count, last_completed;\n+\tuint64_t fails = 0;\n+\tint state, i;\n+\n+\tlast_completed = __get_last_completed(ioat, &state);\n+\tcount = (last_completed + 1 - read) & mask;\n+\n+\tfor (i = 0; i < RTE_MIN(count + 1, max_ops); i++)\n+\t\tstatus[i] = RTE_DMA_STATUS_SUCCESSFUL;\n+\n+\t/* Cap count at max_ops or set as last run in batch. */\n+\tif (count > max_ops)\n+\t\tcount = max_ops;\n+\n+\tif (count == max_ops || state != IOAT_CHANSTS_HALTED)\n+\t\tioat->next_read = read + count;\n+\telse {\n+\t\trte_errno = EIO;\n+\t\tstatus[count] = __translate_status_ioat_to_dma(ioat->regs->chanerr);\n+\t\tcount++;\n+\t\tioat->next_read = read + count;\n+\t\tif (__ioat_recover(ioat) != 0) {\n+\t\t\tIOAT_PMD_ERR(\"Device HALTED and could not be recovered\\n\");\n+\t\t\t__dev_dump(dev_private, stdout);\n+\t\t\treturn 0;\n+\t\t}\n+\t\t__submit(ioat);\n+\t\tfails++;\n+\t}\n+\n+\tif (ioat->failure > 0) {\n+\t\tstatus[0] = __translate_status_ioat_to_dma(ioat->failure);\n+\t\tcount = RTE_MIN(count + 1, max_ops);\n+\t\tioat->failure = 0;\n+\t}\n+\n+\t*last_idx = ioat->next_read - 1;\n+\n+\treturn count;\n+}\n+\n /* Create a DMA device. */\n static int\n ioat_dmadev_create(const char *name, struct rte_pci_device *dev)\n@@ -398,6 +537,8 @@ ioat_dmadev_create(const char *name, struct rte_pci_device *dev)\n \n \tdmadev->dev_ops = &ioat_dmadev_ops;\n \n+\tdmadev->fp_obj->completed = ioat_completed;\n+\tdmadev->fp_obj->completed_status = ioat_completed_status;\n \tdmadev->fp_obj->copy = ioat_enqueue_copy;\n \tdmadev->fp_obj->fill = ioat_enqueue_fill;\n \tdmadev->fp_obj->submit = ioat_submit;\n", "prefixes": [ "v8", "07/12" ] }